1 /*- 2 ******************************************************************************** 3 Copyright (C) 2015 Annapurna Labs Ltd. 4 5 This file may be licensed under the terms of the Annapurna Labs Commercial 6 License Agreement. 7 8 Alternatively, this file can be distributed under the terms of the GNU General 9 Public License V2 as published by the Free Software Foundation and can be 10 found at http://www.gnu.org/licenses/gpl-2.0.html 11 12 Alternatively, redistribution and use in source and binary forms, with or 13 without modification, are permitted provided that the following conditions are 14 met: 15 16 * Redistributions of source code must retain the above copyright notice, 17 this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20 notice, this list of conditions and the following disclaimer in 21 the documentation and/or other materials provided with the 22 distribution. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35 *******************************************************************************/ 36 37 #ifndef __AL_HAL_UNIT_ADAPTER_REGS_H__ 38 #define __AL_HAL_UNIT_ADAPTER_REGS_H__ 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 #define AL_PCI_COMMAND 0x04 /* 16 bits */ 45 #define AL_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 46 #define AL_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 47 #define AL_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 48 49 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ 50 51 #define AL_PCI_BASE_ADDRESS_SPACE_IO 0x01 52 #define AL_PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 53 #define AL_PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 54 #define AL_PCI_BASE_ADDRESS_DEVICE_ID 0x0c 55 56 #define AL_PCI_BASE_ADDRESS_0 0x10 57 #define AL_PCI_BASE_ADDRESS_0_HI 0x14 58 #define AL_PCI_BASE_ADDRESS_2 0x18 59 #define AL_PCI_BASE_ADDRESS_2_HI 0x1c 60 #define AL_PCI_BASE_ADDRESS_4 0x20 61 #define AL_PCI_BASE_ADDRESS_4_HI 0x24 62 63 #define AL_PCI_EXP_ROM_BASE_ADDRESS 0x30 64 65 #define AL_PCI_AXI_CFG_AND_CTR_0 0x110 66 #define AL_PCI_AXI_CFG_AND_CTR_1 0x130 67 #define AL_PCI_AXI_CFG_AND_CTR_2 0x150 68 #define AL_PCI_AXI_CFG_AND_CTR_3 0x170 69 70 #define AL_PCI_APP_CONTROL 0x220 71 72 #define AL_PCI_SRIOV_TOTAL_AND_INITIAL_VFS 0x30c 73 74 #define AL_PCI_VF_BASE_ADDRESS_0 0x324 75 76 77 #define AL_PCI_EXP_CAP_BASE 0x40 78 #define AL_PCI_EXP_DEVCAP 4 /* Device capabilities */ 79 #define AL_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ 80 #define AL_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ 81 #define AL_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ 82 #define AL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ 83 #define AL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ 84 #define AL_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ 85 #define AL_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ 86 #define AL_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ 87 #define AL_PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */ 88 #define AL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ 89 #define AL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ 90 #define AL_PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ 91 #define AL_PCI_EXP_DEVCTL 8 /* Device Control */ 92 #define AL_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ 93 #define AL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ 94 #define AL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ 95 #define AL_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ 96 #define AL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 97 #define AL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ 98 #define AL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ 99 #define AL_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ 100 #define AL_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ 101 #define AL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ 102 #define AL_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ 103 #define AL_PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ 104 #define AL_PCI_EXP_DEVSTA 0xA /* Device Status */ 105 #define AL_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ 106 #define AL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ 107 #define AL_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ 108 #define AL_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */ 109 #define AL_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ 110 #define AL_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ 111 #define AL_PCI_EXP_LNKCAP 0xC /* Link Capabilities */ 112 #define AL_PCI_EXP_LNKCAP_SLS 0xf /* Supported Link Speeds */ 113 #define AL_PCI_EXP_LNKCAP_SLS_2_5GB 0x1 /* LNKCAP2 SLS Vector bit 0 (2.5GT/s) */ 114 #define AL_PCI_EXP_LNKCAP_SLS_5_0GB 0x2 /* LNKCAP2 SLS Vector bit 1 (5.0GT/s) */ 115 #define AL_PCI_EXP_LNKCAP_MLW 0x3f0 /* Maximum Link Width */ 116 #define AL_PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ 117 #define AL_PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ 118 #define AL_PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ 119 #define AL_PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */ 120 #define AL_PCI_EXP_LNKCAP_SDERC 0x80000 /* Surprise Down Error Reporting Capable */ 121 #define AL_PCI_EXP_LNKCAP_DLLLARC 0x100000 /* Data Link Layer Link Active Reporting Capable */ 122 #define AL_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */ 123 #define AL_PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ 124 125 #define AL_PCI_EXP_LNKCTL 0x10 /* Link Control */ 126 #define AL_PCI_EXP_LNKCTL_LNK_DIS 0x4 /* Link Disable Status */ 127 #define AL_PCI_EXP_LNKCTL_LNK_RTRN 0x5 /* Link Retrain Status */ 128 129 #define AL_PCI_EXP_LNKSTA 0x12 /* Link Status */ 130 #define AL_PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ 131 #define AL_PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */ 132 #define AL_PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */ 133 #define AL_PCI_EXP_LNKSTA_CLS_8_0GB 0x03 /* Current Link Speed 8.0GT/s */ 134 #define AL_PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */ 135 #define AL_PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ 136 #define AL_PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ 137 #define AL_PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ 138 #define AL_PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ 139 #define AL_PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ 140 #define AL_PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ 141 142 #define AL_PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */ 143 144 #define AL_PCI_MSIX_MSGCTRL 0 /* MSIX message control reg */ 145 #define AL_PCI_MSIX_MSGCTRL_TBL_SIZE 0x7ff /* MSIX table size */ 146 #define AL_PCI_MSIX_MSGCTRL_TBL_SIZE_SHIFT 16 /* MSIX table size shift */ 147 #define AL_PCI_MSIX_MSGCTRL_EN 0x80000000 /* MSIX enable */ 148 #define AL_PCI_MSIX_MSGCTRL_MASK 0x40000000 /* MSIX mask */ 149 150 #define AL_PCI_MSIX_TABLE 0x4 /* MSIX table offset and bar reg */ 151 #define AL_PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* MSIX table offset */ 152 #define AL_PCI_MSIX_TABLE_BAR 0x7 /* MSIX table BAR */ 153 154 #define AL_PCI_MSIX_PBA 0x8 /* MSIX pba offset and bar reg */ 155 #define AL_PCI_MSIX_PBA_OFFSET 0xfffffff8 /* MSIX pba offset */ 156 #define AL_PCI_MSIX_PBA_BAR 0x7 /* MSIX pba BAR */ 157 158 159 /* Adapter power management register 0 */ 160 #define AL_ADAPTER_PM_0 0x80 161 #define AL_ADAPTER_PM_0_PM_NEXT_CAP_MASK 0xff00 162 #define AL_ADAPTER_PM_0_PM_NEXT_CAP_SHIFT 8 163 #define AL_ADAPTER_PM_0_PM_NEXT_CAP_VAL_MSIX 0x90 164 165 /* Adapter power management register 1 */ 166 #define AL_ADAPTER_PM_1 0x84 167 #define AL_ADAPTER_PM_1_PME_EN 0x100 /* PM enable */ 168 #define AL_ADAPTER_PM_1_PWR_STATE_MASK 0x3 /* PM state mask */ 169 #define AL_ADAPTER_PM_1_PWR_STATE_D3 0x3 /* PM D3 state */ 170 171 /* Sub Master Configuration & Control */ 172 #define AL_ADAPTER_SMCC 0x110 173 #define AL_ADAPTER_SMCC_CONF_2 0x114 174 175 /* Interrupt_Cause register */ 176 #define AL_ADAPTER_INT_CAUSE 0x1B0 177 #define AL_ADAPTER_INT_CAUSE_WR_ERR AL_BIT(1) 178 #define AL_ADAPTER_INT_CAUSE_RD_ERR AL_BIT(0) 179 180 /* AXI_Master_Write_Error_Attribute_Latch register */ 181 /* AXI_Master_Read_Error_Attribute_Latch register */ 182 #define AL_ADAPTER_AXI_MSTR_WR_ERR_ATTR 0x1B4 183 #define AL_ADAPTER_AXI_MSTR_RD_ERR_ATTR 0x1B8 184 185 #define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_STAT_MASK AL_FIELD_MASK(1, 0) 186 #define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_STAT_SHIFT 0 187 #define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_MSTR_ID_MASK AL_FIELD_MASK(4, 2) 188 #define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_MSTR_ID_SHIFT 2 189 #define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_ADDR_TO AL_BIT(8) 190 #define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_ERR AL_BIT(9) 191 #define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_TO AL_BIT(10) 192 #define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_ERR_BLK AL_BIT(11) 193 #define AL_ADAPTER_AXI_MSTR_RD_ERR_ATTR_RD_PARITY_ERR AL_BIT(12) 194 195 /* Interrupt_Cause_mask register */ 196 #define AL_ADAPTER_INT_CAUSE_MASK 0x1BC 197 #define AL_ADAPTER_INT_CAUSE_MASK_WR_ERR AL_BIT(1) 198 #define AL_ADAPTER_INT_CAUSE_MASK_RD_ERR AL_BIT(0) 199 200 /* AXI_Master_write_error_address_Latch register */ 201 #define AL_ADAPTER_AXI_MSTR_WR_ERR_LO_LATCH 0x1C0 202 203 /* AXI_Master_write_error_address_high_Latch register */ 204 #define AL_ADAPTER_AXI_MSTR_WR_ERR_HI_LATCH 0x1C4 205 206 /* AXI_Master_read_error_address_Latch register */ 207 #define AL_ADAPTER_AXI_MSTR_RD_ERR_LO_LATCH 0x1C8 208 209 /* AXI_Master_read_error_address_high_Latch register */ 210 #define AL_ADAPTER_AXI_MSTR_RD_ERR_HI_LATCH 0x1CC 211 212 /* AXI_Master_Timeout register */ 213 #define AL_ADAPTER_AXI_MSTR_TO 0x1D0 214 #define AL_ADAPTER_AXI_MSTR_TO_WR_MASK AL_FIELD_MASK(31, 16) 215 #define AL_ADAPTER_AXI_MSTR_TO_WR_SHIFT 16 216 #define AL_ADAPTER_AXI_MSTR_TO_RD_MASK AL_FIELD_MASK(15, 0) 217 #define AL_ADAPTER_AXI_MSTR_TO_RD_SHIFT 0 218 219 /* 220 * Generic control registers 221 */ 222 223 /* Control 0 */ 224 #define AL_ADAPTER_GENERIC_CONTROL_0 0x1E0 225 /* Control 2 */ 226 #define AL_ADAPTER_GENERIC_CONTROL_2 0x1E8 227 /* Control 3 */ 228 #define AL_ADAPTER_GENERIC_CONTROL_3 0x1EC 229 /* Control 9 */ 230 #define AL_ADAPTER_GENERIC_CONTROL_9 0x218 231 /* Control 10 */ 232 #define AL_ADAPTER_GENERIC_CONTROL_10 0x21C 233 /* Control 11 */ 234 #define AL_ADAPTER_GENERIC_CONTROL_11 0x220 235 /* Control 12 */ 236 #define AL_ADAPTER_GENERIC_CONTROL_12 0x224 237 /* Control 13 */ 238 #define AL_ADAPTER_GENERIC_CONTROL_13 0x228 239 /* Control 14 */ 240 #define AL_ADAPTER_GENERIC_CONTROL_14 0x22C 241 /* Control 15 */ 242 #define AL_ADAPTER_GENERIC_CONTROL_15 0x230 243 /* Control 16 */ 244 #define AL_ADAPTER_GENERIC_CONTROL_16 0x234 245 /* Control 17 */ 246 #define AL_ADAPTER_GENERIC_CONTROL_17 0x238 247 /* Control 18 */ 248 #define AL_ADAPTER_GENERIC_CONTROL_18 0x23C 249 /* Control 19 */ 250 #define AL_ADAPTER_GENERIC_CONTROL_19 0x240 251 252 /* Enable clock gating */ 253 #define AL_ADAPTER_GENERIC_CONTROL_0_CLK_GATE_EN 0x01 254 /* When set, all transactions through the PCI conf & mem BARs get timeout */ 255 #define AL_ADAPTER_GENERIC_CONTROL_0_ADAPTER_DIS 0x40 256 #define AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC AL_BIT(18) 257 #define AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC_ON_FLR AL_BIT(26) 258 259 /* 260 * SATA registers only 261 */ 262 /* Select 125MHz free running clock from IOFAB main PLL as SATA OOB clock 263 * instead of using power management ref clock 264 */ 265 #define AL_ADAPTER_GENERIC_CONTROL_10_SATA_OOB_CLK_SEL AL_BIT(26) 266 /* AXUSER selection and value per bit (1 = address, 0 = register) */ 267 /* Rx */ 268 #define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_VAL_MASK AL_FIELD_MASK(15, 0) 269 #define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_VAL_SHIFT 0 270 #define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_SEL_MASK AL_FIELD_MASK(31, 16) 271 #define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_SEL_SHIFT 16 272 /* Tx */ 273 #define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_VAL_MASK AL_FIELD_MASK(15, 0) 274 #define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_VAL_SHIFT 0 275 #define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_SEL_MASK AL_FIELD_MASK(31, 16) 276 #define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_SEL_SHIFT 16 277 /* Central VMID enabler. If set, then each entry will be used as programmed */ 278 #define AL_ADPTR_GEN_CTL_14_SATA_MSIX_VMID_SEL AL_BIT(0) 279 /* Allow access to store VMID values per entry */ 280 #define AL_ADPTR_GEN_CTL_14_SATA_MSIX_VMID_ACCESS_EN AL_BIT(1) 281 /* VMID Address select */ 282 /* Tx */ 283 #define AL_ADPTR_GEN_CTL_14_SATA_VM_ARADDR_SEL_MASK AL_FIELD_MASK(13, 8) 284 #define AL_ADPTR_GEN_CTL_14_SATA_VM_ARADDR_SEL_SHIFT 8 285 /* Rx */ 286 #define AL_ADPTR_GEN_CTL_14_SATA_VM_AWADDR_SEL_MASK AL_FIELD_MASK(21, 16) 287 #define AL_ADPTR_GEN_CTL_14_SATA_VM_AWADDR_SEL_SHIFT 16 288 /* Address Value */ 289 /* Rx */ 290 #define AL_ADPTR_GEN_CTL_15_SATA_VM_AWDDR_HI AL_FIELD_MASK(31, 0) 291 /* Tx */ 292 #define AL_ADPTR_GEN_CTL_16_SATA_VM_ARDDR_HI AL_FIELD_MASK(31, 0) 293 294 /* 295 * ROB registers 296 */ 297 /* Read ROB_Enable, when disabled the read ROB is bypassed */ 298 #define AL_ADPTR_GEN_CTL_19_READ_ROB_EN AL_BIT(0) 299 /* Read force in-order of every read transaction */ 300 #define AL_ADPTR_GEN_CTL_19_READ_ROB_FORCE_INORDER AL_BIT(1) 301 /* Read software reset */ 302 #define AL_ADPTR_GEN_CTL_19_READ_ROB_SW_RESET AL_BIT(15) 303 /* Write ROB_Enable, when disabled_the_Write ROB is bypassed */ 304 #define AL_ADPTR_GEN_CTL_19_WRITE_ROB_EN AL_BIT(16) 305 /* Write force in-order of every write transaction */ 306 #define AL_ADPTR_GEN_CTL_19_WRITE_ROB_FORCE_INORDER AL_BIT(17) 307 /* Write software reset */ 308 #define AL_ADPTR_GEN_CTL_19_WRITE_ROB_SW_RESET AL_BIT(31) 309 310 #ifdef __cplusplus 311 } 312 #endif 313 314 #endif 315