1 /*- 2 ******************************************************************************* 3 Copyright (C) 2015 Annapurna Labs Ltd. 4 5 This file may be licensed under the terms of the Annapurna Labs Commercial 6 License Agreement. 7 8 Alternatively, this file can be distributed under the terms of the GNU General 9 Public License V2 as published by the Free Software Foundation and can be 10 found at http://www.gnu.org/licenses/gpl-2.0.html 11 12 Alternatively, redistribution and use in source and binary forms, with or 13 without modification, are permitted provided that the following conditions are 14 met: 15 16 * Redistributions of source code must retain the above copyright notice, 17 this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20 notice, this list of conditions and the following disclaimer in 21 the documentation and/or other materials provided with the 22 distribution. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35 *******************************************************************************/ 36 37 /** 38 * @file al_hal_udma_regs_s2m.h 39 * 40 * @brief C Header file for the UDMA S2M registers 41 * 42 */ 43 44 #ifndef __AL_HAL_UDMA_S2M_REG_H 45 #define __AL_HAL_UDMA_S2M_REG_H 46 47 #include "al_hal_plat_types.h" 48 49 #ifdef __cplusplus 50 extern "C" { 51 #endif 52 /* 53 * Unit Registers 54 */ 55 56 57 58 struct udma_axi_s2m { 59 /* [0x0] Data write master configuration */ 60 uint32_t data_wr_cfg_1; 61 /* [0x4] Data write master configuration */ 62 uint32_t data_wr_cfg_2; 63 /* [0x8] Descriptor read master configuration */ 64 uint32_t desc_rd_cfg_4; 65 /* [0xc] Descriptor read master configuration */ 66 uint32_t desc_rd_cfg_5; 67 /* [0x10] Completion write master configuration */ 68 uint32_t comp_wr_cfg_1; 69 /* [0x14] Completion write master configuration */ 70 uint32_t comp_wr_cfg_2; 71 /* [0x18] Data write master configuration */ 72 uint32_t data_wr_cfg; 73 /* [0x1c] Descriptors read master configuration */ 74 uint32_t desc_rd_cfg_3; 75 /* [0x20] Completion descriptors write master configuration */ 76 uint32_t desc_wr_cfg_1; 77 /* [0x24] AXI outstanding read configuration */ 78 uint32_t ostand_cfg_rd; 79 /* [0x28] AXI outstanding write configuration */ 80 uint32_t ostand_cfg_wr; 81 uint32_t rsrvd[53]; 82 }; 83 struct udma_s2m { 84 /* 85 * [0x0] DMA state 86 * 00 - No pending tasks 87 * 01 – Normal (active) 88 * 10 – Abort (error condition) 89 * 11 – Reserved 90 */ 91 uint32_t state; 92 /* [0x4] CPU request to change DMA state */ 93 uint32_t change_state; 94 uint32_t rsrvd_0; 95 /* 96 * [0xc] S2M DMA error log mask. 97 * Each error has an interrupt controller cause bit. 98 * This register determines if these errors cause the S2M DMA to log the 99 * error condition. 100 * 0 - Log is enable 101 * 1 - Log is masked. 102 */ 103 uint32_t err_log_mask; 104 uint32_t rsrvd_1; 105 /* 106 * [0x14] DMA header log 107 * Sample the packet header that caused the error 108 */ 109 uint32_t log_0; 110 /* 111 * [0x18] DMA header log 112 * Sample the packet header that caused the error. 113 */ 114 uint32_t log_1; 115 /* 116 * [0x1c] DMA header log 117 * Sample the packet header that caused the error. 118 */ 119 uint32_t log_2; 120 /* 121 * [0x20] DMA header log 122 * Sample the packet header that caused the error 123 */ 124 uint32_t log_3; 125 /* [0x24] DMA clear error log */ 126 uint32_t clear_err_log; 127 /* [0x28] S2M stream data FIFO status */ 128 uint32_t s_data_fifo_status; 129 /* [0x2c] S2M stream header FIFO status */ 130 uint32_t s_header_fifo_status; 131 /* [0x30] S2M AXI data FIFO status */ 132 uint32_t axi_data_fifo_status; 133 /* [0x34] S2M unack FIFO status */ 134 uint32_t unack_fifo_status; 135 /* [0x38] Select queue for debug */ 136 uint32_t indirect_ctrl; 137 /* 138 * [0x3c] S2M prefetch FIFO status. 139 * Status of the selected queue in S2M_indirect_ctrl 140 */ 141 uint32_t sel_pref_fifo_status; 142 /* 143 * [0x40] S2M completion FIFO status. 144 * Status of the selected queue in S2M_indirect_ctrl 145 */ 146 uint32_t sel_comp_fifo_status; 147 /* [0x44] S2M state machine and FIFO clear control */ 148 uint32_t clear_ctrl; 149 /* [0x48] S2M Misc Check enable */ 150 uint32_t check_en; 151 /* [0x4c] S2M FIFO enable control, internal */ 152 uint32_t fifo_en; 153 /* [0x50] Stream interface configuration */ 154 uint32_t stream_cfg; 155 uint32_t rsrvd[43]; 156 }; 157 struct udma_s2m_rd { 158 /* [0x0] S2M descriptor prefetch configuration */ 159 uint32_t desc_pref_cfg_1; 160 /* [0x4] S2M descriptor prefetch configuration */ 161 uint32_t desc_pref_cfg_2; 162 /* [0x8] S2M descriptor prefetch configuration */ 163 uint32_t desc_pref_cfg_3; 164 /* [0xc] S2M descriptor prefetch configuration */ 165 uint32_t desc_pref_cfg_4; 166 uint32_t rsrvd[12]; 167 }; 168 struct udma_s2m_wr { 169 /* [0x0] Stream data FIFO configuration */ 170 uint32_t data_cfg_1; 171 /* [0x4] Data write configuration */ 172 uint32_t data_cfg_2; 173 uint32_t rsrvd[14]; 174 }; 175 struct udma_s2m_comp { 176 /* [0x0] Completion controller configuration */ 177 uint32_t cfg_1c; 178 /* [0x4] Completion controller configuration */ 179 uint32_t cfg_2c; 180 uint32_t rsrvd_0; 181 /* [0xc] Completion controller application acknowledge configuration */ 182 uint32_t cfg_application_ack; 183 uint32_t rsrvd[12]; 184 }; 185 struct udma_s2m_stat { 186 uint32_t rsrvd_0; 187 /* [0x4] Number of dropped packets */ 188 uint32_t drop_pkt; 189 /* 190 * [0x8] Counting the net length of the data buffers [64-bit] 191 * Should be read before rx_bytes_high 192 */ 193 uint32_t rx_bytes_low; 194 /* 195 * [0xc] Counting the net length of the data buffers [64-bit] 196 * Should be read after tx_bytes_low (value is sampled when reading 197 * Should be read before rx_bytes_low 198 */ 199 uint32_t rx_bytes_high; 200 /* [0x10] Total number of descriptors read from the host memory */ 201 uint32_t prefed_desc; 202 /* [0x14] Number of packets written into the completion ring */ 203 uint32_t comp_pkt; 204 /* [0x18] Number of descriptors written into the completion ring */ 205 uint32_t comp_desc; 206 /* 207 * [0x1c] Number of acknowledged packets. 208 * (acknowledge sent to the stream interface) 209 */ 210 uint32_t ack_pkts; 211 uint32_t rsrvd[56]; 212 }; 213 struct udma_s2m_feature { 214 /* 215 * [0x0] S2M Feature register 216 * S2M instantiation parameters 217 */ 218 uint32_t reg_1; 219 /* [0x4] Reserved S2M feature register */ 220 uint32_t reg_2; 221 /* 222 * [0x8] S2M Feature register 223 * S2M instantiation parameters 224 */ 225 uint32_t reg_3; 226 /* 227 * [0xc] S2M Feature register. 228 * S2M instantiation parameters. 229 */ 230 uint32_t reg_4; 231 /* 232 * [0x10] S2M Feature register. 233 * S2M instantiation parameters. 234 */ 235 uint32_t reg_5; 236 /* [0x14] S2M Feature register. S2M instantiation parameters. */ 237 uint32_t reg_6; 238 uint32_t rsrvd[58]; 239 }; 240 struct udma_s2m_q { 241 uint32_t rsrvd_0[8]; 242 /* [0x20] S2M Descriptor ring configuration */ 243 uint32_t cfg; 244 /* [0x24] S2M Descriptor ring status and information */ 245 uint32_t status; 246 /* [0x28] Rx Descriptor Ring Base Pointer [31:4] */ 247 uint32_t rdrbp_low; 248 /* [0x2c] Rx Descriptor Ring Base Pointer [63:32] */ 249 uint32_t rdrbp_high; 250 /* 251 * [0x30] Rx Descriptor Ring Length[23:2] 252 */ 253 uint32_t rdrl; 254 /* [0x34] RX Descriptor Ring Head Pointer */ 255 uint32_t rdrhp; 256 /* [0x38] Rx Descriptor Tail Pointer increment */ 257 uint32_t rdrtp_inc; 258 /* [0x3c] Rx Descriptor Tail Pointer */ 259 uint32_t rdrtp; 260 /* [0x40] RX Descriptor Current Pointer */ 261 uint32_t rdcp; 262 /* [0x44] Rx Completion Ring Base Pointer [31:4] */ 263 uint32_t rcrbp_low; 264 /* [0x48] Rx Completion Ring Base Pointer [63:32] */ 265 uint32_t rcrbp_high; 266 /* [0x4c] Rx Completion Ring Head Pointer */ 267 uint32_t rcrhp; 268 /* 269 * [0x50] RX Completion Ring Head Pointer internal. 270 * (Before the coalescing FIFO) 271 */ 272 uint32_t rcrhp_internal; 273 /* [0x54] Completion controller configuration for the queue */ 274 uint32_t comp_cfg; 275 /* [0x58] Completion controller configuration for the queue */ 276 uint32_t comp_cfg_2; 277 /* [0x5c] Packet handler configuration */ 278 uint32_t pkt_cfg; 279 /* [0x60] Queue QoS configuration */ 280 uint32_t qos_cfg; 281 /* [0x64] DMB software control */ 282 uint32_t q_sw_ctrl; 283 /* [0x68] Number of S2M Rx packets after completion */ 284 uint32_t q_rx_pkt; 285 uint32_t rsrvd[997]; 286 }; 287 288 struct udma_s2m_regs { 289 uint32_t rsrvd_0[64]; 290 struct udma_axi_s2m axi_s2m; /* [0x100] */ 291 struct udma_s2m s2m; /* [0x200] */ 292 struct udma_s2m_rd s2m_rd; /* [0x300] */ 293 struct udma_s2m_wr s2m_wr; /* [0x340] */ 294 struct udma_s2m_comp s2m_comp; /* [0x380] */ 295 uint32_t rsrvd_1[80]; 296 struct udma_s2m_stat s2m_stat; /* [0x500] */ 297 struct udma_s2m_feature s2m_feature; /* [0x600] */ 298 uint32_t rsrvd_2[576]; 299 struct udma_s2m_q s2m_q[4]; /* [0x1000] */ 300 }; 301 302 303 /* 304 * Registers Fields 305 */ 306 307 308 /**** data_wr_cfg_1 register ****/ 309 /* AXI write ID (AWID) */ 310 #define UDMA_AXI_S2M_DATA_WR_CFG_1_AWID_MASK 0x000000FF 311 #define UDMA_AXI_S2M_DATA_WR_CFG_1_AWID_SHIFT 0 312 /* Cache Type */ 313 #define UDMA_AXI_S2M_DATA_WR_CFG_1_AWCACHE_MASK 0x000F0000 314 #define UDMA_AXI_S2M_DATA_WR_CFG_1_AWCACHE_SHIFT 16 315 /* Burst type */ 316 #define UDMA_AXI_S2M_DATA_WR_CFG_1_AWBURST_MASK 0x03000000 317 #define UDMA_AXI_S2M_DATA_WR_CFG_1_AWBURST_SHIFT 24 318 319 /**** data_wr_cfg_2 register ****/ 320 /* User extension */ 321 #define UDMA_AXI_S2M_DATA_WR_CFG_2_AWUSER_MASK 0x000FFFFF 322 #define UDMA_AXI_S2M_DATA_WR_CFG_2_AWUSER_SHIFT 0 323 /* Bus size, 128-bit */ 324 #define UDMA_AXI_S2M_DATA_WR_CFG_2_AWSIZE_MASK 0x00700000 325 #define UDMA_AXI_S2M_DATA_WR_CFG_2_AWSIZE_SHIFT 20 326 /* 327 * AXI Master QoS. 328 * Used for arbitration between AXI masters 329 */ 330 #define UDMA_AXI_S2M_DATA_WR_CFG_2_AWQOS_MASK 0x07000000 331 #define UDMA_AXI_S2M_DATA_WR_CFG_2_AWQOS_SHIFT 24 332 /* Protection Type */ 333 #define UDMA_AXI_S2M_DATA_WR_CFG_2_AWPROT_MASK 0x70000000 334 #define UDMA_AXI_S2M_DATA_WR_CFG_2_AWPROT_SHIFT 28 335 336 /**** desc_rd_cfg_4 register ****/ 337 /* AXI read ID (ARID) */ 338 #define UDMA_AXI_S2M_DESC_RD_CFG_4_ARID_MASK 0x000000FF 339 #define UDMA_AXI_S2M_DESC_RD_CFG_4_ARID_SHIFT 0 340 /* Cache Type */ 341 #define UDMA_AXI_S2M_DESC_RD_CFG_4_ARCACHE_MASK 0x000F0000 342 #define UDMA_AXI_S2M_DESC_RD_CFG_4_ARCACHE_SHIFT 16 343 /* Burst type */ 344 #define UDMA_AXI_S2M_DESC_RD_CFG_4_ARBURST_MASK 0x03000000 345 #define UDMA_AXI_S2M_DESC_RD_CFG_4_ARBURST_SHIFT 24 346 347 /**** desc_rd_cfg_5 register ****/ 348 /* User extension */ 349 #define UDMA_AXI_S2M_DESC_RD_CFG_5_ARUSER_MASK 0x000FFFFF 350 #define UDMA_AXI_S2M_DESC_RD_CFG_5_ARUSER_SHIFT 0 351 /* Bus size, 128-bit */ 352 #define UDMA_AXI_S2M_DESC_RD_CFG_5_ARSIZE_MASK 0x00700000 353 #define UDMA_AXI_S2M_DESC_RD_CFG_5_ARSIZE_SHIFT 20 354 /* 355 * AXI Master QoS. 356 * Used for arbitration between AXI masters 357 */ 358 #define UDMA_AXI_S2M_DESC_RD_CFG_5_ARQOS_MASK 0x07000000 359 #define UDMA_AXI_S2M_DESC_RD_CFG_5_ARQOS_SHIFT 24 360 /* Protection Type */ 361 #define UDMA_AXI_S2M_DESC_RD_CFG_5_ARPROT_MASK 0x70000000 362 #define UDMA_AXI_S2M_DESC_RD_CFG_5_ARPROT_SHIFT 28 363 364 /**** comp_wr_cfg_1 register ****/ 365 /* AXI write ID (AWID) */ 366 #define UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_MASK 0x000000FF 367 #define UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_SHIFT 0 368 /* Cache Type */ 369 #define UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_MASK 0x000F0000 370 #define UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_SHIFT 16 371 /* Burst type */ 372 #define UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_MASK 0x03000000 373 #define UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_SHIFT 24 374 375 /**** comp_wr_cfg_2 register ****/ 376 /* User extension */ 377 #define UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_MASK 0x000FFFFF 378 #define UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_SHIFT 0 379 /* Bus size, 128-bit */ 380 #define UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_MASK 0x00700000 381 #define UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_SHIFT 20 382 /* 383 * AXI Master QoS. 384 * Used for arbitration between AXI masters 385 */ 386 #define UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_MASK 0x07000000 387 #define UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_SHIFT 24 388 /* Protection Type */ 389 #define UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_MASK 0x70000000 390 #define UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_SHIFT 28 391 392 /**** data_wr_cfg register ****/ 393 /* 394 * Defines the maximum number of AXI beats for a single AXI burst. This value is 395 * used for the burst split decision. 396 */ 397 #define UDMA_AXI_S2M_DATA_WR_CFG_MAX_AXI_BEATS_MASK 0x000000FF 398 #define UDMA_AXI_S2M_DATA_WR_CFG_MAX_AXI_BEATS_SHIFT 0 399 400 /**** desc_rd_cfg_3 register ****/ 401 /* 402 * Defines the maximum number of AXI beats for a single AXI burst. This value is 403 * used for the burst split decision. 404 */ 405 #define UDMA_AXI_S2M_DESC_RD_CFG_3_MAX_AXI_BEATS_MASK 0x000000FF 406 #define UDMA_AXI_S2M_DESC_RD_CFG_3_MAX_AXI_BEATS_SHIFT 0 407 /* 408 * Enables breaking descriptor read request. 409 * Aligned to max_AXI_beats when the total read size is less than max_AXI_beats. 410 */ 411 #define UDMA_AXI_S2M_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY (1 << 16) 412 413 /**** desc_wr_cfg_1 register ****/ 414 /* 415 * Defines the maximum number of AXI beats for a single AXI burst. This value is 416 * used for the burst split decision. 417 */ 418 #define UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK 0x000000FF 419 #define UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_SHIFT 0 420 /* 421 * Minimum burst for writing completion descriptors. 422 * (AXI beats). 423 * Value must be aligned to cache lines (64 bytes). 424 * Default value is 2 cache lines, 8 beats. 425 */ 426 #define UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK 0x00FF0000 427 #define UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_SHIFT 16 428 429 /**** ostand_cfg_rd register ****/ 430 /* 431 * Maximum number of outstanding descriptor reads to the AXI. 432 * (AXI transactions). 433 */ 434 #define UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_DESC_RD_OSTAND_MASK 0x0000003F 435 #define UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_DESC_RD_OSTAND_SHIFT 0 436 /* Maximum number of outstanding stream acknowledges. */ 437 #define UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_MASK 0x001F0000 438 #define UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_SHIFT 16 439 440 /**** ostand_cfg_wr register ****/ 441 /* 442 * Maximum number of outstanding data writes to the AXI. 443 * (AXI transactions). 444 */ 445 #define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_WR_OSTAND_MASK 0x0000003F 446 #define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_WR_OSTAND_SHIFT 0 447 /* 448 * Maximum number of outstanding data beats for data write to AXI. 449 * (AXI beats). 450 */ 451 #define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_MASK 0x0000FF00 452 #define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_SHIFT 8 453 /* 454 * Maximum number of outstanding descriptor writes to the AXI. 455 * (AXI transactions). 456 */ 457 #define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_MASK 0x003F0000 458 #define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_SHIFT 16 459 /* 460 * Maximum number of outstanding data beats for descriptor write to AXI. 461 * (AXI beats). 462 */ 463 #define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_MASK 0xFF000000 464 #define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_SHIFT 24 465 466 /**** state register ****/ 467 468 #define UDMA_S2M_STATE_COMP_CTRL_MASK 0x00000003 469 #define UDMA_S2M_STATE_COMP_CTRL_SHIFT 0 470 471 #define UDMA_S2M_STATE_STREAM_IF_MASK 0x00000030 472 #define UDMA_S2M_STATE_STREAM_IF_SHIFT 4 473 474 #define UDMA_S2M_STATE_DATA_WR_CTRL_MASK 0x00000300 475 #define UDMA_S2M_STATE_DATA_WR_CTRL_SHIFT 8 476 477 #define UDMA_S2M_STATE_DESC_PREF_MASK 0x00003000 478 #define UDMA_S2M_STATE_DESC_PREF_SHIFT 12 479 480 #define UDMA_S2M_STATE_AXI_WR_DATA_MASK 0x00030000 481 #define UDMA_S2M_STATE_AXI_WR_DATA_SHIFT 16 482 483 /**** change_state register ****/ 484 /* Start normal operation */ 485 #define UDMA_S2M_CHANGE_STATE_NORMAL (1 << 0) 486 /* Stop normal operation */ 487 #define UDMA_S2M_CHANGE_STATE_DIS (1 << 1) 488 /* 489 * Stop all machines. 490 * (Prefetch, scheduling, completion and stream interface) 491 */ 492 #define UDMA_S2M_CHANGE_STATE_ABORT (1 << 2) 493 494 /**** clear_err_log register ****/ 495 /* Clear error log */ 496 #define UDMA_S2M_CLEAR_ERR_LOG_CLEAR (1 << 0) 497 498 /**** s_data_fifo_status register ****/ 499 /* FIFO used indication */ 500 #define UDMA_S2M_S_DATA_FIFO_STATUS_USED_MASK 0x0000FFFF 501 #define UDMA_S2M_S_DATA_FIFO_STATUS_USED_SHIFT 0 502 /* FIFO empty indication */ 503 #define UDMA_S2M_S_DATA_FIFO_STATUS_EMPTY (1 << 24) 504 /* FIFO full indication */ 505 #define UDMA_S2M_S_DATA_FIFO_STATUS_FULL (1 << 28) 506 507 /**** s_header_fifo_status register ****/ 508 /* FIFO used indication */ 509 #define UDMA_S2M_S_HEADER_FIFO_STATUS_USED_MASK 0x0000FFFF 510 #define UDMA_S2M_S_HEADER_FIFO_STATUS_USED_SHIFT 0 511 /* FIFO empty indication */ 512 #define UDMA_S2M_S_HEADER_FIFO_STATUS_EMPTY (1 << 24) 513 /* FIFO full indication */ 514 #define UDMA_S2M_S_HEADER_FIFO_STATUS_FULL (1 << 28) 515 516 /**** axi_data_fifo_status register ****/ 517 /* FIFO used indication */ 518 #define UDMA_S2M_AXI_DATA_FIFO_STATUS_USED_MASK 0x0000FFFF 519 #define UDMA_S2M_AXI_DATA_FIFO_STATUS_USED_SHIFT 0 520 /* FIFO empty indication */ 521 #define UDMA_S2M_AXI_DATA_FIFO_STATUS_EMPTY (1 << 24) 522 /* FIFO full indication */ 523 #define UDMA_S2M_AXI_DATA_FIFO_STATUS_FULL (1 << 28) 524 525 /**** unack_fifo_status register ****/ 526 /* FIFO used indication */ 527 #define UDMA_S2M_UNACK_FIFO_STATUS_USED_MASK 0x0000FFFF 528 #define UDMA_S2M_UNACK_FIFO_STATUS_USED_SHIFT 0 529 /* FIFO empty indication */ 530 #define UDMA_S2M_UNACK_FIFO_STATUS_EMPTY (1 << 24) 531 /* FIFO full indication */ 532 #define UDMA_S2M_UNACK_FIFO_STATUS_FULL (1 << 28) 533 534 /**** indirect_ctrl register ****/ 535 /* Selected queue for status read */ 536 #define UDMA_S2M_INDIRECT_CTRL_Q_NUM_MASK 0x00000FFF 537 #define UDMA_S2M_INDIRECT_CTRL_Q_NUM_SHIFT 0 538 539 /**** sel_pref_fifo_status register ****/ 540 /* FIFO used indication */ 541 #define UDMA_S2M_SEL_PREF_FIFO_STATUS_USED_MASK 0x0000FFFF 542 #define UDMA_S2M_SEL_PREF_FIFO_STATUS_USED_SHIFT 0 543 /* FIFO empty indication */ 544 #define UDMA_S2M_SEL_PREF_FIFO_STATUS_EMPTY (1 << 24) 545 /* FIFO full indication */ 546 #define UDMA_S2M_SEL_PREF_FIFO_STATUS_FULL (1 << 28) 547 548 /**** sel_comp_fifo_status register ****/ 549 /* FIFO used indication */ 550 #define UDMA_S2M_SEL_COMP_FIFO_STATUS_USED_MASK 0x0000FFFF 551 #define UDMA_S2M_SEL_COMP_FIFO_STATUS_USED_SHIFT 0 552 /* Coalescing ACTIVE FSM state indication. */ 553 #define UDMA_S2M_SEL_COMP_FIFO_STATUS_COAL_ACTIVE_STATE_MASK 0x00300000 554 #define UDMA_S2M_SEL_COMP_FIFO_STATUS_COAL_ACTIVE_STATE_SHIFT 20 555 /* FIFO empty indication */ 556 #define UDMA_S2M_SEL_COMP_FIFO_STATUS_EMPTY (1 << 24) 557 /* FIFO full indication */ 558 #define UDMA_S2M_SEL_COMP_FIFO_STATUS_FULL (1 << 28) 559 560 /**** stream_cfg register ****/ 561 /* 562 * Disables the stream interface operation. 563 * Changing to 1 stops at the end of packet reception. 564 */ 565 #define UDMA_S2M_STREAM_CFG_DISABLE (1 << 0) 566 /* 567 * Flush the stream interface operation. 568 * Changing to 1 stops at the end of packet reception and assert ready to the 569 * stream I/F. 570 */ 571 #define UDMA_S2M_STREAM_CFG_FLUSH (1 << 4) 572 /* Stop descriptor prefetch when the stream is disabled and the S2M is idle. */ 573 #define UDMA_S2M_STREAM_CFG_STOP_PREFETCH (1 << 8) 574 575 /**** desc_pref_cfg_1 register ****/ 576 /* 577 * Size of the descriptor prefetch FIFO. 578 * (descriptors) 579 */ 580 #define UDMA_S2M_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK 0x000000FF 581 #define UDMA_S2M_RD_DESC_PREF_CFG_1_FIFO_DEPTH_SHIFT 0 582 583 /**** desc_pref_cfg_2 register ****/ 584 /* Enable promotion of the current queue in progress */ 585 #define UDMA_S2M_RD_DESC_PREF_CFG_2_Q_PROMOTION (1 << 0) 586 /* Force promotion of the current queue in progress */ 587 #define UDMA_S2M_RD_DESC_PREF_CFG_2_FORCE_PROMOTION (1 << 1) 588 /* Enable prefetch prediction of next packet in line. */ 589 #define UDMA_S2M_RD_DESC_PREF_CFG_2_EN_PREF_PREDICTION (1 << 2) 590 /* 591 * Threshold for queue promotion. 592 * Queue is promoted for prefetch if there are less descriptors in the prefetch 593 * FIFO than the threshold 594 */ 595 #define UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_MASK 0x0000FF00 596 #define UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_SHIFT 8 597 /* 598 * Force RR arbitration in the prefetch arbiter. 599 * 0 - Standard arbitration based on queue QoS 600 * 1 - Force round robin arbitration 601 */ 602 #define UDMA_S2M_RD_DESC_PREF_CFG_2_PREF_FORCE_RR (1 << 16) 603 604 /**** desc_pref_cfg_3 register ****/ 605 /* 606 * Minimum descriptor burst size when prefetch FIFO level is below the 607 * descriptor prefetch threshold 608 * (must be 1) 609 */ 610 #define UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK 0x0000000F 611 #define UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_SHIFT 0 612 /* 613 * Minimum descriptor burst size when prefetch FIFO level is above the 614 * descriptor prefetch threshold 615 */ 616 #define UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK 0x000000F0 617 #define UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT 4 618 /* 619 * Descriptor fetch threshold. 620 * Used as a threshold to determine the allowed minimum descriptor burst size. 621 * (Must be at least "max_desc_per_pkt") 622 */ 623 #define UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_MASK 0x0000FF00 624 #define UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT 8 625 626 /**** desc_pref_cfg_4 register ****/ 627 /* 628 * Used as a threshold for generating almost FULL indication to the application 629 */ 630 #define UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_MASK 0x000000FF 631 #define UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_SHIFT 0 632 633 /**** data_cfg_1 register ****/ 634 /* 635 * Maximum number of data beats in the data write FIFO. 636 * Defined based on data FIFO size 637 * (default FIFO size 512B → 32 beats) 638 */ 639 #define UDMA_S2M_WR_DATA_CFG_1_DATA_FIFO_DEPTH_MASK 0x000003FF 640 #define UDMA_S2M_WR_DATA_CFG_1_DATA_FIFO_DEPTH_SHIFT 0 641 /* 642 * Maximum number of packets in the data write FIFO. 643 * Defined based on header FIFO size 644 */ 645 #define UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_MASK 0x00FF0000 646 #define UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_SHIFT 16 647 /* 648 * Internal use 649 * Data FIFO margin 650 */ 651 #define UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_MASK 0xFF000000 652 #define UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_SHIFT 24 653 654 /**** data_cfg_2 register ****/ 655 /* 656 * Drop timer. 657 * Waiting time for the host to write new descriptor to the queue 658 * (for the current packet in process) 659 */ 660 #define UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK 0x00FFFFFF 661 #define UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_SHIFT 0 662 /* 663 * Drop enable. 664 * Enable packet drop if there are no available descriptors in the system for 665 * this queue 666 */ 667 #define UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC (1 << 27) 668 /* 669 * Lack of descriptors hint. 670 * Generate interrupt when a packet is waiting but there are no available 671 * descriptors in the queue 672 */ 673 #define UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC (1 << 28) 674 /* 675 * Drop conditions 676 * Wait until a descriptor is available in the prefetch FIFO or the host before 677 * dropping packet. 678 * 1 - Drop if a descriptor is not available in the prefetch. 679 * 0 - Drop if a descriptor is not available in the system 680 */ 681 #define UDMA_S2M_WR_DATA_CFG_2_WAIT_FOR_PREF (1 << 29) 682 /* 683 * DRAM write optimization 684 * 0 - Data write with byte enable 685 * 1 - Data write is always in Full AXI bus width (128 bit) 686 */ 687 #define UDMA_S2M_WR_DATA_CFG_2_FULL_LINE_MODE (1 << 30) 688 /* 689 * Direct data write address 690 * 1 - Use buffer 1 instead of buffer 2 when direct data placement is used with 691 * header split. 692 * 0 - Use buffer 2 for the header. 693 */ 694 #define UDMA_S2M_WR_DATA_CFG_2_DIRECT_HDR_USE_BUF1 (1 << 31) 695 696 /**** cfg_1c register ****/ 697 /* 698 * Completion descriptor size. 699 * (words) 700 */ 701 #define UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK 0x0000000F 702 #define UDMA_S2M_COMP_CFG_1C_DESC_SIZE_SHIFT 0 703 /* 704 * Completion queue counter configuration. 705 * Completion FIFO in use counter measured in words or descriptors 706 * 1 - Words 707 * 0 - Descriptors 708 */ 709 #define UDMA_S2M_COMP_CFG_1C_CNT_WORDS (1 << 8) 710 /* 711 * Enable promotion of the current queue in progress in the completion write 712 * scheduler. 713 */ 714 #define UDMA_S2M_COMP_CFG_1C_Q_PROMOTION (1 << 12) 715 /* Force RR arbitration in the completion arbiter */ 716 #define UDMA_S2M_COMP_CFG_1C_FORCE_RR (1 << 16) 717 /* Minimum number of free completion entries to qualify for promotion */ 718 #define UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_MASK 0xF0000000 719 #define UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_SHIFT 28 720 721 /**** cfg_2c register ****/ 722 /* 723 * Completion FIFO size. 724 * (words per queue) 725 */ 726 #define UDMA_S2M_COMP_CFG_2C_COMP_FIFO_DEPTH_MASK 0x00000FFF 727 #define UDMA_S2M_COMP_CFG_2C_COMP_FIFO_DEPTH_SHIFT 0 728 /* 729 * Unacknowledged FIFO size. 730 * (descriptors) 731 */ 732 #define UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_MASK 0x0FFF0000 733 #define UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_SHIFT 16 734 735 /**** reg_1 register ****/ 736 /* 737 * Descriptor prefetch FIFO size 738 * (descriptors) 739 */ 740 #define UDMA_S2M_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_MASK 0x000000FF 741 #define UDMA_S2M_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_SHIFT 0 742 743 /**** reg_3 register ****/ 744 /* 745 * Maximum number of data beats in the data write FIFO. 746 * Defined based on data FIFO size 747 * (default FIFO size 512B →32 beats) 748 */ 749 #define UDMA_S2M_FEATURE_REG_3_DATA_FIFO_DEPTH_MASK 0x000003FF 750 #define UDMA_S2M_FEATURE_REG_3_DATA_FIFO_DEPTH_SHIFT 0 751 /* 752 * Maximum number of packets in the data write FIFO. 753 * Defined based on header FIFO size 754 */ 755 #define UDMA_S2M_FEATURE_REG_3_DATA_WR_MAX_PKT_LIMIT_MASK 0x00FF0000 756 #define UDMA_S2M_FEATURE_REG_3_DATA_WR_MAX_PKT_LIMIT_SHIFT 16 757 758 /**** reg_4 register ****/ 759 /* 760 * Completion FIFO size. 761 * (words per queue) 762 */ 763 #define UDMA_S2M_FEATURE_REG_4_COMP_FIFO_DEPTH_MASK 0x00000FFF 764 #define UDMA_S2M_FEATURE_REG_4_COMP_FIFO_DEPTH_SHIFT 0 765 /* 766 * Unacknowledged FIFO size. 767 * (descriptors) 768 */ 769 #define UDMA_S2M_FEATURE_REG_4_COMP_UNACK_FIFO_DEPTH_MASK 0x0FFF0000 770 #define UDMA_S2M_FEATURE_REG_4_COMP_UNACK_FIFO_DEPTH_SHIFT 16 771 772 /**** reg_5 register ****/ 773 /* Maximum number of outstanding data writes to the AXI */ 774 #define UDMA_S2M_FEATURE_REG_5_MAX_DATA_WR_OSTAND_MASK 0x0000003F 775 #define UDMA_S2M_FEATURE_REG_5_MAX_DATA_WR_OSTAND_SHIFT 0 776 /* 777 * Maximum number of outstanding data beats for data write to AXI. 778 * (AXI beats) 779 */ 780 #define UDMA_S2M_FEATURE_REG_5_MAX_DATA_BEATS_WR_OSTAND_MASK 0x0000FF00 781 #define UDMA_S2M_FEATURE_REG_5_MAX_DATA_BEATS_WR_OSTAND_SHIFT 8 782 /* 783 * Maximum number of outstanding descriptor reads to the AXI. 784 * (AXI transactions) 785 */ 786 #define UDMA_S2M_FEATURE_REG_5_MAX_COMP_REQ_MASK 0x003F0000 787 #define UDMA_S2M_FEATURE_REG_5_MAX_COMP_REQ_SHIFT 16 788 /* 789 * Maximum number of outstanding data beats for descriptor write to AXI. 790 * (AXI beats) 791 */ 792 #define UDMA_S2M_FEATURE_REG_5_MAX_COMP_DATA_WR_OSTAND_MASK 0xFF000000 793 #define UDMA_S2M_FEATURE_REG_5_MAX_COMP_DATA_WR_OSTAND_SHIFT 24 794 795 /**** reg_6 register ****/ 796 /* Maximum number of outstanding descriptor reads to the AXI */ 797 #define UDMA_S2M_FEATURE_REG_6_MAX_DESC_RD_OSTAND_MASK 0x0000003F 798 #define UDMA_S2M_FEATURE_REG_6_MAX_DESC_RD_OSTAND_SHIFT 0 799 /* Maximum number of outstanding stream acknowledges */ 800 #define UDMA_S2M_FEATURE_REG_6_MAX_STREAM_ACK_MASK 0x001F0000 801 #define UDMA_S2M_FEATURE_REG_6_MAX_STREAM_ACK_SHIFT 16 802 803 /**** cfg register ****/ 804 /* 805 * Configure the AXI AWCACHE 806 * for header write. 807 */ 808 #define UDMA_S2M_Q_CFG_AXI_AWCACHE_HDR_MASK 0x0000000F 809 #define UDMA_S2M_Q_CFG_AXI_AWCACHE_HDR_SHIFT 0 810 /* 811 * Configure the AXI AWCACHE 812 * for data write. 813 */ 814 #define UDMA_S2M_Q_CFG_AXI_AWCACHE_DATA_MASK 0x000000F0 815 #define UDMA_S2M_Q_CFG_AXI_AWCACHE_DATA_SHIFT 4 816 /* 817 * Enable operation of this queue. 818 * Start prefetch. 819 */ 820 #define UDMA_S2M_Q_CFG_EN_PREF (1 << 16) 821 /* Enables the reception of packets from the stream to this queue */ 822 #define UDMA_S2M_Q_CFG_EN_STREAM (1 << 17) 823 /* Allow prefetch of less than minimum prefetch burst size. */ 824 #define UDMA_S2M_Q_CFG_ALLOW_LT_MIN_PREF (1 << 20) 825 /* 826 * Configure the AXI AWCACHE 827 * for completion descriptor write 828 */ 829 #define UDMA_S2M_Q_CFG_AXI_AWCACHE_COMP_MASK 0x0F000000 830 #define UDMA_S2M_Q_CFG_AXI_AWCACHE_COMP_SHIFT 24 831 /* 832 * AXI QoS 833 * This value is used in AXI transactions associated with this queue and the 834 * prefetch and completion arbiters. 835 */ 836 #define UDMA_S2M_Q_CFG_AXI_QOS_MASK 0x70000000 837 #define UDMA_S2M_Q_CFG_AXI_QOS_SHIFT 28 838 839 /**** status register ****/ 840 /* Indicates how many entries are used in the Queue */ 841 #define UDMA_S2M_Q_STATUS_Q_USED_MASK 0x01FFFFFF 842 #define UDMA_S2M_Q_STATUS_Q_USED_SHIFT 0 843 /* 844 * prefetch status 845 * 0 – prefetch operation is stopped 846 * 1 – prefetch is operational 847 */ 848 #define UDMA_S2M_Q_STATUS_PREFETCH (1 << 28) 849 /* 850 * Queue receive status 851 * 0 -queue RX operation is stopped 852 * 1 – RX queue is active and processing packets 853 */ 854 #define UDMA_S2M_Q_STATUS_RX (1 << 29) 855 /* 856 * Indicates if the queue is full. 857 * (Used by the host when head pointer equals tail pointer) 858 */ 859 #define UDMA_S2M_Q_STATUS_Q_FULL (1 << 31) 860 /* 861 * S2M Descriptor Ring Base address [31:4]. 862 * Value of the base address of the S2M descriptor ring 863 * [3:0] - 0 - 16B alignment is enforced 864 * ([11:4] should be 0 for 4KB alignment) 865 */ 866 #define UDMA_S2M_Q_RDRBP_LOW_ADDR_MASK 0xFFFFFFF0 867 #define UDMA_S2M_Q_RDRBP_LOW_ADDR_SHIFT 4 868 869 /**** RDRL register ****/ 870 /* 871 * Length of the descriptor ring. 872 * (descriptors) 873 * Associated with the ring base address ends at maximum burst size alignment 874 */ 875 #define UDMA_S2M_Q_RDRL_OFFSET_MASK 0x00FFFFFF 876 #define UDMA_S2M_Q_RDRL_OFFSET_SHIFT 0 877 878 /**** RDRHP register ****/ 879 /* 880 * Relative offset of the next descriptor that needs to be read into the 881 * prefetch FIFO. 882 * Incremented when the DMA reads valid descriptors from the host memory to the 883 * prefetch FIFO. 884 * Note that this is the offset in # of descriptors and not in byte address. 885 */ 886 #define UDMA_S2M_Q_RDRHP_OFFSET_MASK 0x00FFFFFF 887 #define UDMA_S2M_Q_RDRHP_OFFSET_SHIFT 0 888 /* Ring ID */ 889 #define UDMA_S2M_Q_RDRHP_RING_ID_MASK 0xC0000000 890 #define UDMA_S2M_Q_RDRHP_RING_ID_SHIFT 30 891 892 /**** RDRTP_inc register ****/ 893 /* 894 * Increments the value in Q_RDRTP with the value written to this field in 895 * number of descriptors. 896 */ 897 #define UDMA_S2M_Q_RDRTP_INC_VAL_MASK 0x00FFFFFF 898 #define UDMA_S2M_Q_RDRTP_INC_VAL_SHIFT 0 899 900 /**** RDRTP register ****/ 901 /* 902 * Relative offset of the next free descriptor in the host memory. 903 * Note that this is the offset in # of descriptors and not in byte address. 904 */ 905 #define UDMA_S2M_Q_RDRTP_OFFSET_MASK 0x00FFFFFF 906 #define UDMA_S2M_Q_RDRTP_OFFSET_SHIFT 0 907 /* Ring ID */ 908 #define UDMA_S2M_Q_RDRTP_RING_ID_MASK 0xC0000000 909 #define UDMA_S2M_Q_RDRTP_RING_ID_SHIFT 30 910 911 /**** RDCP register ****/ 912 /* Relative offset of the first descriptor in the prefetch FIFO. */ 913 #define UDMA_S2M_Q_RDCP_OFFSET_MASK 0x00FFFFFF 914 #define UDMA_S2M_Q_RDCP_OFFSET_SHIFT 0 915 /* Ring ID */ 916 #define UDMA_S2M_Q_RDCP_RING_ID_MASK 0xC0000000 917 #define UDMA_S2M_Q_RDCP_RING_ID_SHIFT 30 918 /* 919 * S2M Descriptor Ring Base address [31:4]. 920 * Value of the base address of the S2M descriptor ring 921 * [3:0] - 0 - 16B alignment is enforced 922 * ([11:4] Must be 0 for 4KB alignment) 923 * NOTE: 924 * Length of the descriptor ring (in descriptors) associated with the ring base 925 * address ends at maximum burst size alignment 926 */ 927 #define UDMA_S2M_Q_RCRBP_LOW_ADDR_MASK 0xFFFFFFF0 928 #define UDMA_S2M_Q_RCRBP_LOW_ADDR_SHIFT 4 929 930 /**** RCRHP register ****/ 931 /* 932 * Relative offset of the next descriptor that needs to be updated by the 933 * completion controller. 934 * Note: This is in descriptors and not in byte address. 935 */ 936 #define UDMA_S2M_Q_RCRHP_OFFSET_MASK 0x00FFFFFF 937 #define UDMA_S2M_Q_RCRHP_OFFSET_SHIFT 0 938 /* Ring ID */ 939 #define UDMA_S2M_Q_RCRHP_RING_ID_MASK 0xC0000000 940 #define UDMA_S2M_Q_RCRHP_RING_ID_SHIFT 30 941 942 /**** RCRHP_internal register ****/ 943 /* 944 * Relative offset of the next descriptor that needs to be updated by the 945 * completion controller. 946 * Note: This is in descriptors and not in byte address. 947 */ 948 #define UDMA_S2M_Q_RCRHP_INTERNAL_OFFSET_MASK 0x00FFFFFF 949 #define UDMA_S2M_Q_RCRHP_INTERNAL_OFFSET_SHIFT 0 950 /* Ring ID */ 951 #define UDMA_S2M_Q_RCRHP_INTERNAL_RING_ID_MASK 0xC0000000 952 #define UDMA_S2M_Q_RCRHP_INTERNAL_RING_ID_SHIFT 30 953 954 /**** comp_cfg register ****/ 955 /* Enables writing to the completion ring. */ 956 #define UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE (1 << 0) 957 /* Disables the completion coalescing function. */ 958 #define UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL (1 << 1) 959 /* Reserved */ 960 #define UDMA_S2M_Q_COMP_CFG_FIRST_PKT_PROMOTION (1 << 2) 961 /* 962 * Buffer 2 location. 963 * Determines the position of the buffer 2 length in the S2M completion 964 * descriptor. 965 * 0 - WORD 1 [31:16] 966 * 1 - WORD 2 [31:16] 967 */ 968 #define UDMA_S2M_Q_COMP_CFG_BUF2_LEN_LOCATION (1 << 3) 969 970 /**** pkt_cfg register ****/ 971 /* Header size. (bytes) */ 972 #define UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK 0x0000FFFF 973 #define UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_SHIFT 0 974 /* Force header split */ 975 #define UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT (1 << 16) 976 /* Enable header split. */ 977 #define UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT (1 << 17) 978 979 /**** qos_cfg register ****/ 980 /* Queue QoS */ 981 #define UDMA_S2M_QOS_CFG_Q_QOS_MASK 0x000000FF 982 #define UDMA_S2M_QOS_CFG_Q_QOS_SHIFT 0 983 /* Reset the tail pointer hardware. */ 984 #define UDMA_S2M_Q_SW_CTRL_RST_TAIL_PTR (1 << 1) 985 /* Reset the head pointer hardware. */ 986 #define UDMA_S2M_Q_SW_CTRL_RST_HEAD_PTR (1 << 2) 987 /* Reset the current pointer hardware. */ 988 #define UDMA_S2M_Q_SW_CTRL_RST_CURRENT_PTR (1 << 3) 989 /* Reset the prefetch FIFO */ 990 #define UDMA_S2M_Q_SW_CTRL_RST_PREFETCH (1 << 4) 991 /* Reset the queue */ 992 #define UDMA_S2M_Q_SW_CTRL_RST_Q (1 << 8) 993 994 #ifdef __cplusplus 995 } 996 #endif 997 998 #endif /* __AL_HAL_UDMA_S2M_REG_H */ 999