1 /******************************************************************************* 2 Copyright (C) 2015 Annapurna Labs Ltd. 3 4 This file may be licensed under the terms of the Annapurna Labs Commercial 5 License Agreement. 6 7 Alternatively, this file can be distributed under the terms of the GNU General 8 Public License V2 as published by the Free Software Foundation and can be 9 found at http://www.gnu.org/licenses/gpl-2.0.html 10 11 Alternatively, redistribution and use in source and binary forms, with or 12 without modification, are permitted provided that the following conditions are 13 met: 14 15 * Redistributions of source code must retain the above copyright notice, 16 this list of conditions and the following disclaimer. 17 18 * Redistributions in binary form must reproduce the above copyright 19 notice, this list of conditions and the following disclaimer in 20 the documentation and/or other materials provided with the 21 distribution. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 24 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 27 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 34 *******************************************************************************/ 35 36 /** 37 * @file al_hal_udma_regs_gen.h 38 * 39 * @brief C Header file for the UDMA general registers 40 * 41 */ 42 43 #ifndef __AL_HAL_UDMA_GEN_REG_H 44 #define __AL_HAL_UDMA_GEN_REG_H 45 46 #include "al_hal_udma_iofic_regs.h" 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 /* 52 * Unit Registers 53 */ 54 55 56 57 struct udma_gen_dma_misc { 58 /* [0x0] Reserved register for the interrupt controller */ 59 uint32_t int_cfg; 60 /* [0x4] Revision register */ 61 uint32_t revision; 62 /* [0x8] Reserved for future use */ 63 uint32_t general_cfg_1; 64 /* [0xc] Reserved for future use */ 65 uint32_t general_cfg_2; 66 /* [0x10] Reserved for future use */ 67 uint32_t general_cfg_3; 68 /* [0x14] Reserved for future use */ 69 uint32_t general_cfg_4; 70 /* [0x18] General timer configuration */ 71 uint32_t general_cfg_5; 72 uint32_t rsrvd[57]; 73 }; 74 struct udma_gen_mailbox { 75 /* 76 * [0x0] Mailbox interrupt generator. 77 * Generates interrupt to neighbor DMA 78 */ 79 uint32_t interrupt; 80 /* [0x4] Mailbox message data out */ 81 uint32_t msg_out; 82 /* [0x8] Mailbox message data in */ 83 uint32_t msg_in; 84 uint32_t rsrvd[13]; 85 }; 86 struct udma_gen_axi { 87 /* [0x0] Configuration of the AXI masters */ 88 uint32_t cfg_1; 89 /* [0x4] Configuration of the AXI masters */ 90 uint32_t cfg_2; 91 /* [0x8] Configuration of the AXI masters. Endianess configuration */ 92 uint32_t endian_cfg; 93 uint32_t rsrvd[61]; 94 }; 95 struct udma_gen_sram_ctrl { 96 /* [0x0] Timing configuration */ 97 uint32_t timing; 98 }; 99 struct udma_gen_tgtid { 100 /* [0x0] Target-ID control */ 101 uint32_t cfg_tgtid_0; 102 /* [0x4] TX queue 0/1 Target-ID */ 103 uint32_t cfg_tgtid_1; 104 /* [0x8] TX queue 2/3 Target-ID */ 105 uint32_t cfg_tgtid_2; 106 /* [0xc] RX queue 0/1 Target-ID */ 107 uint32_t cfg_tgtid_3; 108 /* [0x10] RX queue 2/3 Target-ID */ 109 uint32_t cfg_tgtid_4; 110 }; 111 struct udma_gen_tgtaddr { 112 /* [0x0] TX queue 0/1 Target-Address */ 113 uint32_t cfg_tgtaddr_0; 114 /* [0x4] TX queue 2/3 Target-Address */ 115 uint32_t cfg_tgtaddr_1; 116 /* [0x8] RX queue 0/1 Target-Address */ 117 uint32_t cfg_tgtaddr_2; 118 /* [0xc] RX queue 2/3 Target-Address */ 119 uint32_t cfg_tgtaddr_3; 120 }; 121 struct udma_gen_vmpr { 122 /* [0x0] TX VMPR control */ 123 uint32_t cfg_vmpr_0; 124 /* [0x4] TX VMPR Address High Regsiter */ 125 uint32_t cfg_vmpr_1; 126 /* [0x8] TX queue Target-ID values */ 127 uint32_t cfg_vmpr_2; 128 /* [0xc] TX queue Target-ID values */ 129 uint32_t cfg_vmpr_3; 130 /* [0x10] RX VMPR control */ 131 uint32_t cfg_vmpr_4; 132 /* [0x14] RX VMPR Buffer2 MSB address */ 133 uint32_t cfg_vmpr_5; 134 /* [0x18] RX queue Target-ID values */ 135 uint32_t cfg_vmpr_6; 136 /* [0x1c] RX queue BUF1 Target-ID values */ 137 uint32_t cfg_vmpr_7; 138 /* [0x20] RX queue BUF2 Target-ID values */ 139 uint32_t cfg_vmpr_8; 140 /* [0x24] RX queue Direct Data Placement Target-ID values */ 141 uint32_t cfg_vmpr_9; 142 /* [0x28] RX VMPR BUF1 Address High Regsiter */ 143 uint32_t cfg_vmpr_10; 144 /* [0x2c] RX VMPR BUF2 Address High Regsiter */ 145 uint32_t cfg_vmpr_11; 146 /* [0x30] RX VMPR DDP Address High Regsiter */ 147 uint32_t cfg_vmpr_12; 148 uint32_t rsrvd[3]; 149 }; 150 151 struct udma_gen_regs { 152 struct udma_iofic_regs interrupt_regs; /* [0x0000] */ 153 struct udma_gen_dma_misc dma_misc; /* [0x2080] */ 154 struct udma_gen_mailbox mailbox[4]; /* [0x2180] */ 155 struct udma_gen_axi axi; /* [0x2280] */ 156 struct udma_gen_sram_ctrl sram_ctrl[25]; /* [0x2380] */ 157 uint32_t rsrvd_1[2]; 158 struct udma_gen_tgtid tgtid; /* [0x23ec] */ 159 struct udma_gen_tgtaddr tgtaddr; /* [0x2400] */ 160 uint32_t rsrvd_2[252]; 161 struct udma_gen_vmpr vmpr[4]; /* [0x2800] */ 162 }; 163 164 165 /* 166 * Registers Fields 167 */ 168 169 170 /**** int_cfg register ****/ 171 /* 172 * MSIX data width 173 * 1 - 64 bit 174 * 0 – 32 bit 175 */ 176 #define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_64 (1 << 0) 177 /* General configuration */ 178 #define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_3_1_MASK 0x0000000E 179 #define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_3_1_SHIFT 1 180 /* MSIx AXI QoS */ 181 #define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_AXI_QOS_MASK 0x00000070 182 #define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_AXI_QOS_SHIFT 4 183 184 #define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_31_7_MASK 0xFFFFFF80 185 #define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_31_7_SHIFT 7 186 187 /**** revision register ****/ 188 /* Design programming interface revision ID */ 189 #define UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_MASK 0x00000FFF 190 #define UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_SHIFT 0 191 /* Design minor revision ID */ 192 #define UDMA_GEN_DMA_MISC_REVISION_MINOR_ID_MASK 0x00FFF000 193 #define UDMA_GEN_DMA_MISC_REVISION_MINOR_ID_SHIFT 12 194 /* Design major revision ID */ 195 #define UDMA_GEN_DMA_MISC_REVISION_MAJOR_ID_MASK 0xFF000000 196 #define UDMA_GEN_DMA_MISC_REVISION_MAJOR_ID_SHIFT 24 197 198 /**** Interrupt register ****/ 199 /* Generate interrupt to another DMA */ 200 #define UDMA_GEN_MAILBOX_INTERRUPT_SET (1 << 0) 201 202 /**** cfg_2 register ****/ 203 /* 204 * Enable arbitration promotion. 205 * Increment master priority after configured number of arbitration cycles 206 */ 207 #define UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_MASK 0x0000000F 208 #define UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_SHIFT 0 209 210 /**** endian_cfg register ****/ 211 /* Swap M2S descriptor read and completion descriptor write. */ 212 #define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC (1 << 0) 213 /* Swap M2S data read. */ 214 #define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DATA (1 << 1) 215 /* Swap S2M descriptor read and completion descriptor write. */ 216 #define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DESC (1 << 2) 217 /* Swap S2M data write. */ 218 #define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA (1 << 3) 219 /* 220 * Swap 32 or 64 bit mode: 221 * 0 - Swap groups of 4 bytes 222 * 1 - Swap groups of 8 bytes 223 */ 224 #define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN (1 << 4) 225 226 /**** timing register ****/ 227 /* Write margin */ 228 #define UDMA_GEN_SRAM_CTRL_TIMING_RMA_MASK 0x0000000F 229 #define UDMA_GEN_SRAM_CTRL_TIMING_RMA_SHIFT 0 230 /* Write margin enable */ 231 #define UDMA_GEN_SRAM_CTRL_TIMING_RMEA (1 << 8) 232 /* Read margin */ 233 #define UDMA_GEN_SRAM_CTRL_TIMING_RMB_MASK 0x000F0000 234 #define UDMA_GEN_SRAM_CTRL_TIMING_RMB_SHIFT 16 235 /* Read margin enable */ 236 #define UDMA_GEN_SRAM_CTRL_TIMING_RMEB (1 << 24) 237 238 /**** cfg_tgtid_0 register ****/ 239 /* For M2S queues 3:0, enable usage of the Target-ID from the buffer address 63:56 */ 240 #define UDMA_GEN_TGTID_CFG_TGTID_0_TX_Q_TGTID_DESC_EN_MASK 0x0000000F 241 #define UDMA_GEN_TGTID_CFG_TGTID_0_TX_Q_TGTID_DESC_EN_SHIFT 0 242 /* 243 * For M2S queues 3:0, enable usage of the Target-ID from the configuration register 244 * (cfg_tgtid_1/2 used for M2S queue_x) 245 */ 246 #define UDMA_GEN_TGTID_CFG_TGTID_0_TX_Q_TGTID_QUEUE_EN_MASK 0x000000F0 247 #define UDMA_GEN_TGTID_CFG_TGTID_0_TX_Q_TGTID_QUEUE_EN_SHIFT 4 248 /* use Target-ID_n [7:0] from MSI-X Controller for MSI-X message */ 249 #define UDMA_GEN_TGTID_CFG_TGTID_0_MSIX_TGTID_SEL (1 << 8) 250 /* Enable write to all Target-ID_n registers in the MSI-X Controller */ 251 #define UDMA_GEN_TGTID_CFG_TGTID_0_MSIX_TGTID_ACCESS_EN (1 << 9) 252 /* For S2M queues 3:0, enable usage of the Target-ID from the buffer address 63:56 */ 253 #define UDMA_GEN_TGTID_CFG_TGTID_0_RX_Q_TGTID_DESC_EN_MASK 0x000F0000 254 #define UDMA_GEN_TGTID_CFG_TGTID_0_RX_Q_TGTID_DESC_EN_SHIFT 16 255 /* 256 * For S2M queues 3:0, enable usage of the Target-ID from the configuration register 257 * (cfg_tgtid_3/4 used for M2S queue_x) 258 */ 259 #define UDMA_GEN_TGTID_CFG_TGTID_0_RX_Q_TGTID_QUEUE_EN_MASK 0x00F00000 260 #define UDMA_GEN_TGTID_CFG_TGTID_0_RX_Q_TGTID_QUEUE_EN_SHIFT 20 261 262 #define UDMA_GEN_TGTID_CFG_TGTID_SHIFT(qid) (((qid) & 0x1) ? 16 : 0) 263 #define UDMA_GEN_TGTID_CFG_TGTID_MASK(qid) (((qid) & 0x1) ? 0xFFFF0000 : 0x0000FFFF) 264 265 /**** cfg_tgtid_1 register ****/ 266 /* TX queue 0 Target-ID value */ 267 #define UDMA_GEN_TGTID_CFG_TGTID_1_TX_Q_0_TGTID_MASK 0x0000FFFF 268 #define UDMA_GEN_TGTID_CFG_TGTID_1_TX_Q_0_TGTID_SHIFT 0 269 /* TX queue 1 Target-ID value */ 270 #define UDMA_GEN_TGTID_CFG_TGTID_1_TX_Q_1_TGTID_MASK 0xFFFF0000 271 #define UDMA_GEN_TGTID_CFG_TGTID_1_TX_Q_1_TGTID_SHIFT 16 272 273 /**** cfg_tgtid_2 register ****/ 274 /* TX queue 2 Target-ID value */ 275 #define UDMA_GEN_TGTID_CFG_TGTID_2_TX_Q_2_TGTID_MASK 0x0000FFFF 276 #define UDMA_GEN_TGTID_CFG_TGTID_2_TX_Q_2_TGTID_SHIFT 0 277 /* TX queue 3 Target-ID value */ 278 #define UDMA_GEN_TGTID_CFG_TGTID_2_TX_Q_3_TGTID_MASK 0xFFFF0000 279 #define UDMA_GEN_TGTID_CFG_TGTID_2_TX_Q_3_TGTID_SHIFT 16 280 281 /**** cfg_tgtid_3 register ****/ 282 /* RX queue 0 Target-ID value */ 283 #define UDMA_GEN_TGTID_CFG_TGTID_3_RX_Q_0_TGTID_MASK 0x0000FFFF 284 #define UDMA_GEN_TGTID_CFG_TGTID_3_RX_Q_0_TGTID_SHIFT 0 285 /* RX queue 1 Target-ID value */ 286 #define UDMA_GEN_TGTID_CFG_TGTID_3_RX_Q_1_TGTID_MASK 0xFFFF0000 287 #define UDMA_GEN_TGTID_CFG_TGTID_3_RX_Q_1_TGTID_SHIFT 16 288 289 /**** cfg_tgtid_4 register ****/ 290 /* RX queue 2 Target-ID value */ 291 #define UDMA_GEN_TGTID_CFG_TGTID_4_RX_Q_2_TGTID_MASK 0x0000FFFF 292 #define UDMA_GEN_TGTID_CFG_TGTID_4_RX_Q_2_TGTID_SHIFT 0 293 /* RX queue 3 Target-ID value */ 294 #define UDMA_GEN_TGTID_CFG_TGTID_4_RX_Q_3_TGTID_MASK 0xFFFF0000 295 #define UDMA_GEN_TGTID_CFG_TGTID_4_RX_Q_3_TGTID_SHIFT 16 296 297 #define UDMA_GEN_TGTADDR_CFG_SHIFT(qid) (((qid) & 0x1) ? 16 : 0) 298 #define UDMA_GEN_TGTADDR_CFG_MASK(qid) (((qid) & 0x1) ? 0xFFFF0000 : 0x0000FFFF) 299 300 /**** cfg_tgtaddr_0 register ****/ 301 /* TX queue 0 Target-Address value */ 302 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_0_TX_Q_0_TGTADDR_MASK 0x0000FFFF 303 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_0_TX_Q_0_TGTADDR_SHIFT 0 304 /* TX queue 1 Target-Address value */ 305 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_0_TX_Q_1_TGTADDR_MASK 0xFFFF0000 306 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_0_TX_Q_1_TGTADDR_SHIFT 16 307 308 /**** cfg_tgtaddr_1 register ****/ 309 /* TX queue 2 Target-Address value */ 310 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_1_TX_Q_2_TGTADDR_MASK 0x0000FFFF 311 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_1_TX_Q_2_TGTADDR_SHIFT 0 312 /* TX queue 3 Target-Address value */ 313 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_1_TX_Q_3_TGTADDR_MASK 0xFFFF0000 314 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_1_TX_Q_3_TGTADDR_SHIFT 16 315 316 /**** cfg_tgtaddr_2 register ****/ 317 /* RX queue 0 Target-Address value */ 318 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_2_RX_Q_0_TGTADDR_MASK 0x0000FFFF 319 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_2_RX_Q_0_TGTADDR_SHIFT 0 320 /* RX queue 1 Target-Address value */ 321 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_2_RX_Q_1_TGTADDR_MASK 0xFFFF0000 322 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_2_RX_Q_1_TGTADDR_SHIFT 16 323 324 /**** cfg_tgtaddr_3 register ****/ 325 /* RX queue 2 Target-Address value */ 326 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_3_RX_Q_2_TGTADDR_MASK 0x0000FFFF 327 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_3_RX_Q_2_TGTADDR_SHIFT 0 328 /* RX queue 3 Target-Address value */ 329 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_3_RX_Q_3_TGTADDR_MASK 0xFFFF0000 330 #define UDMA_GEN_TGTADDR_CFG_TGTADDR_3_RX_Q_3_TGTADDR_SHIFT 16 331 332 /**** cfg_vmpr_0 register ****/ 333 /* TX High Address Select Per Q */ 334 #define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_MASK 0x0000003F 335 #define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_SHIFT 0 336 /* TX Data Target-ID Enable Per Q */ 337 #define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_DATA_TGTID_EN (1 << 7) 338 /* TX Prefetch Target-ID Enable Per Q */ 339 #define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_PREF_TGTID_EN (1 << 28) 340 /* TX Completions Target-ID Enable Per Q */ 341 #define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_CMPL_TGTID_EN (1 << 29) 342 343 /**** cfg_vmpr_2 register ****/ 344 /* TX queue Prefetch Target-ID */ 345 #define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_TGTID_MASK 0x0000FFFF 346 #define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_TGTID_SHIFT 0 347 /* TX queue Completion Target-ID */ 348 #define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_TGTID_MASK 0xFFFF0000 349 #define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_TGTID_SHIFT 16 350 351 /**** cfg_vmpr_3 register ****/ 352 /* TX queue Data Target-ID */ 353 #define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_TGTID_MASK 0x0000FFFF 354 #define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_TGTID_SHIFT 0 355 /* TX queue Data Target-ID select */ 356 #define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_TGTID_SEL_MASK 0xFFFF0000 357 #define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_TGTID_SEL_SHIFT 16 358 359 /**** cfg_vmpr_4 register ****/ 360 /* RX Data Buffer1 - High Address Select Per Q */ 361 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_MASK 0x0000003F 362 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_SHIFT 0 363 /* RX Data Buffer1 Target-ID Enable Per Q */ 364 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_TGTID_EN (1 << 7) 365 /* RX Data Buffer2 - High Address Select Per Q */ 366 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_MASK 0x00003F00 367 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_SHIFT 8 368 /* RX Data Buffer2 Target-ID Enable Per Q */ 369 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_TGTID_EN (1 << 15) 370 /* RX Direct Data Placement - High Address Select Per Q */ 371 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_MASK 0x003F0000 372 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_SHIFT 16 373 /* RX Direct Data Placement Target-ID Enable Per Q */ 374 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_TGTID_EN (1 << 23) 375 /* RX Buffer 2 MSB address word selects per bytes, per queue */ 376 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_MASK 0x0F000000 377 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_SHIFT 24 378 /* RX Prefetch Target-ID Enable Per Q */ 379 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_PREF_TGTID_EN (1 << 28) 380 /* RX Completions Target-ID Enable Per Q */ 381 #define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_CMPL_TGTID_EN (1 << 29) 382 383 /**** cfg_vmpr_6 register ****/ 384 /* RX queue Prefetch Target-ID */ 385 #define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_TGTID_MASK 0x0000FFFF 386 #define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_TGTID_SHIFT 0 387 /* RX queue Completion Target-ID */ 388 #define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_TGTID_MASK 0xFFFF0000 389 #define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_TGTID_SHIFT 16 390 391 /**** cfg_vmpr_7 register ****/ 392 /* RX queue Data Buffer 1 Target-ID */ 393 #define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_TGTID_MASK 0x0000FFFF 394 #define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_TGTID_SHIFT 0 395 /* RX queue Data Buffer 1 Target-ID select */ 396 #define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_TGTID_SEL_MASK 0xFFFF0000 397 #define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_TGTID_SEL_SHIFT 16 398 399 /**** cfg_vmpr_8 register ****/ 400 /* RX queue Data Buffer 2 Target-ID */ 401 #define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_TGTID_MASK 0x0000FFFF 402 #define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_TGTID_SHIFT 0 403 /* RX queue Data Buffer 2 Target-ID select */ 404 #define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_TGTID_SEL_MASK 0xFFFF0000 405 #define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_TGTID_SEL_SHIFT 16 406 407 /**** cfg_vmpr_9 register ****/ 408 /* RX queue DDP Target-ID */ 409 #define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_TGTID_MASK 0x0000FFFF 410 #define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_TGTID_SHIFT 0 411 /* RX queue DDP Target-ID select */ 412 #define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_TGTID_SEL_MASK 0xFFFF0000 413 #define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_TGTID_SEL_SHIFT 16 414 415 #ifdef __cplusplus 416 } 417 #endif 418 419 #endif /* __AL_HAL_UDMA_GEN_REG_H */ 420