1 /*- 2 ******************************************************************************* 3 Copyright (C) 2015 Annapurna Labs Ltd. 4 5 This file may be licensed under the terms of the Annapurna Labs Commercial 6 License Agreement. 7 8 Alternatively, this file can be distributed under the terms of the GNU General 9 Public License V2 as published by the Free Software Foundation and can be 10 found at http://www.gnu.org/licenses/gpl-2.0.html 11 12 Alternatively, redistribution and use in source and binary forms, with or 13 without modification, are permitted provided that the following conditions are 14 met: 15 16 * Redistributions of source code must retain the above copyright notice, 17 this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20 notice, this list of conditions and the following disclaimer in 21 the documentation and/or other materials provided with the 22 distribution. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35 *******************************************************************************/ 36 37 /** 38 * @{ 39 * @file al_hal_serdes_regs.h 40 * 41 * @brief ... registers 42 * 43 */ 44 45 #ifndef __AL_HAL_SERDES_REGS_H__ 46 #define __AL_HAL_SERDES_REGS_H__ 47 48 #include "al_hal_plat_types.h" 49 50 #ifdef __cplusplus 51 extern "C" { 52 #endif 53 /* 54 * Unit Registers 55 */ 56 57 struct serdes_gen { 58 /* [0x0] SerDes Registers Version */ 59 uint32_t version; 60 uint32_t rsrvd_0[3]; 61 /* [0x10] SerDes register file address */ 62 uint32_t reg_addr; 63 /* [0x14] SerDes register file data */ 64 uint32_t reg_data; 65 uint32_t rsrvd_1[2]; 66 /* [0x20] SerDes control */ 67 uint32_t ictl_multi_bist; 68 /* [0x24] SerDes control */ 69 uint32_t ictl_pcs; 70 /* [0x28] SerDes control */ 71 uint32_t ictl_pma; 72 uint32_t rsrvd_2; 73 /* [0x30] SerDes control */ 74 uint32_t ipd_multi_synth; 75 /* [0x34] SerDes control */ 76 uint32_t irst; 77 /* [0x38] SerDes control */ 78 uint32_t octl_multi_synthready; 79 /* [0x3c] SerDes control */ 80 uint32_t octl_multi_synthstatus; 81 /* [0x40] SerDes control */ 82 uint32_t clk_out; 83 uint32_t rsrvd[47]; 84 }; 85 struct serdes_lane { 86 uint32_t rsrvd1[4]; 87 /* [0x10] SerDes status */ 88 uint32_t octl_pma; 89 /* [0x14] SerDes control */ 90 uint32_t ictl_multi_andme; 91 /* [0x18] SerDes control */ 92 uint32_t ictl_multi_lb; 93 /* [0x1c] SerDes control */ 94 uint32_t ictl_multi_rxbist; 95 /* [0x20] SerDes control */ 96 uint32_t ictl_multi_txbist; 97 /* [0x24] SerDes control */ 98 uint32_t ictl_multi; 99 /* [0x28] SerDes control */ 100 uint32_t ictl_multi_rxeq; 101 /* [0x2c] SerDes control */ 102 uint32_t ictl_multi_rxeq_l_low; 103 /* [0x30] SerDes control */ 104 uint32_t ictl_multi_rxeq_l_high; 105 /* [0x34] SerDes control */ 106 uint32_t ictl_multi_rxeyediag; 107 /* [0x38] SerDes control */ 108 uint32_t ictl_multi_txdeemph; 109 /* [0x3c] SerDes control */ 110 uint32_t ictl_multi_txmargin; 111 /* [0x40] SerDes control */ 112 uint32_t ictl_multi_txswing; 113 /* [0x44] SerDes control */ 114 uint32_t idat_multi; 115 /* [0x48] SerDes control */ 116 uint32_t ipd_multi; 117 /* [0x4c] SerDes control */ 118 uint32_t octl_multi_rxbist; 119 /* [0x50] SerDes control */ 120 uint32_t octl_multi; 121 /* [0x54] SerDes control */ 122 uint32_t octl_multi_rxeyediag; 123 /* [0x58] SerDes control */ 124 uint32_t odat_multi_rxbist; 125 /* [0x5c] SerDes control */ 126 uint32_t odat_multi_rxeq; 127 /* [0x60] SerDes control */ 128 uint32_t multi_rx_dvalid; 129 /* [0x64] SerDes control */ 130 uint32_t reserved; 131 uint32_t rsrvd[6]; 132 }; 133 134 struct al_serdes_regs { 135 uint32_t rsrvd_0[64]; 136 struct serdes_gen gen; /* [0x100] */ 137 struct serdes_lane lane[4]; /* [0x200] */ 138 }; 139 140 141 /* 142 * Registers Fields 143 */ 144 145 146 /**** version register ****/ 147 /* Revision number (Minor) */ 148 #define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF 149 #define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0 150 /* Revision number (Major) */ 151 #define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00 152 #define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8 153 /* Date of release */ 154 #define SERDES_GEN_VERSION_DATE_DAY_MASK 0x001F0000 155 #define SERDES_GEN_VERSION_DATE_DAY_SHIFT 16 156 /* Month of release */ 157 #define SERDES_GEN_VERSION_DATA_MONTH_MASK 0x01E00000 158 #define SERDES_GEN_VERSION_DATA_MONTH_SHIFT 21 159 /* Year of release (starting from 2000) */ 160 #define SERDES_GEN_VERSION_DATE_YEAR_MASK 0x3E000000 161 #define SERDES_GEN_VERSION_DATE_YEAR_SHIFT 25 162 /* Reserved */ 163 #define SERDES_GEN_VERSION_RESERVED_MASK 0xC0000000 164 #define SERDES_GEN_VERSION_RESERVED_SHIFT 30 165 166 /**** reg_addr register ****/ 167 /* Address value */ 168 #define SERDES_GEN_REG_ADDR_VAL_MASK 0x0000FFFF 169 #define SERDES_GEN_REG_ADDR_VAL_SHIFT 0 170 171 /**** reg_data register ****/ 172 /* Data value */ 173 #define SERDES_GEN_REG_DATA_VAL_MASK 0x000000FF 174 #define SERDES_GEN_REG_DATA_VAL_SHIFT 0 175 176 /**** ICTL_MULTI_BIST register ****/ 177 178 #define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_MASK 0x00000007 179 #define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_SHIFT 0 180 181 /**** ICTL_PCS register ****/ 182 183 #define SERDES_GEN_ICTL_PCS_EN_NT (1 << 0) 184 185 /**** ICTL_PMA register ****/ 186 187 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_MASK 0x00000007 188 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT 0 189 190 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_REF \ 191 (0 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT)) 192 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_R2L \ 193 (3 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT)) 194 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_L2R \ 195 (4 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT)) 196 197 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_MASK 0x00000070 198 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT 4 199 200 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_0 \ 201 (0 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT)) 202 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_REF \ 203 (2 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT)) 204 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_R2L \ 205 (3 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT)) 206 207 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_MASK 0x00000700 208 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT 8 209 210 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_0 \ 211 (0 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT)) 212 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_REF \ 213 (2 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT)) 214 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_L2R \ 215 (3 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT)) 216 217 #define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC (1 << 11) 218 #define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_THIS (0 << 11) 219 #define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_MASTER (1 << 11) 220 221 #define SERDES_GEN_ICTL_PMA_TXENABLE_A (1 << 12) 222 223 #define SERDES_GEN_ICTL_PMA_SYNTHCKBYPASSEN_NT (1 << 13) 224 225 /**** IPD_MULTI_SYNTH register ****/ 226 227 #define SERDES_GEN_IPD_MULTI_SYNTH_B (1 << 0) 228 229 /**** IRST register ****/ 230 231 #define SERDES_GEN_IRST_PIPE_RST_L3_B_A (1 << 0) 232 233 #define SERDES_GEN_IRST_PIPE_RST_L2_B_A (1 << 1) 234 235 #define SERDES_GEN_IRST_PIPE_RST_L1_B_A (1 << 2) 236 237 #define SERDES_GEN_IRST_PIPE_RST_L0_B_A (1 << 3) 238 239 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A (1 << 4) 240 241 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A (1 << 5) 242 243 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A (1 << 6) 244 245 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A (1 << 7) 246 247 #define SERDES_GEN_IRST_MULTI_HARD_SYNTH_B_A (1 << 8) 248 249 #define SERDES_GEN_IRST_POR_B_A (1 << 12) 250 251 #define SERDES_GEN_IRST_PIPE_RST_L3_B_A_SEL (1 << 16) 252 253 #define SERDES_GEN_IRST_PIPE_RST_L2_B_A_SEL (1 << 17) 254 255 #define SERDES_GEN_IRST_PIPE_RST_L1_B_A_SEL (1 << 18) 256 257 #define SERDES_GEN_IRST_PIPE_RST_L0_B_A_SEL (1 << 19) 258 259 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A_SEL (1 << 20) 260 261 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A_SEL (1 << 21) 262 263 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A_SEL (1 << 22) 264 265 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A_SEL (1 << 23) 266 267 /**** OCTL_MULTI_SYNTHREADY register ****/ 268 269 #define SERDES_GEN_OCTL_MULTI_SYNTHREADY_A (1 << 0) 270 271 /**** OCTL_MULTI_SYNTHSTATUS register ****/ 272 273 #define SERDES_GEN_OCTL_MULTI_SYNTHSTATUS_A (1 << 0) 274 275 /**** clk_out register ****/ 276 277 #define SERDES_GEN_CLK_OUT_SEL_MASK 0x0000003F 278 #define SERDES_GEN_CLK_OUT_SEL_SHIFT 0 279 280 /**** OCTL_PMA register ****/ 281 282 #define SERDES_LANE_OCTL_PMA_TXSTATUS_L_A (1 << 0) 283 284 /**** ICTL_MULTI_ANDME register ****/ 285 286 #define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A (1 << 0) 287 288 #define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A_SEL (1 << 1) 289 290 /**** ICTL_MULTI_LB register ****/ 291 292 #define SERDES_LANE_ICTL_MULTI_LB_TX2RXIOTIMEDEN_L_NT (1 << 0) 293 294 #define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT (1 << 1) 295 296 #define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT (1 << 2) 297 298 #define SERDES_LANE_ICTL_MULTI_LB_PARRX2TXTIMEDEN_L_NT (1 << 3) 299 300 #define SERDES_LANE_ICTL_MULTI_LB_CDRCLK2TXEN_L_NT (1 << 4) 301 302 #define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT_SEL (1 << 8) 303 304 #define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT_SEL (1 << 9) 305 306 /**** ICTL_MULTI_RXBIST register ****/ 307 308 #define SERDES_LANE_ICTL_MULTI_RXBIST_EN_L_A (1 << 0) 309 310 /**** ICTL_MULTI_TXBIST register ****/ 311 312 #define SERDES_LANE_ICTL_MULTI_TXBIST_EN_L_A (1 << 0) 313 314 /**** ICTL_MULTI register ****/ 315 316 #define SERDES_LANE_ICTL_MULTI_PSTATE_L_MASK 0x00000003 317 #define SERDES_LANE_ICTL_MULTI_PSTATE_L_SHIFT 0 318 319 #define SERDES_LANE_ICTL_MULTI_PSTATE_L_SEL (1 << 2) 320 321 #define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_MASK 0x00000070 322 #define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_SHIFT 4 323 324 #define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATAEN_L_A (1 << 8) 325 326 #define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATA_L_A (1 << 9) 327 328 #define SERDES_LANE_ICTL_MULTI_TXBEACON_L_A (1 << 12) 329 330 #define SERDES_LANE_ICTL_MULTI_TXDETECTRXREQ_L_A (1 << 13) 331 332 #define SERDES_LANE_ICTL_MULTI_RXRATE_L_MASK 0x00070000 333 #define SERDES_LANE_ICTL_MULTI_RXRATE_L_SHIFT 16 334 335 #define SERDES_LANE_ICTL_MULTI_RXRATE_L_SEL (1 << 19) 336 337 #define SERDES_LANE_ICTL_MULTI_TXRATE_L_MASK 0x00700000 338 #define SERDES_LANE_ICTL_MULTI_TXRATE_L_SHIFT 20 339 340 #define SERDES_LANE_ICTL_MULTI_TXRATE_L_SEL (1 << 23) 341 342 #define SERDES_LANE_ICTL_MULTI_TXAMP_L_MASK 0x07000000 343 #define SERDES_LANE_ICTL_MULTI_TXAMP_L_SHIFT 24 344 345 #define SERDES_LANE_ICTL_MULTI_TXAMP_EN_L (1 << 27) 346 347 #define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_MASK 0x70000000 348 #define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_SHIFT 28 349 350 /**** ICTL_MULTI_RXEQ register ****/ 351 352 #define SERDES_LANE_ICTL_MULTI_RXEQ_EN_L (1 << 0) 353 354 #define SERDES_LANE_ICTL_MULTI_RXEQ_START_L_A (1 << 1) 355 356 #define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_MASK 0x00000070 357 #define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_SHIFT 4 358 359 /**** ICTL_MULTI_RXEQ_L_high register ****/ 360 361 #define SERDES_LANE_ICTL_MULTI_RXEQ_L_HIGH_VAL (1 << 0) 362 363 /**** ICTL_MULTI_RXEYEDIAG register ****/ 364 365 #define SERDES_LANE_ICTL_MULTI_RXEYEDIAG_START_L_A (1 << 0) 366 367 /**** ICTL_MULTI_TXDEEMPH register ****/ 368 369 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_MASK 0x0003FFFF 370 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_SHIFT 0 371 372 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_MASK 0x7c0 373 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_SHIFT 6 374 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_MASK 0xf000 375 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_SHIFT 12 376 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_MASK 0x7 377 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_SHIFT 0 378 379 /**** ICTL_MULTI_TXMARGIN register ****/ 380 381 #define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_MASK 0x00000007 382 #define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_SHIFT 0 383 384 /**** ICTL_MULTI_TXSWING register ****/ 385 386 #define SERDES_LANE_ICTL_MULTI_TXSWING_L (1 << 0) 387 388 /**** IDAT_MULTI register ****/ 389 390 #define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_MASK 0x0000000F 391 #define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SHIFT 0 392 393 #define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SEL (1 << 4) 394 395 /**** IPD_MULTI register ****/ 396 397 #define SERDES_LANE_IPD_MULTI_TX_L_B (1 << 0) 398 399 #define SERDES_LANE_IPD_MULTI_RX_L_B (1 << 1) 400 401 /**** OCTL_MULTI_RXBIST register ****/ 402 403 #define SERDES_LANE_OCTL_MULTI_RXBIST_DONE_L_A (1 << 0) 404 405 #define SERDES_LANE_OCTL_MULTI_RXBIST_RXLOCKED_L_A (1 << 1) 406 407 /**** OCTL_MULTI register ****/ 408 409 #define SERDES_LANE_OCTL_MULTI_RXCDRLOCK2DATA_L_A (1 << 0) 410 411 #define SERDES_LANE_OCTL_MULTI_RXEQ_DONE_L_A (1 << 1) 412 413 #define SERDES_LANE_OCTL_MULTI_RXREADY_L_A (1 << 2) 414 415 #define SERDES_LANE_OCTL_MULTI_RXSTATUS_L_A (1 << 3) 416 417 #define SERDES_LANE_OCTL_MULTI_TXREADY_L_A (1 << 4) 418 419 #define SERDES_LANE_OCTL_MULTI_TXDETECTRXSTAT_L_A (1 << 5) 420 421 #define SERDES_LANE_OCTL_MULTI_TXDETECTRXACK_L_A (1 << 6) 422 423 #define SERDES_LANE_OCTL_MULTI_RXSIGNALDETECT_L_A (1 << 7) 424 425 /**** OCTL_MULTI_RXEYEDIAG register ****/ 426 427 #define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_MASK 0x00003FFF 428 #define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_SHIFT 0 429 430 #define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_DONE_L_A (1 << 16) 431 432 #define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_ERR_L_A (1 << 17) 433 434 /**** ODAT_MULTI_RXBIST register ****/ 435 436 #define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_MASK 0x0000FFFF 437 #define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_SHIFT 0 438 439 #define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_OVERFLOW_L_A (1 << 16) 440 441 /**** ODAT_MULTI_RXEQ register ****/ 442 443 #define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_MASK 0x00003FFF 444 #define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_SHIFT 0 445 446 /**** MULTI_RX_DVALID register ****/ 447 448 #define SERDES_LANE_MULTI_RX_DVALID_MASK_CDR_LOCK (1 << 0) 449 450 #define SERDES_LANE_MULTI_RX_DVALID_MASK_SIGNALDETECT (1 << 1) 451 452 #define SERDES_LANE_MULTI_RX_DVALID_MASK_TX_READY (1 << 2) 453 454 #define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_READY (1 << 3) 455 456 #define SERDES_LANE_MULTI_RX_DVALID_MASK_SYNT_READY (1 << 4) 457 458 #define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_ELECIDLE (1 << 5) 459 460 #define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_MASK 0x00FF0000 461 #define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_SHIFT 16 462 463 #define SERDES_LANE_MULTI_RX_DVALID_PS_00_SEL (1 << 24) 464 465 #define SERDES_LANE_MULTI_RX_DVALID_PS_00_VAL (1 << 25) 466 467 #define SERDES_LANE_MULTI_RX_DVALID_PS_01_SEL (1 << 26) 468 469 #define SERDES_LANE_MULTI_RX_DVALID_PS_01_VAL (1 << 27) 470 471 #define SERDES_LANE_MULTI_RX_DVALID_PS_10_SEL (1 << 28) 472 473 #define SERDES_LANE_MULTI_RX_DVALID_PS_10_VAL (1 << 29) 474 475 #define SERDES_LANE_MULTI_RX_DVALID_PS_11_SEL (1 << 30) 476 477 #define SERDES_LANE_MULTI_RX_DVALID_PS_11_VAL (1 << 31) 478 479 /**** reserved register ****/ 480 481 #define SERDES_LANE_RESERVED_OUT_MASK 0x000000FF 482 #define SERDES_LANE_RESERVED_OUT_SHIFT 0 483 484 #define SERDES_LANE_RESERVED_IN_MASK 0x00FF0000 485 #define SERDES_LANE_RESERVED_IN_SHIFT 16 486 487 #ifdef __cplusplus 488 } 489 #endif 490 491 #endif /* __AL_HAL_serdes_REGS_H__ */ 492 493 /** @} end of ... group */ 494 495 496