1 /******************************************************************************* 2 Copyright (C) 2013 Annapurna Labs Ltd. 3 4 This file may be licensed under the terms of the Annapurna Labs Commercial 5 License Agreement. 6 7 Alternatively, this file can be distributed under the terms of the GNU General 8 Public License V2 or V3 as published by the Free Software Foundation and can be 9 found at http://www.gnu.org/licenses/gpl-2.0.html 10 11 Alternatively, redistribution and use in source and binary forms, with or 12 without modification, are permitted provided that the following conditions are 13 met: 14 15 * Redistributions of source code must retain the above copyright notice, 16 this list of conditions and the following disclaimer. 17 18 * Redistributions in binary form must reproduce the above copyright 19 notice, this list of conditions and the following disclaimer in 20 the documentation and/or other materials provided with the 21 distribution. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 24 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 27 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 34 *******************************************************************************/ 35 36 /** 37 * @{ 38 * @file al_hal_serdes_c_regs.h 39 * 40 * @brief ... registers 41 * 42 */ 43 44 #ifndef __AL_HAL_serdes_c_REGS_H__ 45 #define __AL_HAL_serdes_c_REGS_H__ 46 47 #include "al_hal_plat_types.h" 48 49 #ifdef __cplusplus 50 extern "C" { 51 #endif 52 /* 53 * Unit Registers 54 */ 55 56 struct al_serdes_c_gen { 57 /* [0x0] SERDES registers Version */ 58 uint32_t version; 59 uint32_t rsrvd_0[3]; 60 /* [0x10] SERDES register file address */ 61 uint32_t reg_addr; 62 /* [0x14] SERDES register file data */ 63 uint32_t reg_data; 64 /* [0x18] SERDES control */ 65 uint32_t ctrl; 66 /* [0x1c] SERDES cpu mem address */ 67 uint32_t cpu_prog_addr; 68 /* [0x20] SERDES cpu mem data */ 69 uint32_t cpu_prog_data; 70 /* [0x24] SERDES data mem address */ 71 uint32_t cpu_data_mem_addr; 72 /* [0x28] SERDES data mem data */ 73 uint32_t cpu_data_mem_data; 74 /* [0x2c] SERDES control */ 75 uint32_t rst; 76 /* [0x30] SERDES control */ 77 uint32_t status; 78 uint32_t rsrvd[51]; 79 }; 80 struct al_serdes_c_lane { 81 uint32_t rsrvd_0[4]; 82 /* [0x10] Data configuration */ 83 uint32_t cfg; 84 /* [0x14] Lane status */ 85 uint32_t stat; 86 /* [0x18] SERDES control */ 87 uint32_t reserved; 88 uint32_t rsrvd[25]; 89 }; 90 91 struct al_serdes_c_regs { 92 uint32_t rsrvd_0[64]; 93 struct al_serdes_c_gen gen; /* [0x100] */ 94 struct al_serdes_c_lane lane[2]; /* [0x200] */ 95 }; 96 97 98 /* 99 * Registers Fields 100 */ 101 102 103 /**** version register ****/ 104 /* Revision number (Minor) */ 105 #define SERDES_C_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF 106 #define SERDES_C_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0 107 /* Revision number (Major) */ 108 #define SERDES_C_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00 109 #define SERDES_C_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8 110 /* date of release */ 111 #define SERDES_C_GEN_VERSION_DATE_DAY_MASK 0x001F0000 112 #define SERDES_C_GEN_VERSION_DATE_DAY_SHIFT 16 113 /* month of release */ 114 #define SERDES_C_GEN_VERSION_DATA_MONTH_MASK 0x01E00000 115 #define SERDES_C_GEN_VERSION_DATA_MONTH_SHIFT 21 116 /* year of release (starting from 2000) */ 117 #define SERDES_C_GEN_VERSION_DATE_YEAR_MASK 0x3E000000 118 #define SERDES_C_GEN_VERSION_DATE_YEAR_SHIFT 25 119 /* Reserved */ 120 #define SERDES_C_GEN_VERSION_RESERVED_MASK 0xC0000000 121 #define SERDES_C_GEN_VERSION_RESERVED_SHIFT 30 122 123 /**** reg_addr register ****/ 124 /* address value */ 125 #define SERDES_C_GEN_REG_ADDR_VAL_MASK 0x00007FFF 126 #define SERDES_C_GEN_REG_ADDR_VAL_SHIFT 0 127 128 /**** reg_data register ****/ 129 /* data value */ 130 #define SERDES_C_GEN_REG_DATA_VAL_MASK 0x000000FF 131 #define SERDES_C_GEN_REG_DATA_VAL_SHIFT 0 132 /* Bit-wise write enable */ 133 #define SERDES_C_GEN_REG_DATA_STRB_MASK 0x0000FF00 134 #define SERDES_C_GEN_REG_DATA_STRB_SHIFT 8 135 136 /**** ctrl register ****/ 137 /* 138 * 0x0 – Select reference clock from Bump 139 * 0x1 – Select inter-macro reference clock from the left side 140 * 0x2 – Same as 0x0 141 * 0x3 – Select inter-macro reference clock from the right side 142 */ 143 #define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_MASK 0x00000003 144 #define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT 0 145 146 #define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_REF \ 147 (0 << (SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT)) 148 #define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_L2R \ 149 (1 << (SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT)) 150 #define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_R2L \ 151 (3 << (SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT)) 152 153 /* 154 * 0x0 – Tied to 0 to save power 155 * 0x1 – Select reference clock from Bump 156 * 0x2 – Select inter-macro reference clock input from right side 157 * 0x3 – Same as 0x2 158 */ 159 #define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_MASK 0x00000030 160 #define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT 4 161 162 #define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_0 \ 163 (0 << (SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT)) 164 #define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_REF \ 165 (1 << (SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT)) 166 #define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_R2L \ 167 (2 << (SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT)) 168 169 /* 170 * 0x0 – Tied to 0 to save power 171 * 0x1 – Select reference clock from Bump 172 * 0x2 – Select inter-macro reference clock input from left side 173 * 0x3 – Same as 0x2 174 */ 175 #define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_MASK 0x000000C0 176 #define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT 6 177 178 #define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_0 \ 179 (0 << (SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT)) 180 #define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_REF \ 181 (1 << (SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT)) 182 #define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_L2R \ 183 (2 << (SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT)) 184 185 /* 186 * Program memory acknowledge - Only when the access 187 * to the program memory is not 188 * ready for the microcontroller, it 189 * is driven to 0 190 */ 191 #define SERDES_C_GEN_CTRL_CPU_MEMPSACK (1 << 8) 192 /* 193 * Data memory acknowledge - Only when the access 194 * to the program memory is not 195 * ready for the microcontroller, it 196 * is driven to 0 197 */ 198 #define SERDES_C_GEN_CTRL_CPU_MEMACK (1 << 12) 199 /* 200 * 0 - keep cpu clk as sb clk 201 * 1 – cpu_clk is sb_clk divided by 2 202 */ 203 #define SERDES_C_GEN_CTRL_CPU_CLK_DIV (1 << 16) 204 /* 205 * 0x0 – OIF CEI-28G-SR 206 * 0x1 – OIF CIE-25G-LR 207 * 0x8 – XFI 208 * Others – Reserved 209 * 210 * Note that phy_ctrl_cfg_i[3] is used to signify high-speed/low-speed 211 */ 212 #define SERDES_C_GEN_CTRL_PHY_CTRL_CFG_MASK 0x00F00000 213 #define SERDES_C_GEN_CTRL_PHY_CTRL_CFG_SHIFT 20 214 /* 215 * 0 - Internal 8051 micro- controller is allowed to access the internal APB 216 * CSR. Internal APB runs at cpu_clk_i, and the accesses from the external APB 217 * in apb_clk_i domain to APB CSR are resynchronized to cpu_clk_i. 1 – Bypass 218 * CPU. Internal 8051 micro-controller is blocked from accessing the internal 219 * APB CSR. Internal APB runs at apb_clk_i. 220 */ 221 #define SERDES_C_GEN_CTRL_CPU_BYPASS (1 << 24) 222 223 /**** cpu_prog_addr register ****/ 224 /* 225 * address value 32 bit, 226 * The firmware data will be 1 byte with 64K rows 227 */ 228 #define SERDES_C_GEN_CPU_PROG_ADDR_VAL_MASK 0x00007FFF 229 #define SERDES_C_GEN_CPU_PROG_ADDR_VAL_SHIFT 0 230 231 /**** cpu_data_mem_addr register ****/ 232 /* address value – 8K byte memory */ 233 #define SERDES_C_GEN_CPU_DATA_MEM_ADDR_VAL_MASK 0x00001FFF 234 #define SERDES_C_GEN_CPU_DATA_MEM_ADDR_VAL_SHIFT 0 235 236 /**** cpu_data_mem_data register ****/ 237 /* data value */ 238 #define SERDES_C_GEN_CPU_DATA_MEM_DATA_VAL_MASK 0x000000FF 239 #define SERDES_C_GEN_CPU_DATA_MEM_DATA_VAL_SHIFT 0 240 241 /**** rst register ****/ 242 /* Power on reset Signal – active low */ 243 #define SERDES_C_GEN_RST_POR_N (1 << 0) 244 /* CMU reset Active low */ 245 #define SERDES_C_GEN_RST_CM0_RST_N (1 << 1) 246 /* 247 * 0x0 – Normal / Active 248 * 0x1 – Partial power down 249 * 0x2 – Near complete power down (only 250 * refclk buffers and portions of analog bias 251 * active) 252 * 0x3 – complete power down (IDDQ mode) 253 * Can be asserted when CMU is in normal 254 * mode. These modes provide an increased 255 * power savings compared to reset mode. 256 * Signal is overridden by por_n_i so has no 257 * effect in power on reset state. 258 */ 259 #define SERDES_C_GEN_RST_CM0_PD_MASK 0x00000030 260 #define SERDES_C_GEN_RST_CM0_PD_SHIFT 4 261 /* Lane0 reset signal active low */ 262 #define SERDES_C_GEN_RST_LN0_RST_N (1 << 6) 263 /* Lane1 reset signal active low */ 264 #define SERDES_C_GEN_RST_LN1_RST_N (1 << 7) 265 /* 266 * 0x0 – Normal / Active 267 * 0x1 – Partial power down 268 * 0x2 – Most blocks powered down (only LOS 269 * active) 270 * 0x3 – complete power down (IDDQ mode) 271 * Can be asserted when Lane is in normal 272 * mode. These modes provide an increased 273 * power savings compared to reset mode. 274 * Signal is overridden by por_n_i so has no 275 * affect in power on reset state 276 */ 277 #define SERDES_C_GEN_RST_LN0_PD_MASK 0x00000300 278 #define SERDES_C_GEN_RST_LN0_PD_SHIFT 8 279 /* 280 * 0x0 – Normal / Active 281 * 0x1 – Partial power down 282 * 0x2 – Most blocks powered down (only LOS 283 * active) 284 * 0x3 – complete power down (IDDQ mode) 285 * Can be asserted when Lane is in normal 286 * mode. These modes provide an increased 287 * power savings compared to reset mode. 288 * Signal is overridden by por_n_i so has no 289 * affect in power on reset state 290 */ 291 #define SERDES_C_GEN_RST_LN1_PD_MASK 0x00000C00 292 #define SERDES_C_GEN_RST_LN1_PD_SHIFT 10 293 294 #define SERDES_C_GEN_RST_CPU_MEM_RESET (1 << 12) 295 296 #define SERDES_C_GEN_RST_CPU_MEM_SHUTDOWN (1 << 13) 297 298 #define SERDES_C_GEN_RST_CAPRI_APB_RESET (1 << 14) 299 300 /**** status register ****/ 301 /* 302 * 0x0 – No error 303 * 0x1 – PHY has an internal error 304 */ 305 #define SERDES_C_GEN_STATUS_ERR_O (1 << 0) 306 /* 307 * 0x0 – PHY is not ready to respond to 308 * cm0_rst_n_i and cm0_pd_i[1:0]. The 309 * signals should not be changed. 310 * 0x1 - PHY is ready to respond to 311 * cm0_rst_n_i and cm0_pd_i[1:0] 312 */ 313 #define SERDES_C_GEN_STATUS_CM0_RST_PD_READY (1 << 1) 314 /* 315 * Indicates CMU PLL has locked to the 316 * reference clock and all output clocks are at 317 * the correct frequency 318 */ 319 #define SERDES_C_GEN_STATUS_CM0_OK_O (1 << 2) 320 /* 321 * 0x0 – PHY is not ready to respond to 322 * ln0_rst_n and ln0_pd[1:0]. The signals 323 * should not be changed. 324 * 0x1 - PHY is ready to respond to lnX_rst_n_i 325 * and lnX_pd_i[1:0] 326 */ 327 #define SERDES_C_GEN_STATUS_LN0_RST_PD_READY (1 << 3) 328 /* 329 * 0x0 – PHY is not ready to respond to 330 * ln1_rst_n_i and ln1_pd[1:0]. The signals 331 * should not be changed. 332 * 0x1 - PHY is ready to respond to lnX_rst_n_i 333 * and lnX_pd_i[1:0] 334 */ 335 #define SERDES_C_GEN_STATUS_LN1_RST_PD_READY (1 << 4) 336 /* 337 * Active low when the CPU performs a wait cycle (internally or externally 338 * generated) 339 */ 340 #define SERDES_C_GEN_STATUS_CPU_WAITSTATE (1 << 5) 341 342 #define SERDES_C_GEN_STATUS_TBUS_MASK 0x000FFF00 343 #define SERDES_C_GEN_STATUS_TBUS_SHIFT 8 344 345 /**** cfg register ****/ 346 /* 1- Swap 32 bit data on RX side */ 347 #define SERDES_C_LANE_CFG_RX_LANE_SWAP (1 << 0) 348 /* 1- Swap 32 bit data on TX side */ 349 #define SERDES_C_LANE_CFG_TX_LANE_SWAP (1 << 1) 350 /* 1 – invert rx data polarity */ 351 #define SERDES_C_LANE_CFG_LN_CTRL_RXPOLARITY (1 << 2) 352 /* 1 – invert tx data polarity */ 353 #define SERDES_C_LANE_CFG_TX_LANE_POLARITY (1 << 3) 354 /* 355 * 0x0 –Data on lnX_txdata_o will not be 356 * transmitted. Transmitter will be placed into 357 * electrical idle. 358 * 0x1 – Data on the active bits of 359 * lnX_txdata_o will be transmitted 360 */ 361 #define SERDES_C_LANE_CFG_LN_CTRL_TX_EN (1 << 4) 362 /* 363 * Informs the PHY to bypass the output of the 364 * analog LOS detector and instead rely upon 365 * a protocol LOS mechanism in the SoC/ASIC 366 * 0x0 – LOS operates as normal 367 * 0x1 – Bypass analog LOS output and 368 * instead rely upon protocol-level LOS 369 * detection via input lnX_ctrl_los_eii_value 370 */ 371 #define SERDES_C_LANE_CFG_LN_CTRL_LOS_EII_EN (1 << 5) 372 /* 373 * If lnX_ctrl_los_eii_en_i = 1 then Informs 374 * the PHY that the received signal was lost 375 */ 376 #define SERDES_C_LANE_CFG_LN_CTRL_LOS_EII_VALUE (1 << 6) 377 /* One hot mux */ 378 #define SERDES_C_LANE_CFG_TX_DATA_SRC_SELECT_MASK 0x00000F00 379 #define SERDES_C_LANE_CFG_TX_DATA_SRC_SELECT_SHIFT 8 380 /* 0x0 - 20-bit 0x1 – 40-bit */ 381 #define SERDES_C_LANE_CFG_LN_CTRL_DATA_WIDTH (1 << 12) 382 383 /**** stat register ****/ 384 /* 385 * x0 – lane is not ready to send and receive data 386 * 0x1 – lane is ready to send and receive data 387 */ 388 #define SERDES_C_LANE_STAT_LNX_STAT_OK (1 << 0) 389 /* 390 * 0x0 – received data run length has not 391 * exceed the programmable run length 392 * detector threshold 393 * 0x1 – received data run length has 394 * exceeded the programmable run length 395 * detector threshold 396 */ 397 #define SERDES_C_LANE_STAT_LN_STAT_RUNLEN_ERR (1 << 1) 398 /* 399 * 0x0 – data on lnX_rxdata_o are invalid 400 * 0x1 – data on the active bits of 401 * lnX_rxdata_o are valid 402 */ 403 #define SERDES_C_LANE_STAT_LN_STAT_RXVALID (1 << 2) 404 /* 405 * Loss of Signal (LOS) indicator that includes 406 * the combined functions of the digitally 407 * assisted analog LOS, digital LOS, and 408 * protocol LOS override features 409 * 0x0 – Signal detected on lnX_rxp_i / 410 * lnX_rxm_i pins 411 * 0x1 – No signal detected on lnX_rxp_i / 412 * lnX_rxm_i pins 413 */ 414 #define SERDES_C_LANE_STAT_LN_STAT_LOS (1 << 3) 415 416 #define SERDES_C_LANE_STAT_LN_STAT_LOS_DEGLITCH (1 << 4) 417 418 /**** reserved register ****/ 419 420 #define SERDES_C_LANE_RESERVED_DEF_0_MASK 0x0000FFFF 421 #define SERDES_C_LANE_RESERVED_DEF_0_SHIFT 0 422 423 #define SERDES_C_LANE_RESERVED_DEF_1_MASK 0xFFFF0000 424 #define SERDES_C_LANE_RESERVED_DEF_1_SHIFT 16 425 426 #ifdef __cplusplus 427 } 428 #endif 429 430 #endif /* __AL_HAL_serdes_c_REGS_H__ */ 431 432 /** @} end of ... group */ 433 434 435