xref: /freebsd/sys/contrib/alpine-hal/al_hal_pcie_regs.h (revision bd18fd57db1df29da1a3adf94d47924a977a29c2)
1 /*-
2 ********************************************************************************
3 Copyright (C) 2015 Annapurna Labs Ltd.
4 
5 This file may be licensed under the terms of the Annapurna Labs Commercial
6 License Agreement.
7 
8 Alternatively, this file can be distributed under the terms of the GNU General
9 Public License V2 as published by the Free Software Foundation and can be
10 found at http://www.gnu.org/licenses/gpl-2.0.html
11 
12 Alternatively, redistribution and use in source and binary forms, with or
13 without modification, are permitted provided that the following conditions are
14 met:
15 
16     *     Redistributions of source code must retain the above copyright notice,
17 this list of conditions and the following disclaimer.
18 
19     *     Redistributions in binary form must reproduce the above copyright
20 notice, this list of conditions and the following disclaimer in
21 the documentation and/or other materials provided with the
22 distribution.
23 
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 
35 *******************************************************************************/
36 
37 #ifndef __AL_HAL_PCIE_REGS_H__
38 #define __AL_HAL_PCIE_REGS_H__
39 
40 /* Note: Definitions before the includes so axi/wrapper regs sees them */
41 
42 /** Maximum physical functions supported */
43 #define REV1_2_MAX_NUM_OF_PFS	1
44 #define REV3_MAX_NUM_OF_PFS	4
45 #define AL_MAX_NUM_OF_PFS	4 /* the maximum between all Revisions */
46 
47 #include "al_hal_pcie_axi_reg.h"
48 #ifndef AL_PCIE_EX
49 #include "al_hal_pcie_w_reg.h"
50 #else
51 #include "al_hal_pcie_w_reg_ex.h"
52 #endif
53 
54 /**
55  * Revision IDs:
56  * ID_0: SlickRock M0
57  * ID_1: SlickRock A0
58  * ID_2: PeakRock  x4
59  * ID_3: PeakRock  x8
60  */
61 #define AL_PCIE_REV_ID_0			0
62 #define AL_PCIE_REV_ID_1			1
63 #define AL_PCIE_REV_ID_2			2
64 #define AL_PCIE_REV_ID_3			3
65 
66 #define AL_PCIE_AXI_REGS_OFFSET			0x0
67 #define AL_PCIE_REV_1_2_APP_REGS_OFFSET		0x1000
68 #define AL_PCIE_REV_3_APP_REGS_OFFSET		0x2000
69 #define AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET	0x2000
70 #define AL_PCIE_REV_3_CORE_CONF_BASE_OFFSET	0x10000
71 
72 /** Maximum number of lanes supported */
73 #define REV1_2_MAX_NUM_LANES	4
74 #define REV3_MAX_NUM_LANES	8
75 #define AL_MAX_NUM_OF_LANES	8 /* the maximum between all Revisions */
76 
77 struct al_pcie_core_iatu_regs {
78 	uint32_t index;
79 	uint32_t cr1;
80 	uint32_t cr2;
81 	uint32_t lower_base_addr;
82 	uint32_t upper_base_addr;
83 	uint32_t limit_addr;
84 	uint32_t lower_target_addr;
85 	uint32_t upper_target_addr;
86 	uint32_t cr3;
87 	uint32_t rsrvd[(0x270 - 0x224) >> 2];
88 };
89 
90 struct al_pcie_core_port_regs {
91 	uint32_t ack_lat_rply_timer;
92 	uint32_t reserved1[(0x10 - 0x4) >> 2];
93 	uint32_t port_link_ctrl;
94 	uint32_t reserved2[(0x18 - 0x14) >> 2];
95 	uint32_t timer_ctrl_max_func_num;
96 	uint32_t filter_mask_reg_1;
97 	uint32_t reserved3[(0x48 - 0x20) >> 2];
98 	uint32_t vc0_posted_rcv_q_ctrl;
99 	uint32_t vc0_non_posted_rcv_q_ctrl;
100 	uint32_t vc0_comp_rcv_q_ctrl;
101 	uint32_t reserved4[(0x10C - 0x54) >> 2];
102 	uint32_t gen2_ctrl;
103 	uint32_t reserved5[(0x190 - 0x110) >> 2];
104 	uint32_t gen3_ctrl;
105 	uint32_t gen3_eq_fs_lf;
106 	uint32_t gen3_eq_preset_to_coef_map;
107 	uint32_t gen3_eq_preset_idx;
108 	uint32_t reserved6;
109 	uint32_t gen3_eq_status;
110 	uint32_t gen3_eq_ctrl;
111 	uint32_t reserved7[(0x1B8 - 0x1AC) >> 2];
112 	uint32_t pipe_loopback_ctrl;
113 	uint32_t rd_only_wr_en;
114 	uint32_t reserved8[(0x1D0 - 0x1C0) >> 2];
115 	uint32_t axi_slave_err_resp;
116 	uint32_t reserved9[(0x200 - 0x1D4) >> 2];
117 	struct al_pcie_core_iatu_regs iatu;
118 	uint32_t reserved10[(0x448 - 0x270) >> 2];
119 };
120 
121 struct al_pcie_core_aer_regs {
122 	/* 0x0 - PCI Express Extended Capability Header */
123 	uint32_t header;
124 	/* 0x4 - Uncorrectable Error Status Register */
125 	uint32_t uncorr_err_stat;
126 	/* 0x8 - Uncorrectable Error Mask Register */
127 	uint32_t uncorr_err_mask;
128 	/* 0xc - Uncorrectable Error Severity Register */
129 	uint32_t uncorr_err_severity;
130 	/* 0x10 - Correctable Error Status Register */
131 	uint32_t corr_err_stat;
132 	/* 0x14 - Correctable Error Mask Register */
133 	uint32_t corr_err_mask;
134 	/* 0x18 - Advanced Error Capabilities and Control Register */
135 	uint32_t cap_and_ctrl;
136 	/* 0x1c - Header Log Registers */
137 	uint32_t header_log[4];
138 	/* 0x2c - Root Error Command Register */
139 	uint32_t root_err_cmd;
140 	/* 0x30 - Root Error Status Register */
141 	uint32_t root_err_stat;
142 	/* 0x34 - Error Source Identification Register */
143 	uint32_t err_src_id;
144 };
145 
146 struct al_pcie_core_reg_space_rev_1_2 {
147 	uint32_t			config_header[0x40 >> 2];
148 	uint32_t			pcie_pm_cap_base;
149 	uint32_t			reserved1[(0x70 - 0x44) >> 2];
150 	uint32_t			pcie_cap_base;
151 	uint32_t			pcie_dev_cap_base;
152 	uint32_t			pcie_dev_ctrl_status;
153 	uint32_t			pcie_link_cap_base;
154 	uint32_t			reserved2[(0xB0 - 0x80) >> 2];
155 	uint32_t			msix_cap_base;
156 	uint32_t			reserved3[(0x100 - 0xB4) >> 2];
157 	struct al_pcie_core_aer_regs	aer;
158 	uint32_t			reserved4[(0x150 -
159 						   (0x100 +
160 						    sizeof(struct al_pcie_core_aer_regs))) >> 2];
161 	uint32_t			pcie_sec_ext_cap_base;
162 	uint32_t			reserved5[(0x700 - 0x154) >> 2];
163 	struct al_pcie_core_port_regs	port_regs;
164 	uint32_t			reserved6[(0x1000 -
165 						   (0x700 +
166 						    sizeof(struct al_pcie_core_port_regs))) >> 2];
167 };
168 
169 struct al_pcie_core_reg_space_rev_3 {
170 	uint32_t			config_header[0x40 >> 2];
171 	uint32_t			pcie_pm_cap_base;
172 	uint32_t			reserved1[(0x70 - 0x44) >> 2];
173 	uint32_t			pcie_cap_base;
174 	uint32_t			pcie_dev_cap_base;
175 	uint32_t			pcie_dev_ctrl_status;
176 	uint32_t			pcie_link_cap_base;
177 	uint32_t			reserved2[(0xB0 - 0x80) >> 2];
178 	uint32_t			msix_cap_base;
179 	uint32_t			reserved3[(0x100 - 0xB4) >> 2];
180 	struct al_pcie_core_aer_regs	aer;
181 	uint32_t			reserved4[(0x158 -
182 						   (0x100 +
183 						    sizeof(struct al_pcie_core_aer_regs))) >> 2];
184 	/* pcie_sec_cap is only applicable for function 0 */
185 	uint32_t			pcie_sec_ext_cap_base;
186 	uint32_t			reserved5[(0x178 - 0x15C) >> 2];
187 	/* tph capability is only applicable for rev3 */
188 	uint32_t			tph_cap_base;
189 	uint32_t			reserved6[(0x700 - 0x17C) >> 2];
190 	/* port_regs is only applicable for function 0 */
191 	struct al_pcie_core_port_regs	port_regs;
192 	uint32_t			reserved7[(0x1000 -
193 						   (0x700 +
194 						    sizeof(struct al_pcie_core_port_regs))) >> 2];
195 };
196 
197 struct al_pcie_rev3_core_reg_space {
198 	struct al_pcie_core_reg_space_rev_3 func[REV3_MAX_NUM_OF_PFS];
199 };
200 
201 struct al_pcie_core_reg_space {
202 	uint32_t			*config_header;
203 	uint32_t			*pcie_pm_cap_base;
204 	uint32_t			*pcie_cap_base;
205 	uint32_t			*pcie_dev_cap_base;
206 	uint32_t			*pcie_dev_ctrl_status;
207 	uint32_t			*pcie_link_cap_base;
208 	uint32_t			*msix_cap_base;
209 	struct al_pcie_core_aer_regs	*aer;
210 	uint32_t			*pcie_sec_ext_cap_base;
211 	uint32_t			*tph_cap_base;
212 };
213 
214 struct al_pcie_revx_regs {
215 	struct al_pcie_revx_axi_regs __iomem	axi;
216 };
217 
218 struct al_pcie_rev1_regs {
219 	struct al_pcie_rev1_axi_regs __iomem	axi;
220 	uint32_t reserved1[(AL_PCIE_REV_1_2_APP_REGS_OFFSET -
221 				(AL_PCIE_AXI_REGS_OFFSET +
222 				sizeof(struct al_pcie_rev1_axi_regs))) >> 2];
223 	struct al_pcie_rev1_w_regs __iomem	app;
224 	uint32_t reserved2[(AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET -
225 				(AL_PCIE_REV_1_2_APP_REGS_OFFSET +
226 				sizeof(struct al_pcie_rev1_w_regs))) >> 2];
227 	struct al_pcie_core_reg_space_rev_1_2	core_space;
228 };
229 
230 struct al_pcie_rev2_regs {
231 	struct al_pcie_rev2_axi_regs __iomem	axi;
232 	uint32_t reserved1[(AL_PCIE_REV_1_2_APP_REGS_OFFSET -
233 				(AL_PCIE_AXI_REGS_OFFSET +
234 				sizeof(struct al_pcie_rev2_axi_regs))) >> 2];
235 	struct al_pcie_rev2_w_regs __iomem	app;
236 	uint32_t reserved2[(AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET -
237 				(AL_PCIE_REV_1_2_APP_REGS_OFFSET +
238 				sizeof(struct al_pcie_rev2_w_regs))) >> 2];
239 	struct al_pcie_core_reg_space_rev_1_2	core_space;
240 };
241 
242 struct al_pcie_rev3_regs {
243 	struct al_pcie_rev3_axi_regs __iomem	axi;
244 	uint32_t reserved1[(AL_PCIE_REV_3_APP_REGS_OFFSET -
245 				(AL_PCIE_AXI_REGS_OFFSET +
246 				sizeof(struct al_pcie_rev3_axi_regs))) >> 2];
247 	struct al_pcie_rev3_w_regs __iomem	app;
248 	uint32_t reserved2[(AL_PCIE_REV_3_CORE_CONF_BASE_OFFSET -
249 				(AL_PCIE_REV_3_APP_REGS_OFFSET +
250 				sizeof(struct al_pcie_rev3_w_regs))) >> 2];
251 	struct al_pcie_rev3_core_reg_space	core_space;
252 };
253 
254 struct al_pcie_axi_ctrl {
255 	uint32_t *global;
256 	uint32_t *master_arctl;
257 	uint32_t *master_awctl;
258 	uint32_t *slv_ctl;
259 };
260 
261 struct al_pcie_axi_ob_ctrl {
262 	uint32_t *cfg_target_bus;
263 	uint32_t *cfg_control;
264 	uint32_t *io_start_l;
265 	uint32_t *io_start_h;
266 	uint32_t *io_limit_l;
267 	uint32_t *io_limit_h;
268 };
269 
270 struct al_pcie_axi_pcie_global {
271 	uint32_t *conf;
272 };
273 
274 struct al_pcie_axi_conf {
275 	uint32_t *zero_lane0;
276 	uint32_t *zero_lane1;
277 	uint32_t *zero_lane2;
278 	uint32_t *zero_lane3;
279 	uint32_t *zero_lane4;
280 	uint32_t *zero_lane5;
281 	uint32_t *zero_lane6;
282 	uint32_t *zero_lane7;
283 };
284 
285 struct al_pcie_axi_status {
286 	uint32_t *lane[AL_MAX_NUM_OF_LANES];
287 };
288 
289 struct al_pcie_axi_parity {
290 	uint32_t *en_axi;
291 };
292 
293 struct al_pcie_axi_ordering {
294 	uint32_t *pos_cntl;
295 };
296 
297 struct al_pcie_axi_pre_configuration {
298 	uint32_t *pcie_core_setup;
299 };
300 
301 struct al_pcie_axi_init_fc {
302 	uint32_t *cfg;
303 };
304 
305 struct al_pcie_axi_attr_ovrd {
306 	uint32_t *write_msg_ctrl_0;
307 	uint32_t *write_msg_ctrl_1;
308 	uint32_t *pf_sel;
309 };
310 
311 struct al_pcie_axi_pf_axi_attr_ovrd {
312 	uint32_t *func_ctrl_0;
313 	uint32_t *func_ctrl_1;
314 	uint32_t *func_ctrl_2;
315 	uint32_t *func_ctrl_3;
316 	uint32_t *func_ctrl_4;
317 	uint32_t *func_ctrl_5;
318 	uint32_t *func_ctrl_6;
319 	uint32_t *func_ctrl_7;
320 	uint32_t *func_ctrl_8;
321 	uint32_t *func_ctrl_9;
322 };
323 
324 struct al_pcie_axi_msg_attr_axuser_table {
325 	uint32_t *entry_vec;
326 };
327 
328 struct al_pcie_axi_regs {
329 	struct al_pcie_axi_ctrl ctrl;
330 	struct al_pcie_axi_ob_ctrl ob_ctrl;
331 	struct al_pcie_axi_pcie_global pcie_global;
332 	struct al_pcie_axi_conf conf;
333 	struct al_pcie_axi_status status;
334 	struct al_pcie_axi_parity parity;
335 	struct al_pcie_axi_ordering ordering;
336 	struct al_pcie_axi_pre_configuration pre_configuration;
337 	struct al_pcie_axi_init_fc init_fc;
338 	struct al_pcie_revx_axi_int_grp_a_axi *int_grp_a;
339 	/* Rev3 only */
340 	struct al_pcie_axi_attr_ovrd axi_attr_ovrd;
341 	struct al_pcie_axi_pf_axi_attr_ovrd pf_axi_attr_ovrd[REV3_MAX_NUM_OF_PFS];
342 	struct al_pcie_axi_msg_attr_axuser_table msg_attr_axuser_table;
343 };
344 
345 struct al_pcie_w_global_ctrl {
346 	uint32_t *port_init;
347 	uint32_t *pm_control;
348 	uint32_t *events_gen[REV3_MAX_NUM_OF_PFS];
349 	uint32_t *corr_err_sts_int;
350 	uint32_t *uncorr_err_sts_int;
351 	uint32_t *sris_kp_counter;
352 };
353 
354 struct al_pcie_w_soc_int {
355 	uint32_t *mask_inta_leg_0;
356 	uint32_t *mask_inta_leg_3; /* Rev 2/3 only */
357 	uint32_t *mask_msi_leg_0;
358 	uint32_t *mask_msi_leg_3; /* Rev 2/3 only */
359 };
360 struct al_pcie_w_atu {
361 	uint32_t *in_mask_pair;
362 	uint32_t *out_mask_pair;
363 };
364 
365 struct al_pcie_w_regs {
366 	struct al_pcie_w_global_ctrl		global_ctrl;
367 	struct al_pcie_revx_w_debug		*debug;
368 	struct al_pcie_revx_w_ap_user_send_msg	*ap_user_send_msg;
369 	struct al_pcie_w_soc_int		soc_int[REV3_MAX_NUM_OF_PFS];
370 	struct al_pcie_revx_w_cntl_gen		*ctrl_gen;
371 	struct al_pcie_revx_w_parity		*parity;
372 	struct al_pcie_w_atu			atu;
373 	struct al_pcie_revx_w_status_per_func	*status_per_func[REV3_MAX_NUM_OF_PFS];
374 	struct al_pcie_revx_w_int_grp		*int_grp_a;
375 	struct al_pcie_revx_w_int_grp		*int_grp_b;
376 	struct al_pcie_revx_w_int_grp		*int_grp_c;
377 	struct al_pcie_revx_w_int_grp		*int_grp_d;
378 };
379 
380 struct al_pcie_regs {
381 	struct al_pcie_axi_regs		axi;
382 	struct al_pcie_w_regs		app;
383 	struct al_pcie_core_port_regs	*port_regs;
384 	struct al_pcie_core_reg_space	core_space[REV3_MAX_NUM_OF_PFS];
385 };
386 
387 #define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_EP	0
388 #define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_RC	4
389 
390 #define PCIE_PORT_GEN2_CTRL_DIRECT_SPEED_CHANGE		AL_BIT(17)
391 #define PCIE_PORT_GEN2_CTRL_TX_SWING_LOW_SHIFT		18
392 #define PCIE_PORT_GEN2_CTRL_TX_COMPLIANCE_RCV_SHIFT	19
393 #define PCIE_PORT_GEN2_CTRL_DEEMPHASIS_SET_SHIFT	20
394 #define PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_MASK		AL_FIELD_MASK(12, 8)
395 #define PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_SHIFT		8
396 
397 #define PCIE_PORT_GEN3_CTRL_EQ_PHASE_2_3_DISABLE_SHIFT	9
398 #define PCIE_PORT_GEN3_CTRL_EQ_DISABLE_SHIFT		16
399 
400 #define PCIE_PORT_GEN3_EQ_LF_SHIFT			0
401 #define PCIE_PORT_GEN3_EQ_LF_MASK			0x3f
402 #define PCIE_PORT_GEN3_EQ_FS_SHIFT			6
403 #define PCIE_PORT_GEN3_EQ_FS_MASK			(0x3f << PCIE_PORT_GEN3_EQ_FS_SHIFT)
404 
405 #define PCIE_PORT_LINK_CTRL_LB_EN_SHIFT			2
406 #define PCIE_PORT_LINK_CTRL_FAST_LINK_EN_SHIFT		7
407 #define PCIE_PORT_LINK_CTRL_LINK_CAPABLE_MASK		AL_FIELD_MASK(21, 16)
408 #define PCIE_PORT_LINK_CTRL_LINK_CAPABLE_SHIFT		16
409 
410 #define PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT	31
411 
412 #define PCIE_PORT_AXI_SLAVE_ERR_RESP_ALL_MAPPING_SHIFT	0
413 
414 /** timer_ctrl_max_func_num register
415  * Max physical function number (for example: 0 for 1PF, 3 for 4PFs)
416  */
417 #define PCIE_PORT_GEN3_MAX_FUNC_NUM			AL_FIELD_MASK(7, 0)
418 
419 /* filter_mask_reg_1 register */
420 /**
421  * SKP Interval Value.
422  * The number of symbol times to wait between transmitting SKP ordered sets
423  */
424 #define PCIE_FLT_MASK_SKP_INT_VAL_MASK			AL_FIELD_MASK(10, 0)
425 
426 /*
427  * 0: Treat Function MisMatched TLPs as UR
428  * 1: Treat Function MisMatched TLPs as Supported
429  */
430 #define CX_FLT_MASK_UR_FUNC_MISMATCH			AL_BIT(16)
431 
432 /*
433  * 0: Treat CFG type1 TLPs as UR for EP; Supported for RC
434  * 1: Treat CFG type1 TLPs as Supported for EP; UR for RC
435  */
436 #define CX_FLT_MASK_CFG_TYPE1_RE_AS_UR			AL_BIT(19)
437 
438 /*
439  * 0: Enforce requester id match for received CPL TLPs.
440  *    A violation results in cpl_abort, and possibly AER of unexp_cpl_err,
441  *    cpl_rcvd_ur, cpl_rcvd_ca
442  * 1: Mask requester id match for received CPL TLPs
443  */
444 #define CX_FLT_MASK_CPL_REQID_MATCH			AL_BIT(22)
445 
446 /*
447  * 0: Enforce function match for received CPL TLPs.
448  *    A violation results in cpl_abort, and possibly AER of unexp_cpl_err,
449  *    cpl_rcvd_ur, cpl_rcvd_ca
450  * 1: Mask function match for received CPL TLPs
451  */
452 #define CX_FLT_MASK_CPL_FUNC_MATCH			AL_BIT(23)
453 
454 /* vc0_posted_rcv_q_ctrl register */
455 #define RADM_PQ_HCRD_VC0_MASK				AL_FIELD_MASK(19, 12)
456 #define RADM_PQ_HCRD_VC0_SHIFT				12
457 
458 /* vc0_non_posted_rcv_q_ctrl register */
459 #define RADM_NPQ_HCRD_VC0_MASK				AL_FIELD_MASK(19, 12)
460 #define RADM_NPQ_HCRD_VC0_SHIFT				12
461 
462 /* vc0_comp_rcv_q_ctrl register */
463 #define RADM_CPLQ_HCRD_VC0_MASK				AL_FIELD_MASK(19, 12)
464 #define RADM_CPLQ_HCRD_VC0_SHIFT			12
465 
466 /**** iATU, Control Register 1 ****/
467 
468 /**
469  * When the Address and BAR matching logic in the core indicate that a MEM-I/O
470  * transaction matches a BAR in the function corresponding to this value, then
471  * address translation proceeds. This check is only performed if the "Function
472  * Number Match Enable" bit of the "iATU Control 2 Register" is set
473  */
474 #define PCIE_IATU_CR1_FUNC_NUM_MASK			AL_FIELD_MASK(24, 20)
475 #define PCIE_IATU_CR1_FUNC_NUM_SHIFT			20
476 
477 /**** iATU, Control Register 2 ****/
478 /** For outbound regions, the Function Number Translation Bypass mode enables
479  *  taking the function number of the translated TLP from the PCIe core
480  *  interface and not from the "Function Number" field of CR1.
481  *  For inbound regions, this bit should be asserted when physical function
482  *  match mode needs to be enabled
483  */
484 #define PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_MASK	AL_BIT(19)
485 #define PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_SHIFT	19
486 
487 /* pcie_dev_ctrl_status register */
488 #define PCIE_PORT_DEV_CTRL_STATUS_CORR_ERR_REPORT_EN	AL_BIT(0)
489 #define PCIE_PORT_DEV_CTRL_STATUS_NON_FTL_ERR_REPORT_EN	AL_BIT(1)
490 #define PCIE_PORT_DEV_CTRL_STATUS_FTL_ERR_REPORT_EN	AL_BIT(2)
491 #define PCIE_PORT_DEV_CTRL_STATUS_UNSUP_REQ_REPORT_EN	AL_BIT(3)
492 
493 #define PCIE_PORT_DEV_CTRL_STATUS_MPS_MASK		AL_FIELD_MASK(7, 5)
494 #define PCIE_PORT_DEV_CTRL_STATUS_MPS_SHIFT		5
495 #define PCIE_PORT_DEV_CTRL_STATUS_MPS_VAL_256		(1 << PCIE_PORT_DEV_CTRL_STATUS_MPS_SHIFT)
496 
497 #define PCIE_PORT_DEV_CTRL_STATUS_MRRS_MASK		AL_FIELD_MASK(14, 12)
498 #define PCIE_PORT_DEV_CTRL_STATUS_MRRS_SHIFT		12
499 #define PCIE_PORT_DEV_CTRL_STATUS_MRRS_VAL_256		(1 << PCIE_PORT_DEV_CTRL_STATUS_MRRS_SHIFT)
500 
501 /******************************************************************************
502  * AER registers
503  ******************************************************************************/
504 /* PCI Express Extended Capability ID */
505 #define PCIE_AER_CAP_ID_MASK			AL_FIELD_MASK(15, 0)
506 #define PCIE_AER_CAP_ID_SHIFT			0
507 #define PCIE_AER_CAP_ID_VAL			1
508 /* Capability Version */
509 #define PCIE_AER_CAP_VER_MASK			AL_FIELD_MASK(19, 16)
510 #define PCIE_AER_CAP_VER_SHIFT			16
511 #define PCIE_AER_CAP_VER_VAL			2
512 
513 /* First Error Pointer */
514 #define PCIE_AER_CTRL_STAT_FIRST_ERR_PTR_MASK		AL_FIELD_MASK(4, 0)
515 #define PCIE_AER_CTRL_STAT_FIRST_ERR_PTR_SHIFT		0
516 /* ECRC Generation Capability */
517 #define PCIE_AER_CTRL_STAT_ECRC_GEN_SUPPORTED		AL_BIT(5)
518 /* ECRC Generation Enable */
519 #define PCIE_AER_CTRL_STAT_ECRC_GEN_EN			AL_BIT(6)
520 /* ECRC Check Capable */
521 #define PCIE_AER_CTRL_STAT_ECRC_CHK_SUPPORTED		AL_BIT(7)
522 /* ECRC Check Enable */
523 #define PCIE_AER_CTRL_STAT_ECRC_CHK_EN			AL_BIT(8)
524 
525 /* Correctable Error Reporting Enable */
526 #define PCIE_AER_ROOT_ERR_CMD_CORR_ERR_RPRT_EN		AL_BIT(0)
527 /* Non-Fatal Error Reporting Enable */
528 #define PCIE_AER_ROOT_ERR_CMD_NON_FTL_ERR_RPRT_EN	AL_BIT(1)
529 /* Fatal Error Reporting Enable */
530 #define PCIE_AER_ROOT_ERR_CMD_FTL_ERR_RPRT_EN		AL_BIT(2)
531 
532 /* ERR_COR Received */
533 #define PCIE_AER_ROOT_ERR_STAT_CORR_ERR			AL_BIT(0)
534 /* Multiple ERR_COR Received */
535 #define PCIE_AER_ROOT_ERR_STAT_CORR_ERR_MULTI		AL_BIT(1)
536 /* ERR_FATAL/NONFATAL Received */
537 #define PCIE_AER_ROOT_ERR_STAT_FTL_NON_FTL_ERR		AL_BIT(2)
538 /* Multiple ERR_FATAL/NONFATAL Received */
539 #define PCIE_AER_ROOT_ERR_STAT_FTL_NON_FTL_ERR_MULTI	AL_BIT(3)
540 /* First Uncorrectable Fatal */
541 #define PCIE_AER_ROOT_ERR_STAT_FIRST_UNCORR_FTL		AL_BIT(4)
542 /* Non-Fatal Error Messages Received */
543 #define PCIE_AER_ROOT_ERR_STAT_NON_FTL_RCVD		AL_BIT(5)
544 /* Fatal Error Messages Received */
545 #define PCIE_AER_ROOT_ERR_STAT_FTL_RCVD			AL_BIT(6)
546 /* Advanced Error Interrupt Message Number */
547 #define PCIE_AER_ROOT_ERR_STAT_ERR_INT_MSG_NUM_MASK	AL_FIELD_MASK(31, 27)
548 #define PCIE_AER_ROOT_ERR_STAT_ERR_INT_MSG_NUM_SHIFT	27
549 
550 /* ERR_COR Source Identification */
551 #define PCIE_AER_SRC_ID_CORR_ERR_MASK			AL_FIELD_MASK(15, 0)
552 #define PCIE_AER_SRC_ID_CORR_ERR_SHIFT			0
553 /* ERR_FATAL/NONFATAL Source Identification */
554 #define PCIE_AER_SRC_ID_CORR_ERR_FTL_NON_FTL_MASK	AL_FIELD_MASK(31, 16)
555 #define PCIE_AER_SRC_ID_CORR_ERR_FTL_NON_FTL_SHIFT	16
556 
557 /* AER message */
558 #define PCIE_AER_MSG_REQID_MASK				AL_FIELD_MASK(31, 16)
559 #define PCIE_AER_MSG_REQID_SHIFT			16
560 #define PCIE_AER_MSG_TYPE_MASK				AL_FIELD_MASK(15, 8)
561 #define PCIE_AER_MSG_TYPE_SHIFT				8
562 #define PCIE_AER_MSG_RESERVED				AL_FIELD_MASK(7, 1)
563 #define PCIE_AER_MSG_VALID				AL_BIT(0)
564 /* AER message ack */
565 #define PCIE_AER_MSG_ACK				AL_BIT(0)
566 /* AER errors definitions */
567 #define AL_PCIE_AER_TYPE_CORR				(0x30)
568 #define AL_PCIE_AER_TYPE_NON_FATAL			(0x31)
569 #define AL_PCIE_AER_TYPE_FATAL				(0x33)
570 /* Requester ID Bus */
571 #define AL_PCIE_REQID_BUS_NUM_SHIFT			(8)
572 
573 /******************************************************************************
574  * TPH registers
575  ******************************************************************************/
576 #define PCIE_TPH_NEXT_POINTER				AL_FIELD_MASK(31, 20)
577 
578 /******************************************************************************
579  * Config Header registers
580  ******************************************************************************/
581 /**
582  * see BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG in core spec
583  * Note: valid only for EP mode
584  */
585 #define PCIE_BIST_HEADER_TYPE_BASE		0xc
586 #define PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK	AL_BIT(23)
587 
588 /******************************************************************************
589  * SRIS KP counters default values
590  ******************************************************************************/
591 #define PCIE_SRIS_KP_COUNTER_GEN3_DEFAULT_VAL	(0x24)
592 #define PCIE_SRIS_KP_COUNTER_GEN21_DEFAULT_VAL	(0x4B)
593 
594 #endif
595