1 /*- 2 ******************************************************************************** 3 Copyright (C) 2015 Annapurna Labs Ltd. 4 5 This file may be licensed under the terms of the Annapurna Labs Commercial 6 License Agreement. 7 8 Alternatively, this file can be distributed under the terms of the GNU General 9 Public License V2 as published by the Free Software Foundation and can be 10 found at http://www.gnu.org/licenses/gpl-2.0.html 11 12 Alternatively, redistribution and use in source and binary forms, with or 13 without modification, are permitted provided that the following conditions are 14 met: 15 16 * Redistributions of source code must retain the above copyright notice, 17 this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20 notice, this list of conditions and the following disclaimer in 21 the documentation and/or other materials provided with the 22 distribution. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35 *******************************************************************************/ 36 37 /** 38 * @{ 39 * @file al_hal_pbs_regs.h 40 * 41 * @brief ... registers 42 * 43 */ 44 45 #ifndef __AL_HAL_PBS_REGS_H__ 46 #define __AL_HAL_PBS_REGS_H__ 47 48 #include "al_hal_plat_types.h" 49 50 #ifdef __cplusplus 51 extern "C" { 52 #endif 53 /* 54 * Unit Registers 55 */ 56 57 58 59 struct al_pbs_unit { 60 /* [0x0] Conf_bus, Configuration of the SB */ 61 uint32_t conf_bus; 62 /* [0x4] PASW high */ 63 uint32_t dram_0_nb_bar_high; 64 /* [0x8] PASW low */ 65 uint32_t dram_0_nb_bar_low; 66 /* [0xc] PASW high */ 67 uint32_t dram_1_nb_bar_high; 68 /* [0x10] PASW low */ 69 uint32_t dram_1_nb_bar_low; 70 /* [0x14] PASW high */ 71 uint32_t dram_2_nb_bar_high; 72 /* [0x18] PASW low */ 73 uint32_t dram_2_nb_bar_low; 74 /* [0x1c] PASW high */ 75 uint32_t dram_3_nb_bar_high; 76 /* [0x20] PASW low */ 77 uint32_t dram_3_nb_bar_low; 78 /* [0x24] PASW high */ 79 uint32_t msix_nb_bar_high; 80 /* [0x28] PASW low */ 81 uint32_t msix_nb_bar_low; 82 /* [0x2c] PASW high */ 83 uint32_t dram_0_sb_bar_high; 84 /* [0x30] PASW low */ 85 uint32_t dram_0_sb_bar_low; 86 /* [0x34] PASW high */ 87 uint32_t dram_1_sb_bar_high; 88 /* [0x38] PASW low */ 89 uint32_t dram_1_sb_bar_low; 90 /* [0x3c] PASW high */ 91 uint32_t dram_2_sb_bar_high; 92 /* [0x40] PASW low */ 93 uint32_t dram_2_sb_bar_low; 94 /* [0x44] PASW high */ 95 uint32_t dram_3_sb_bar_high; 96 /* [0x48] PASW low */ 97 uint32_t dram_3_sb_bar_low; 98 /* [0x4c] PASW high */ 99 uint32_t msix_sb_bar_high; 100 /* [0x50] PASW low */ 101 uint32_t msix_sb_bar_low; 102 /* [0x54] PASW high */ 103 uint32_t pcie_mem0_bar_high; 104 /* [0x58] PASW low */ 105 uint32_t pcie_mem0_bar_low; 106 /* [0x5c] PASW high */ 107 uint32_t pcie_mem1_bar_high; 108 /* [0x60] PASW low */ 109 uint32_t pcie_mem1_bar_low; 110 /* [0x64] PASW high */ 111 uint32_t pcie_mem2_bar_high; 112 /* [0x68] PASW low */ 113 uint32_t pcie_mem2_bar_low; 114 /* [0x6c] PASW high */ 115 uint32_t pcie_ext_ecam0_bar_high; 116 /* [0x70] PASW low */ 117 uint32_t pcie_ext_ecam0_bar_low; 118 /* [0x74] PASW high */ 119 uint32_t pcie_ext_ecam1_bar_high; 120 /* [0x78] PASW low */ 121 uint32_t pcie_ext_ecam1_bar_low; 122 /* [0x7c] PASW high */ 123 uint32_t pcie_ext_ecam2_bar_high; 124 /* [0x80] PASW low */ 125 uint32_t pcie_ext_ecam2_bar_low; 126 /* [0x84] PASW high */ 127 uint32_t pbs_nor_bar_high; 128 /* [0x88] PASW low */ 129 uint32_t pbs_nor_bar_low; 130 /* [0x8c] PASW high */ 131 uint32_t pbs_spi_bar_high; 132 /* [0x90] PASW low */ 133 uint32_t pbs_spi_bar_low; 134 uint32_t rsrvd_0[3]; 135 /* [0xa0] PASW high */ 136 uint32_t pbs_nand_bar_high; 137 /* [0xa4] PASW low */ 138 uint32_t pbs_nand_bar_low; 139 /* [0xa8] PASW high */ 140 uint32_t pbs_int_mem_bar_high; 141 /* [0xac] PASW low */ 142 uint32_t pbs_int_mem_bar_low; 143 /* [0xb0] PASW high */ 144 uint32_t pbs_boot_bar_high; 145 /* [0xb4] PASW low */ 146 uint32_t pbs_boot_bar_low; 147 /* [0xb8] PASW high */ 148 uint32_t nb_int_bar_high; 149 /* [0xbc] PASW low */ 150 uint32_t nb_int_bar_low; 151 /* [0xc0] PASW high */ 152 uint32_t nb_stm_bar_high; 153 /* [0xc4] PASW low */ 154 uint32_t nb_stm_bar_low; 155 /* [0xc8] PASW high */ 156 uint32_t pcie_ecam_int_bar_high; 157 /* [0xcc] PASW low */ 158 uint32_t pcie_ecam_int_bar_low; 159 /* [0xd0] PASW high */ 160 uint32_t pcie_mem_int_bar_high; 161 /* [0xd4] PASW low */ 162 uint32_t pcie_mem_int_bar_low; 163 /* [0xd8] Control */ 164 uint32_t winit_cntl; 165 /* [0xdc] Control */ 166 uint32_t latch_bars; 167 /* [0xe0] Control */ 168 uint32_t pcie_conf_0; 169 /* [0xe4] Control */ 170 uint32_t pcie_conf_1; 171 /* [0xe8] Control */ 172 uint32_t serdes_mux_pipe; 173 /* [0xec] Control */ 174 uint32_t dma_io_master_map; 175 /* [0xf0] Status */ 176 uint32_t i2c_pld_status_high; 177 /* [0xf4] Status */ 178 uint32_t i2c_pld_status_low; 179 /* [0xf8] Status */ 180 uint32_t spi_dbg_status_high; 181 /* [0xfc] Status */ 182 uint32_t spi_dbg_status_low; 183 /* [0x100] Status */ 184 uint32_t spi_mst_status_high; 185 /* [0x104] Status */ 186 uint32_t spi_mst_status_low; 187 /* [0x108] Log */ 188 uint32_t mem_pbs_parity_err_high; 189 /* [0x10c] Log */ 190 uint32_t mem_pbs_parity_err_low; 191 /* [0x110] Log */ 192 uint32_t boot_strap; 193 /* [0x114] Conf */ 194 uint32_t cfg_axi_conf_0; 195 /* [0x118] Conf */ 196 uint32_t cfg_axi_conf_1; 197 /* [0x11c] Conf */ 198 uint32_t cfg_axi_conf_2; 199 /* [0x120] Conf */ 200 uint32_t cfg_axi_conf_3; 201 /* [0x124] Conf */ 202 uint32_t spi_mst_conf_0; 203 /* [0x128] Conf */ 204 uint32_t spi_mst_conf_1; 205 /* [0x12c] Conf */ 206 uint32_t spi_slv_conf_0; 207 /* [0x130] Conf */ 208 uint32_t apb_mem_conf_int; 209 /* [0x134] PASW remap register */ 210 uint32_t sb2nb_cfg_dram_remap; 211 /* [0x138] Control */ 212 uint32_t pbs_mux_sel_0; 213 /* [0x13c] Control */ 214 uint32_t pbs_mux_sel_1; 215 /* [0x140] Control */ 216 uint32_t pbs_mux_sel_2; 217 /* [0x144] Control */ 218 uint32_t pbs_mux_sel_3; 219 /* [0x148] PASW high */ 220 uint32_t sb_int_bar_high; 221 /* [0x14c] PASW low */ 222 uint32_t sb_int_bar_low; 223 /* [0x150] log */ 224 uint32_t ufc_pbs_parity_err_high; 225 /* [0x154] log */ 226 uint32_t ufc_pbs_parity_err_low; 227 /* [0x158] Cntl - internal */ 228 uint32_t gen_conf; 229 /* [0x15c] Device ID and Rev ID */ 230 uint32_t chip_id; 231 /* [0x160] Status - internal */ 232 uint32_t uart0_debug; 233 /* [0x164] Status - internal */ 234 uint32_t uart1_debug; 235 /* [0x168] Status - internal */ 236 uint32_t uart2_debug; 237 /* [0x16c] Status - internal */ 238 uint32_t uart3_debug; 239 /* [0x170] Control - internal */ 240 uint32_t uart0_conf_status; 241 /* [0x174] Control - internal */ 242 uint32_t uart1_conf_status; 243 /* [0x178] Control - internal */ 244 uint32_t uart2_conf_status; 245 /* [0x17c] Control - internal */ 246 uint32_t uart3_conf_status; 247 /* [0x180] Control - internal */ 248 uint32_t gpio0_conf_status; 249 /* [0x184] Control - internal */ 250 uint32_t gpio1_conf_status; 251 /* [0x188] Control - internal */ 252 uint32_t gpio2_conf_status; 253 /* [0x18c] Control - internal */ 254 uint32_t gpio3_conf_status; 255 /* [0x190] Control - internal */ 256 uint32_t gpio4_conf_status; 257 /* [0x194] Control - internal */ 258 uint32_t i2c_gen_conf_status; 259 /* [0x198] Control - internal */ 260 uint32_t i2c_gen_debug; 261 /* [0x19c] Cntl */ 262 uint32_t watch_dog_reset_out; 263 /* [0x1a0] Cntl */ 264 uint32_t otp_magic_num; 265 /* 266 * [0x1a4] Control - internal 267 */ 268 uint32_t otp_cntl; 269 /* [0x1a8] Cfg - internal */ 270 uint32_t otp_cfg_0; 271 /* [0x1ac] Cfg - internal */ 272 uint32_t otp_cfg_1; 273 /* [0x1b0] Cfg - internal */ 274 uint32_t otp_cfg_3; 275 /* [0x1b4] Cfg */ 276 uint32_t cfg_nand_0; 277 /* [0x1b8] Cfg */ 278 uint32_t cfg_nand_1; 279 /* [0x1bc] Cfg-- timing parameters internal. */ 280 uint32_t cfg_nand_2; 281 /* [0x1c0] Cfg - internal */ 282 uint32_t cfg_nand_3; 283 /* [0x1c4] PASW high */ 284 uint32_t nb_nic_regs_bar_high; 285 /* [0x1c8] PASW low */ 286 uint32_t nb_nic_regs_bar_low; 287 /* [0x1cc] PASW high */ 288 uint32_t sb_nic_regs_bar_high; 289 /* [0x1d0] PASW low */ 290 uint32_t sb_nic_regs_bar_low; 291 /* [0x1d4] Control */ 292 uint32_t serdes_mux_multi_0; 293 /* [0x1d8] Control */ 294 uint32_t serdes_mux_multi_1; 295 /* [0x1dc] Control - not in use any more - internal */ 296 uint32_t pbs_ulpi_mux_conf; 297 /* [0x1e0] Cntl */ 298 uint32_t wr_once_dbg_dis_ovrd_reg; 299 /* [0x1e4] Cntl - internal */ 300 uint32_t gpio5_conf_status; 301 /* [0x1e8] PASW high */ 302 uint32_t pcie_mem3_bar_high; 303 /* [0x1ec] PASW low */ 304 uint32_t pcie_mem3_bar_low; 305 /* [0x1f0] PASW high */ 306 uint32_t pcie_mem4_bar_high; 307 /* [0x1f4] PASW low */ 308 uint32_t pcie_mem4_bar_low; 309 /* [0x1f8] PASW high */ 310 uint32_t pcie_mem5_bar_high; 311 /* [0x1fc] PASW low */ 312 uint32_t pcie_mem5_bar_low; 313 /* [0x200] PASW high */ 314 uint32_t pcie_ext_ecam3_bar_high; 315 /* [0x204] PASW low */ 316 uint32_t pcie_ext_ecam3_bar_low; 317 /* [0x208] PASW high */ 318 uint32_t pcie_ext_ecam4_bar_high; 319 /* [0x20c] PASW low */ 320 uint32_t pcie_ext_ecam4_bar_low; 321 /* [0x210] PASW high */ 322 uint32_t pcie_ext_ecam5_bar_high; 323 /* [0x214] PASW low */ 324 uint32_t pcie_ext_ecam5_bar_low; 325 /* [0x218] PASW high */ 326 uint32_t low_latency_sram_bar_high; 327 /* [0x21c] PASW low */ 328 uint32_t low_latency_sram_bar_low; 329 /* [0x220] Control */ 330 uint32_t pbs_mux_sel_4; 331 /* [0x224] Control */ 332 uint32_t pbs_mux_sel_5; 333 /* [0x228] Control */ 334 uint32_t serdes_mux_eth; 335 /* [0x22c] Control */ 336 uint32_t serdes_mux_pcie; 337 /* [0x230] Control */ 338 uint32_t serdes_mux_sata; 339 uint32_t rsrvd[7]; 340 }; 341 struct al_pbs_low_latency_sram_remap { 342 /* [0x0] PBS MEM Remap */ 343 uint32_t bar1_orig; 344 /* [0x4] PBS MEM Remap */ 345 uint32_t bar1_remap; 346 /* [0x8] ETH0 MEM Remap */ 347 uint32_t bar2_orig; 348 /* [0xc] ETH0 MEM Remap */ 349 uint32_t bar2_remap; 350 /* [0x10] ETH1 MEM Remap */ 351 uint32_t bar3_orig; 352 /* [0x14] ETH1 MEM Remap */ 353 uint32_t bar3_remap; 354 /* [0x18] ETH2 MEM Remap */ 355 uint32_t bar4_orig; 356 /* [0x1c] ETH2 MEM Remap */ 357 uint32_t bar4_remap; 358 /* [0x20] ETH3 MEM Remap */ 359 uint32_t bar5_orig; 360 /* [0x24] ETH3 MEM Remap */ 361 uint32_t bar5_remap; 362 /* [0x28] CRYPTO0 MEM Remap */ 363 uint32_t bar6_orig; 364 /* [0x2c] CRYPTO0 MEM Remap */ 365 uint32_t bar6_remap; 366 /* [0x30] RAID0 MEM Remap */ 367 uint32_t bar7_orig; 368 /* [0x34] RAID0 MEM Remap */ 369 uint32_t bar7_remap; 370 /* [0x38] CRYPTO1 MEM Remap */ 371 uint32_t bar8_orig; 372 /* [0x3c] CRYPTO1 MEM Remap */ 373 uint32_t bar8_remap; 374 /* [0x40] RAID1 MEM Remap */ 375 uint32_t bar9_orig; 376 /* [0x44] RAID2 MEM Remap */ 377 uint32_t bar9_remap; 378 /* [0x48] RESERVED MEM Remap */ 379 uint32_t bar10_orig; 380 /* [0x4c] RESERVED MEM Remap */ 381 uint32_t bar10_remap; 382 }; 383 struct al_pbs_target_id_enforcement { 384 /* [0x0] target enforcement */ 385 uint32_t cpu; 386 /* [0x4] target enforcement mask (bits which are 0 are not compared) */ 387 uint32_t cpu_mask; 388 /* [0x8] target enforcement */ 389 uint32_t debug_nb; 390 /* [0xc] target enforcement mask (bits which are 0 are not compared) */ 391 uint32_t debug_nb_mask; 392 /* [0x10] target enforcement */ 393 uint32_t debug_sb; 394 /* [0x14] target enforcement mask (bits which are 0 are not compared) */ 395 uint32_t debug_sb_mask; 396 /* [0x18] target enforcement */ 397 uint32_t eth_0; 398 /* [0x1c] target enforcement mask (bits which are 0 are not compared) */ 399 uint32_t eth_0_mask; 400 /* [0x20] target enforcement */ 401 uint32_t eth_1; 402 /* [0x24] target enforcement mask (bits which are 0 are not compared) */ 403 uint32_t eth_1_mask; 404 /* [0x28] target enforcement */ 405 uint32_t eth_2; 406 /* [0x2c] target enforcement mask (bits which are 0 are not compared) */ 407 uint32_t eth_2_mask; 408 /* [0x30] target enforcement */ 409 uint32_t eth_3; 410 /* [0x34] target enforcement mask (bits which are 0 are not compared) */ 411 uint32_t eth_3_mask; 412 /* [0x38] target enforcement */ 413 uint32_t sata_0; 414 /* [0x3c] target enforcement mask (bits which are 0 are not compared) */ 415 uint32_t sata_0_mask; 416 /* [0x40] target enforcement */ 417 uint32_t sata_1; 418 /* [0x44] target enforcement mask (bits which are 0 are not compared) */ 419 uint32_t sata_1_mask; 420 /* [0x48] target enforcement */ 421 uint32_t crypto_0; 422 /* [0x4c] target enforcement mask (bits which are 0 are not compared) */ 423 uint32_t crypto_0_mask; 424 /* [0x50] target enforcement */ 425 uint32_t crypto_1; 426 /* [0x54] target enforcement mask (bits which are 0 are not compared) */ 427 uint32_t crypto_1_mask; 428 /* [0x58] target enforcement */ 429 uint32_t pcie_0; 430 /* [0x5c] target enforcement mask (bits which are 0 are not compared) */ 431 uint32_t pcie_0_mask; 432 /* [0x60] target enforcement */ 433 uint32_t pcie_1; 434 /* [0x64] target enforcement mask (bits which are 0 are not compared) */ 435 uint32_t pcie_1_mask; 436 /* [0x68] target enforcement */ 437 uint32_t pcie_2; 438 /* [0x6c] target enforcement mask (bits which are 0 are not compared) */ 439 uint32_t pcie_2_mask; 440 /* [0x70] target enforcement */ 441 uint32_t pcie_3; 442 /* [0x74] target enforcement mask (bits which are 0 are not compared) */ 443 uint32_t pcie_3_mask; 444 /* [0x78] Control */ 445 uint32_t latch; 446 uint32_t rsrvd[9]; 447 }; 448 449 struct al_pbs_regs { 450 struct al_pbs_unit unit; /* [0x0] */ 451 struct al_pbs_low_latency_sram_remap low_latency_sram_remap; /* [0x250] */ 452 uint32_t rsrvd_0[24]; 453 uint32_t iofic_base; /* [0x300] */ 454 uint32_t rsrvd_1[63]; 455 struct al_pbs_target_id_enforcement target_id_enforcement; /* [0x400] */ 456 }; 457 458 459 /* 460 * Registers Fields 461 */ 462 463 464 /**** conf_bus register ****/ 465 /* Read slave error enable */ 466 #define PBS_UNIT_CONF_BUS_RD_SLVERR_EN (1 << 0) 467 /* Write slave error enable */ 468 #define PBS_UNIT_CONF_BUS_WR_SLVERR_EN (1 << 1) 469 /* Read decode error enable */ 470 #define PBS_UNIT_CONF_BUS_RD_DECERR_EN (1 << 2) 471 /* Write decode error enable */ 472 #define PBS_UNIT_CONF_BUS_WR_DECERR_EN (1 << 3) 473 /* For debug clear the APB SM */ 474 #define PBS_UNIT_CONF_BUS_CLR_APB_FSM (1 << 4) 475 /* For debug clear the WFIFO */ 476 #define PBS_UNIT_CONF_BUS_CLR_WFIFO_CLEAR (1 << 5) 477 /* Arbiter between read and write channel */ 478 #define PBS_UNIT_CONF_BUS_WRR_CNT_MASK 0x000001C0 479 #define PBS_UNIT_CONF_BUS_WRR_CNT_SHIFT 6 480 481 482 /* general PASWS */ 483 /* window size = 2 ^ (15 + win_size), zero value disable the win ... */ 484 #define PBS_PASW_WIN_SIZE_MASK 0x0000003F 485 #define PBS_PASW_WIN_SIZE_SHIFT 0 486 /* reserved fields */ 487 #define PBS_PASW_BAR_LOW_RSRVD_MASK 0x0000FFC0 488 #define PBS_PASW_BAR_LOW_RSRVD_SHIFT 6 489 /* bar low address 16 MSB bits */ 490 #define PBS_PASW_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 491 #define PBS_PASW_BAR_LOW_ADDR_HIGH_SHIFT 16 492 493 /**** dram_0_nb_bar_low register ****/ 494 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 495 #define PBS_UNIT_DRAM_0_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 496 #define PBS_UNIT_DRAM_0_NB_BAR_LOW_WIN_SIZE_SHIFT 0 497 /* Reserved fields */ 498 #define PBS_UNIT_DRAM_0_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 499 #define PBS_UNIT_DRAM_0_NB_BAR_LOW_RSRVD_SHIFT 6 500 /* bar low address 16 MSB bits */ 501 #define PBS_UNIT_DRAM_0_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 502 #define PBS_UNIT_DRAM_0_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 503 504 /**** dram_1_nb_bar_low register ****/ 505 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 506 #define PBS_UNIT_DRAM_1_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 507 #define PBS_UNIT_DRAM_1_NB_BAR_LOW_WIN_SIZE_SHIFT 0 508 /* Reserved fields */ 509 #define PBS_UNIT_DRAM_1_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 510 #define PBS_UNIT_DRAM_1_NB_BAR_LOW_RSRVD_SHIFT 6 511 /* bar low address 16 MSB bits */ 512 #define PBS_UNIT_DRAM_1_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 513 #define PBS_UNIT_DRAM_1_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 514 515 /**** dram_2_nb_bar_low register ****/ 516 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 517 #define PBS_UNIT_DRAM_2_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 518 #define PBS_UNIT_DRAM_2_NB_BAR_LOW_WIN_SIZE_SHIFT 0 519 /* Reserved fields */ 520 #define PBS_UNIT_DRAM_2_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 521 #define PBS_UNIT_DRAM_2_NB_BAR_LOW_RSRVD_SHIFT 6 522 /* bar low address 16 MSB bits */ 523 #define PBS_UNIT_DRAM_2_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 524 #define PBS_UNIT_DRAM_2_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 525 526 /**** dram_3_nb_bar_low register ****/ 527 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 528 #define PBS_UNIT_DRAM_3_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 529 #define PBS_UNIT_DRAM_3_NB_BAR_LOW_WIN_SIZE_SHIFT 0 530 /* Reserved fields */ 531 #define PBS_UNIT_DRAM_3_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 532 #define PBS_UNIT_DRAM_3_NB_BAR_LOW_RSRVD_SHIFT 6 533 /* bar low address 16 MSB bits */ 534 #define PBS_UNIT_DRAM_3_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 535 #define PBS_UNIT_DRAM_3_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 536 537 /**** msix_nb_bar_low register ****/ 538 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 539 #define PBS_UNIT_MSIX_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 540 #define PBS_UNIT_MSIX_NB_BAR_LOW_WIN_SIZE_SHIFT 0 541 /* Reserved fields */ 542 #define PBS_UNIT_MSIX_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 543 #define PBS_UNIT_MSIX_NB_BAR_LOW_RSRVD_SHIFT 6 544 /* bar low address 16 MSB bits */ 545 #define PBS_UNIT_MSIX_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 546 #define PBS_UNIT_MSIX_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 547 548 /**** dram_0_sb_bar_low register ****/ 549 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 550 #define PBS_UNIT_DRAM_0_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 551 #define PBS_UNIT_DRAM_0_SB_BAR_LOW_WIN_SIZE_SHIFT 0 552 /* Reserved fields */ 553 #define PBS_UNIT_DRAM_0_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 554 #define PBS_UNIT_DRAM_0_SB_BAR_LOW_RSRVD_SHIFT 6 555 /* bar low address 16 MSB bits */ 556 #define PBS_UNIT_DRAM_0_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 557 #define PBS_UNIT_DRAM_0_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 558 559 /**** dram_1_sb_bar_low register ****/ 560 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 561 #define PBS_UNIT_DRAM_1_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 562 #define PBS_UNIT_DRAM_1_SB_BAR_LOW_WIN_SIZE_SHIFT 0 563 /* Reserved fields */ 564 #define PBS_UNIT_DRAM_1_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 565 #define PBS_UNIT_DRAM_1_SB_BAR_LOW_RSRVD_SHIFT 6 566 /* bar low address 16 MSB bits */ 567 #define PBS_UNIT_DRAM_1_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 568 #define PBS_UNIT_DRAM_1_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 569 570 /**** dram_2_sb_bar_low register ****/ 571 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 572 #define PBS_UNIT_DRAM_2_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 573 #define PBS_UNIT_DRAM_2_SB_BAR_LOW_WIN_SIZE_SHIFT 0 574 /* Reserved fields */ 575 #define PBS_UNIT_DRAM_2_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 576 #define PBS_UNIT_DRAM_2_SB_BAR_LOW_RSRVD_SHIFT 6 577 /* bar low address 16 MSB bits */ 578 #define PBS_UNIT_DRAM_2_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 579 #define PBS_UNIT_DRAM_2_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 580 581 /**** dram_3_sb_bar_low register ****/ 582 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 583 #define PBS_UNIT_DRAM_3_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 584 #define PBS_UNIT_DRAM_3_SB_BAR_LOW_WIN_SIZE_SHIFT 0 585 /* Reserved fields */ 586 #define PBS_UNIT_DRAM_3_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 587 #define PBS_UNIT_DRAM_3_SB_BAR_LOW_RSRVD_SHIFT 6 588 /* bar low address 16 MSB bits */ 589 #define PBS_UNIT_DRAM_3_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 590 #define PBS_UNIT_DRAM_3_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 591 592 /**** msix_sb_bar_low register ****/ 593 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 594 #define PBS_UNIT_MSIX_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 595 #define PBS_UNIT_MSIX_SB_BAR_LOW_WIN_SIZE_SHIFT 0 596 /* Reserved fields */ 597 #define PBS_UNIT_MSIX_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 598 #define PBS_UNIT_MSIX_SB_BAR_LOW_RSRVD_SHIFT 6 599 /* bar low address 16 MSB bits */ 600 #define PBS_UNIT_MSIX_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 601 #define PBS_UNIT_MSIX_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 602 603 /**** pcie_mem0_bar_low register ****/ 604 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 605 #define PBS_UNIT_PCIE_MEM0_BAR_LOW_WIN_SIZE_MASK 0x0000003F 606 #define PBS_UNIT_PCIE_MEM0_BAR_LOW_WIN_SIZE_SHIFT 0 607 /* Reserved fields */ 608 #define PBS_UNIT_PCIE_MEM0_BAR_LOW_RSRVD_MASK 0x0000FFC0 609 #define PBS_UNIT_PCIE_MEM0_BAR_LOW_RSRVD_SHIFT 6 610 /* bar low address 16 MSB bits */ 611 #define PBS_UNIT_PCIE_MEM0_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 612 #define PBS_UNIT_PCIE_MEM0_BAR_LOW_ADDR_HIGH_SHIFT 16 613 614 /**** pcie_mem1_bar_low register ****/ 615 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 616 #define PBS_UNIT_PCIE_MEM1_BAR_LOW_WIN_SIZE_MASK 0x0000003F 617 #define PBS_UNIT_PCIE_MEM1_BAR_LOW_WIN_SIZE_SHIFT 0 618 /* Reserved fields */ 619 #define PBS_UNIT_PCIE_MEM1_BAR_LOW_RSRVD_MASK 0x0000FFC0 620 #define PBS_UNIT_PCIE_MEM1_BAR_LOW_RSRVD_SHIFT 6 621 /* bar low address 16 MSB bits */ 622 #define PBS_UNIT_PCIE_MEM1_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 623 #define PBS_UNIT_PCIE_MEM1_BAR_LOW_ADDR_HIGH_SHIFT 16 624 625 /**** pcie_mem2_bar_low register ****/ 626 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 627 #define PBS_UNIT_PCIE_MEM2_BAR_LOW_WIN_SIZE_MASK 0x0000003F 628 #define PBS_UNIT_PCIE_MEM2_BAR_LOW_WIN_SIZE_SHIFT 0 629 /* Reserved fields */ 630 #define PBS_UNIT_PCIE_MEM2_BAR_LOW_RSRVD_MASK 0x0000FFC0 631 #define PBS_UNIT_PCIE_MEM2_BAR_LOW_RSRVD_SHIFT 6 632 /* bar low address 16 MSB bits */ 633 #define PBS_UNIT_PCIE_MEM2_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 634 #define PBS_UNIT_PCIE_MEM2_BAR_LOW_ADDR_HIGH_SHIFT 16 635 636 /**** pcie_ext_ecam0_bar_low register ****/ 637 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 638 #define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_WIN_SIZE_MASK 0x0000003F 639 #define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_WIN_SIZE_SHIFT 0 640 /* Reserved fields */ 641 #define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_RSRVD_MASK 0x0000FFC0 642 #define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_RSRVD_SHIFT 6 643 /* bar low address 16 MSB bits */ 644 #define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 645 #define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_ADDR_HIGH_SHIFT 16 646 647 /**** pcie_ext_ecam1_bar_low register ****/ 648 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 649 #define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_WIN_SIZE_MASK 0x0000003F 650 #define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_WIN_SIZE_SHIFT 0 651 /* Reserved fields */ 652 #define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_RSRVD_MASK 0x0000FFC0 653 #define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_RSRVD_SHIFT 6 654 /* bar low address 16 MSB bits */ 655 #define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 656 #define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_ADDR_HIGH_SHIFT 16 657 658 /**** pcie_ext_ecam2_bar_low register ****/ 659 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 660 #define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_WIN_SIZE_MASK 0x0000003F 661 #define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_WIN_SIZE_SHIFT 0 662 /* Reserved fields */ 663 #define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_RSRVD_MASK 0x0000FFC0 664 #define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_RSRVD_SHIFT 6 665 /* bar low address 16 MSB bits */ 666 #define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 667 #define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_ADDR_HIGH_SHIFT 16 668 669 /**** pbs_nor_bar_low register ****/ 670 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 671 #define PBS_UNIT_PBS_NOR_BAR_LOW_WIN_SIZE_MASK 0x0000003F 672 #define PBS_UNIT_PBS_NOR_BAR_LOW_WIN_SIZE_SHIFT 0 673 /* Reserved fields */ 674 #define PBS_UNIT_PBS_NOR_BAR_LOW_RSRVD_MASK 0x0000FFC0 675 #define PBS_UNIT_PBS_NOR_BAR_LOW_RSRVD_SHIFT 6 676 /* bar low address 16 MSB bits */ 677 #define PBS_UNIT_PBS_NOR_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 678 #define PBS_UNIT_PBS_NOR_BAR_LOW_ADDR_HIGH_SHIFT 16 679 680 /**** pbs_spi_bar_low register ****/ 681 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 682 #define PBS_UNIT_PBS_SPI_BAR_LOW_WIN_SIZE_MASK 0x0000003F 683 #define PBS_UNIT_PBS_SPI_BAR_LOW_WIN_SIZE_SHIFT 0 684 /* Reserved fields */ 685 #define PBS_UNIT_PBS_SPI_BAR_LOW_RSRVD_MASK 0x0000FFC0 686 #define PBS_UNIT_PBS_SPI_BAR_LOW_RSRVD_SHIFT 6 687 /* bar low address 16 MSB bits */ 688 #define PBS_UNIT_PBS_SPI_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 689 #define PBS_UNIT_PBS_SPI_BAR_LOW_ADDR_HIGH_SHIFT 16 690 691 /**** pbs_nand_bar_low register ****/ 692 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 693 #define PBS_UNIT_PBS_NAND_BAR_LOW_WIN_SIZE_MASK 0x0000003F 694 #define PBS_UNIT_PBS_NAND_BAR_LOW_WIN_SIZE_SHIFT 0 695 /* Reserved fields */ 696 #define PBS_UNIT_PBS_NAND_BAR_LOW_RSRVD_MASK 0x0000FFC0 697 #define PBS_UNIT_PBS_NAND_BAR_LOW_RSRVD_SHIFT 6 698 /* bar low address 16 MSB bits */ 699 #define PBS_UNIT_PBS_NAND_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 700 #define PBS_UNIT_PBS_NAND_BAR_LOW_ADDR_HIGH_SHIFT 16 701 702 /**** pbs_int_mem_bar_low register ****/ 703 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 704 #define PBS_UNIT_PBS_INT_MEM_BAR_LOW_WIN_SIZE_MASK 0x0000003F 705 #define PBS_UNIT_PBS_INT_MEM_BAR_LOW_WIN_SIZE_SHIFT 0 706 /* Reserved fields */ 707 #define PBS_UNIT_PBS_INT_MEM_BAR_LOW_RSRVD_MASK 0x0000FFC0 708 #define PBS_UNIT_PBS_INT_MEM_BAR_LOW_RSRVD_SHIFT 6 709 /* bar low address 16 MSB bits */ 710 #define PBS_UNIT_PBS_INT_MEM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 711 #define PBS_UNIT_PBS_INT_MEM_BAR_LOW_ADDR_HIGH_SHIFT 16 712 713 /**** pbs_boot_bar_low register ****/ 714 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 715 #define PBS_UNIT_PBS_BOOT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 716 #define PBS_UNIT_PBS_BOOT_BAR_LOW_WIN_SIZE_SHIFT 0 717 /* Reserved fields */ 718 #define PBS_UNIT_PBS_BOOT_BAR_LOW_RSRVD_MASK 0x0000FFC0 719 #define PBS_UNIT_PBS_BOOT_BAR_LOW_RSRVD_SHIFT 6 720 /* bar low address 16 MSB bits */ 721 #define PBS_UNIT_PBS_BOOT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 722 #define PBS_UNIT_PBS_BOOT_BAR_LOW_ADDR_HIGH_SHIFT 16 723 724 /**** nb_int_bar_low register ****/ 725 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 726 #define PBS_UNIT_NB_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 727 #define PBS_UNIT_NB_INT_BAR_LOW_WIN_SIZE_SHIFT 0 728 /* Reserved fields */ 729 #define PBS_UNIT_NB_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0 730 #define PBS_UNIT_NB_INT_BAR_LOW_RSRVD_SHIFT 6 731 /* bar low address 16 MSB bits */ 732 #define PBS_UNIT_NB_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 733 #define PBS_UNIT_NB_INT_BAR_LOW_ADDR_HIGH_SHIFT 16 734 735 /**** nb_stm_bar_low register ****/ 736 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 737 #define PBS_UNIT_NB_STM_BAR_LOW_WIN_SIZE_MASK 0x0000003F 738 #define PBS_UNIT_NB_STM_BAR_LOW_WIN_SIZE_SHIFT 0 739 /* Reserved fields */ 740 #define PBS_UNIT_NB_STM_BAR_LOW_RSRVD_MASK 0x0000FFC0 741 #define PBS_UNIT_NB_STM_BAR_LOW_RSRVD_SHIFT 6 742 /* bar low address 16 MSB bits */ 743 #define PBS_UNIT_NB_STM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 744 #define PBS_UNIT_NB_STM_BAR_LOW_ADDR_HIGH_SHIFT 16 745 746 /**** pcie_ecam_int_bar_low register ****/ 747 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 748 #define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 749 #define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_WIN_SIZE_SHIFT 0 750 /* Reserved fields */ 751 #define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0 752 #define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_RSRVD_SHIFT 6 753 /* bar low address 16 MSB bits */ 754 #define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 755 #define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_ADDR_HIGH_SHIFT 16 756 757 /**** pcie_mem_int_bar_low register ****/ 758 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 759 #define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 760 #define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_WIN_SIZE_SHIFT 0 761 /* Reserved fields */ 762 #define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0 763 #define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_RSRVD_SHIFT 6 764 /* bar low address 16 MSB bits */ 765 #define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 766 #define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_ADDR_HIGH_SHIFT 16 767 768 /**** winit_cntl register ****/ 769 /* When set, enables access to winit regs, in normal mode. */ 770 #define PBS_UNIT_WINIT_CNTL_ENABLE_WINIT_REGS_ACCESS (1 << 0) 771 /* Reserved */ 772 #define PBS_UNIT_WINIT_CNTL_RSRVD_MASK 0xFFFFFFFE 773 #define PBS_UNIT_WINIT_CNTL_RSRVD_SHIFT 1 774 775 /**** latch_bars register ****/ 776 /* 777 * Software clears this bit before any bar update, and set it after all bars 778 * updated. 779 */ 780 #define PBS_UNIT_LATCH_BARS_ENABLE (1 << 0) 781 /* Reserved */ 782 #define PBS_UNIT_LATCH_BARS_RSRVD_MASK 0xFFFFFFFE 783 #define PBS_UNIT_LATCH_BARS_RSRVD_SHIFT 1 784 785 /**** pcie_conf_0 register ****/ 786 /* NOT_use, config internal inside each PCIe core */ 787 #define PBS_UNIT_PCIE_CONF_0_DEVS_TYPE_MASK 0x00000FFF 788 #define PBS_UNIT_PCIE_CONF_0_DEVS_TYPE_SHIFT 0 789 /* sys_aux_det value */ 790 #define PBS_UNIT_PCIE_CONF_0_SYS_AUX_PWR_DET_VEC_MASK 0x00007000 791 #define PBS_UNIT_PCIE_CONF_0_SYS_AUX_PWR_DET_VEC_SHIFT 12 792 /* Reserved */ 793 #define PBS_UNIT_PCIE_CONF_0_RSRVD_MASK 0xFFFF8000 794 #define PBS_UNIT_PCIE_CONF_0_RSRVD_SHIFT 15 795 796 /**** pcie_conf_1 register ****/ 797 /* 798 * Which PCIe exists? The PCIe device is under reset until the corresponding bit 799 * is set. 800 */ 801 #define PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_MASK 0x0000003F 802 #define PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_SHIFT 0 803 /* Reserved */ 804 #define PBS_UNIT_PCIE_CONF_1_RSRVD_MASK 0xFFFFFFC0 805 #define PBS_UNIT_PCIE_CONF_1_RSRVD_SHIFT 6 806 807 /**** serdes_mux_pipe register ****/ 808 /* SerDes one hot mux control. For details see datasheet. */ 809 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_2_MASK 0x00000007 810 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_2_SHIFT 0 811 /* Reserved */ 812 #define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_3 (1 << 3) 813 /* SerDes one hot mux control. For details see datasheet. */ 814 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_3_MASK 0x00000070 815 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_3_SHIFT 4 816 /* Reserved */ 817 #define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_7 (1 << 7) 818 /* SerDes one hot mux control. For details see datasheet. */ 819 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_0_MASK 0x00000300 820 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_0_SHIFT 8 821 /* SerDes one hot mux control. For details see datasheet. */ 822 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_1_MASK 0x00000C00 823 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_1_SHIFT 10 824 /* SerDes one hot mux control. For details see datasheet. */ 825 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_0_MASK 0x00003000 826 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_0_SHIFT 12 827 /* SerDes one hot mux control. For details see datasheet. */ 828 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_1_MASK 0x0000C000 829 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_1_SHIFT 14 830 /* SerDes one hot mux control. For details see datasheet. */ 831 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_A_0_MASK 0x00030000 832 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_A_0_SHIFT 16 833 /* SerDes one hot mux control. For details see datasheet. */ 834 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_B_0_MASK 0x000C0000 835 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_B_0_SHIFT 18 836 /* SerDes one hot mux control. For details see datasheet. */ 837 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_2_MASK 0x00300000 838 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_2_SHIFT 20 839 /* Reserved */ 840 #define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_23_22_MASK 0x00C00000 841 #define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_23_22_SHIFT 22 842 /* SerDes one hot mux control. For details see datasheet. */ 843 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_3_MASK 0x07000000 844 #define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_3_SHIFT 24 845 /* Reserved */ 846 #define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_MASK 0xF8000000 847 #define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_SHIFT 27 848 849 /* 850 * 2'b01 - select pcie_b[0] 851 * 2'b10 - select pcie_a[2] 852 */ 853 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_2_MASK 0x00000003 854 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_2_SHIFT 0 855 /* 856 * 2'b01 - select pcie_b[1] 857 * 2'b10 - select pcie_a[3] 858 */ 859 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_3_MASK 0x00000030 860 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_3_SHIFT 4 861 /* 862 * 2'b01 - select pcie_b[0] 863 * 2'b10 - select pcie_a[4] 864 */ 865 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_4_MASK 0x00000300 866 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_4_SHIFT 8 867 /* 868 * 2'b01 - select pcie_b[1] 869 * 2'b10 - select pcie_a[5] 870 */ 871 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_5_MASK 0x00003000 872 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_5_SHIFT 12 873 /* 874 * 2'b01 - select pcie_b[2] 875 * 2'b10 - select pcie_a[6] 876 */ 877 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_6_MASK 0x00030000 878 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_6_SHIFT 16 879 /* 880 * 2'b01 - select pcie_b[3] 881 * 2'b10 - select pcie_a[7] 882 */ 883 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_7_MASK 0x00300000 884 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_7_SHIFT 20 885 /* 886 * 2'b01 - select pcie_d[0] 887 * 2'b10 - select pcie_c[2] 888 */ 889 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_10_MASK 0x03000000 890 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_10_SHIFT 24 891 /* 892 * 2'b01 - select pcie_d[1] 893 * 2'b10 - select pcie_c[3] 894 */ 895 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_11_MASK 0x30000000 896 #define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_11_SHIFT 28 897 898 /**** dma_io_master_map register ****/ 899 /* 900 * [0]: When set, maps all the io_dma transactions to the NB/DRAM, regardless of 901 * the window hit. 902 * [1]: When set, maps all the eth_0 transactions to the NB/DRAM, regardless of 903 * the window hit. 904 * [2]: When set, maps all the eth_2 transaction to the NB/DRAM, regardless of 905 * the window hit. 906 * [3]: When set, maps all the sata_0 transactions to the NB/DRAM, regardless of 907 * the window hit. 908 * [4]: When set, maps all the sata_1 transactions to the NB/DRAM, regardless of 909 * the window hit. 910 * [5]: When set, maps all the pcie_0 master transactions to the NB/DRAM, 911 * regardless of the window hit. 912 * [6]: When set, maps all the SPI debug port transactions to the NB/DRAM, 913 * regardless of the window hit. 914 * [7]: When set, maps all the CPU debug port transactions to the NB/DRAM, 915 * regardless of the window hit. 916 * [8] When set, maps all the Crypto transactions to the NB/DRAM, regardless of 917 * the window hit. 918 * [15:9] - Reserved 919 */ 920 #define PBS_UNIT_DMA_IO_MASTER_MAP_CNTL_MASK 0x0000FFFF 921 #define PBS_UNIT_DMA_IO_MASTER_MAP_CNTL_SHIFT 0 922 /* Reserved fields */ 923 #define PBS_UNIT_DMA_IO_MASTER_MAP_RSRVD_MASK 0xFFFF0000 924 #define PBS_UNIT_DMA_IO_MASTER_MAP_RSRVD_SHIFT 16 925 926 /**** i2c_pld_status_high register ****/ 927 /* I2C pre-load status */ 928 #define PBS_UNIT_I2C_PLD_STATUS_HIGH_STATUS_MASK 0x000000FF 929 #define PBS_UNIT_I2C_PLD_STATUS_HIGH_STATUS_SHIFT 0 930 931 /**** spi_dbg_status_high register ****/ 932 /* SPI DBG load status */ 933 #define PBS_UNIT_SPI_DBG_STATUS_HIGH_STATUS_MASK 0x000000FF 934 #define PBS_UNIT_SPI_DBG_STATUS_HIGH_STATUS_SHIFT 0 935 936 /**** spi_mst_status_high register ****/ 937 /* SP IMST load status */ 938 #define PBS_UNIT_SPI_MST_STATUS_HIGH_STATUS_MASK 0x000000FF 939 #define PBS_UNIT_SPI_MST_STATUS_HIGH_STATUS_SHIFT 0 940 941 /**** mem_pbs_parity_err_high register ****/ 942 /* Address latch in the case of a parity error */ 943 #define PBS_UNIT_MEM_PBS_PARITY_ERR_HIGH_ADDR_MASK 0x000000FF 944 #define PBS_UNIT_MEM_PBS_PARITY_ERR_HIGH_ADDR_SHIFT 0 945 946 /**** cfg_axi_conf_0 register ****/ 947 /* Sets the AXI field in the I2C preloader interface. */ 948 #define PBS_UNIT_CFG_AXI_CONF_0_DBG_RD_ID_MASK 0x0000007F 949 #define PBS_UNIT_CFG_AXI_CONF_0_DBG_RD_ID_SHIFT 0 950 /* Sets the AXI field in the I2C preloader interface. */ 951 #define PBS_UNIT_CFG_AXI_CONF_0_DBG_WR_ID_MASK 0x00003F80 952 #define PBS_UNIT_CFG_AXI_CONF_0_DBG_WR_ID_SHIFT 7 953 /* Sets the AXI field in the I2C preloader interface. */ 954 #define PBS_UNIT_CFG_AXI_CONF_0_PLD_WR_ID_MASK 0x001FC000 955 #define PBS_UNIT_CFG_AXI_CONF_0_PLD_WR_ID_SHIFT 14 956 /* Sets the AXI field in the SPI debug interface. */ 957 #define PBS_UNIT_CFG_AXI_CONF_0_DBG_AWCACHE_MASK 0x01E00000 958 #define PBS_UNIT_CFG_AXI_CONF_0_DBG_AWCACHE_SHIFT 21 959 /* Sets the AXI field in the SPI debug interface. */ 960 #define PBS_UNIT_CFG_AXI_CONF_0_DBG_ARCACHE_MASK 0x1E000000 961 #define PBS_UNIT_CFG_AXI_CONF_0_DBG_ARCACHE_SHIFT 25 962 /* Sets the AXI field in the SPI debug interface. */ 963 #define PBS_UNIT_CFG_AXI_CONF_0_DBG_AXPROT_MASK 0xE0000000 964 #define PBS_UNIT_CFG_AXI_CONF_0_DBG_AXPROT_SHIFT 29 965 966 /**** cfg_axi_conf_1 register ****/ 967 /* Sets the AXI field in the SPI debug interface. */ 968 #define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARUSER_MASK 0x03FFFFFF 969 #define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARUSER_SHIFT 0 970 /* Sets the AXI field in the SPI debug interface. */ 971 #define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARQOS_MASK 0x3C000000 972 #define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARQOS_SHIFT 26 973 974 /**** cfg_axi_conf_2 register ****/ 975 /* Sets the AXI field in the SPI debug interface. */ 976 #define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWUSER_MASK 0x03FFFFFF 977 #define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWUSER_SHIFT 0 978 /* Sets the AXI field in the SPI debug interface. */ 979 #define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_MASK 0x3C000000 980 #define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_SHIFT 26 981 982 /**** cfg_axi_conf_3 register ****/ 983 #define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_LOW_MASK 0xFFFF 984 #define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_LOW_SHIFT 0 985 #define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_HI_MASK 0xFF0000 986 #define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_HI_SHIFT 16 987 #define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_SPI_HI_MASK 0xFF000000 988 #define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_SPI_HI_SHIFT 24 989 990 /**** spi_mst_conf_0 register ****/ 991 /* 992 * Sets the SPI master Configuration. For details see the SPI section in the 993 * documentation. 994 */ 995 #define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SRL (1 << 0) 996 /* 997 * Sets the SPI master Configuration. For details see the SPI section in the 998 * documentation. 999 */ 1000 #define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SCPOL (1 << 1) 1001 /* 1002 * Sets the SPI master Configuration. For details see the SPI section in the 1003 * documentation. 1004 */ 1005 #define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SCPH (1 << 2) 1006 /* 1007 * Set the SPI master configuration. For details see the SPI section in the 1008 * documentation. 1009 */ 1010 #define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SER_MASK 0x00000078 1011 #define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SER_SHIFT 3 1012 /* 1013 * Set the SPI master configuration. For details see the SPI section in the 1014 * documentation. 1015 */ 1016 #define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_BAUD_MASK 0x007FFF80 1017 #define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_BAUD_SHIFT 7 1018 /* 1019 * Sets the SPI master configuration. For details see the SPI section in the 1020 * documentation. 1021 */ 1022 #define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_RD_CMD_MASK 0x7F800000 1023 #define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_RD_CMD_SHIFT 23 1024 1025 /**** spi_mst_conf_1 register ****/ 1026 /* 1027 * Sets the SPI master Configuration. For details see the SPI section in the 1028 * documentation. 1029 */ 1030 #define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_WR_CMD_MASK 0x000000FF 1031 #define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_WR_CMD_SHIFT 0 1032 /* 1033 * Sets the SPI master Configuration. For details see the SPI section in the 1034 * documentation. 1035 */ 1036 #define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_ADDR_BYTES_NUM_MASK 0x00000700 1037 #define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_ADDR_BYTES_NUM_SHIFT 8 1038 /* 1039 * Sets the SPI master Configuration. For details see the SPI section in the 1040 * documentation. 1041 */ 1042 #define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_TMODE_MASK 0x00001800 1043 #define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_TMODE_SHIFT 11 1044 /* 1045 * Sets the SPI master Configuration. For details see the SPI section in the 1046 * documentation. 1047 */ 1048 #define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_FAST_RD (1 << 13) 1049 1050 /**** spi_slv_conf_0 register ****/ 1051 /* 1052 * Sets the SPI slave configuration. For details see the SPI section in the 1053 * documentation. 1054 */ 1055 #define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_BAUD_MASK 0x0000FFFF 1056 #define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_BAUD_SHIFT 0 1057 /* Value. The reset value is according to bootstrap. */ 1058 #define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SCPOL (1 << 16) 1059 /* Value. The reset value is according to bootstrap. */ 1060 #define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SCPH (1 << 17) 1061 /* 1062 * Sets the SPI slave configuration. For details see the SPI section in the 1063 * documentation. 1064 */ 1065 #define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SER_MASK 0x03FC0000 1066 #define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SER_SHIFT 18 1067 /* 1068 * Sets the SPI slave configuration. For details see the SPI section in the 1069 * documentation. 1070 */ 1071 #define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SRL (1 << 26) 1072 /* 1073 * Sets the SPI slave configuration. For details see the SPI section in the 1074 * documentation. 1075 */ 1076 #define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_TMODE_MASK 0x18000000 1077 #define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_TMODE_SHIFT 27 1078 1079 /**** apb_mem_conf_int register ****/ 1080 /* Value-- internal */ 1081 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_WRR_CNT_MASK 0x00000007 1082 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_WRR_CNT_SHIFT 0 1083 /* Value-- internal */ 1084 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_I2C_PLD_APB_MIX_ARB (1 << 3) 1085 /* Value-- internal */ 1086 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_DBG_APB_MIX_ARB (1 << 4) 1087 /* Value-- internal */ 1088 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_MST_APB_MIX_ARB (1 << 5) 1089 /* Value-- internal */ 1090 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_I2C_PLD_CLEAR_FSM (1 << 6) 1091 /* Value-- internal */ 1092 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_DBG_CLEAR_FSM (1 << 7) 1093 /* Value-- internal */ 1094 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_MST_CLEAR_FSM (1 << 8) 1095 /* Value-- internal */ 1096 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_AXI_FSM_CLEAR (1 << 9) 1097 /* Value-- internal */ 1098 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_AXI_FIFOS_CLEAR (1 << 10) 1099 /* Enables parity protection on the integrated SRAM. */ 1100 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_BOOTROM_PARITY_EN (1 << 11) 1101 /* 1102 * When set, reports a slave error whenthe slave returns an AXI slave error, for 1103 * configuration access to the internal configuration space. 1104 */ 1105 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_RD_SLV_ERR_EN (1 << 12) 1106 /* 1107 * When set, reports a decode error when timeout has occurred for configuration 1108 * access to the internal configuration space. 1109 */ 1110 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_RD_DEC_ERR_EN (1 << 13) 1111 /* 1112 * When set, reports a slave error, when the slave returns an AXI slave error, 1113 * for configuration access to the internal configuration space. 1114 */ 1115 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_WR_SLV_ERR_EN (1 << 14) 1116 /* 1117 * When set, reports a decode error when timeout has occurred for configuration 1118 * access to the internal configuration space. 1119 */ 1120 #define PBS_UNIT_APB_MEM_CONF_INT_CFG_WR_DEC_ERR_EN (1 << 15) 1121 1122 /**** sb_int_bar_low register ****/ 1123 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1124 #define PBS_UNIT_SB_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1125 #define PBS_UNIT_SB_INT_BAR_LOW_WIN_SIZE_SHIFT 0 1126 /* Reserved fields */ 1127 #define PBS_UNIT_SB_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0 1128 #define PBS_UNIT_SB_INT_BAR_LOW_RSRVD_SHIFT 6 1129 /* bar low address 16 MSB bits */ 1130 #define PBS_UNIT_SB_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1131 #define PBS_UNIT_SB_INT_BAR_LOW_ADDR_HIGH_SHIFT 16 1132 1133 /**** ufc_pbs_parity_err_high register ****/ 1134 /* 1135 * Address latch in the case of a parity error in the Flash Controller internal 1136 * memories. 1137 */ 1138 #define PBS_UNIT_UFC_PBS_PARITY_ERR_HIGH_ADDR_MASK 0x000000FF 1139 #define PBS_UNIT_UFC_PBS_PARITY_ERR_HIGH_ADDR_SHIFT 0 1140 1141 /**** chip_id register ****/ 1142 /* [15:0] : Dev Rev ID */ 1143 #define PBS_UNIT_CHIP_ID_DEV_REV_ID_MASK 0x0000FFFF 1144 #define PBS_UNIT_CHIP_ID_DEV_REV_ID_SHIFT 0 1145 /* [31:16] : 0x0 - Dev ID */ 1146 #define PBS_UNIT_CHIP_ID_DEV_ID_MASK 0xFFFF0000 1147 #define PBS_UNIT_CHIP_ID_DEV_ID_SHIFT 16 1148 1149 #define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE_V1 0 1150 #define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE_V2 1 1151 #define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE_V3 2 1152 1153 /**** uart0_conf_status register ****/ 1154 /* 1155 * Conf: 1156 * // [0] -- DSR_N RW bit 1157 * // [1] -- DCD_N RW bit 1158 * // [2] -- RI_N bit 1159 * // [3] -- dma_tx_ack_n 1160 * // [4] -- dma_rx_ack_n 1161 */ 1162 #define PBS_UNIT_UART0_CONF_STATUS_CONF_MASK 0x0000FFFF 1163 #define PBS_UNIT_UART0_CONF_STATUS_CONF_SHIFT 0 1164 /* 1165 * Status: 1166 * // [16] -- dtr_n RO bit 1167 * // [17] -- OUT1_N RO bit 1168 * // [18] -- OUT2_N RO bit 1169 * // [19] -- dma_tx_req_n RO bit 1170 * // [20] -- dma_tx_single_n RO bit 1171 * // [21] -- dma_rx_req_n RO bit 1172 * // [22] -- dma_rx_single_n RO bit 1173 * // [23] -- uart_lp_req_pclk RO bit 1174 * // [24] -- baudout_n RO bit 1175 */ 1176 #define PBS_UNIT_UART0_CONF_STATUS_STATUS_MASK 0xFFFF0000 1177 #define PBS_UNIT_UART0_CONF_STATUS_STATUS_SHIFT 16 1178 1179 /**** uart1_conf_status register ****/ 1180 /* 1181 * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3] 1182 * -- dma_tx_ack_n // [4] - dma_rx_ack_n 1183 */ 1184 #define PBS_UNIT_UART1_CONF_STATUS_CONF_MASK 0x0000FFFF 1185 #define PBS_UNIT_UART1_CONF_STATUS_CONF_SHIFT 0 1186 /* 1187 * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO 1188 * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21] 1189 * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] -- 1190 * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit 1191 */ 1192 #define PBS_UNIT_UART1_CONF_STATUS_STATUS_MASK 0xFFFF0000 1193 #define PBS_UNIT_UART1_CONF_STATUS_STATUS_SHIFT 16 1194 1195 /**** uart2_conf_status register ****/ 1196 /* 1197 * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3] 1198 * -- dma_tx_ack_n // [4] - dma_rx_ack_n 1199 */ 1200 #define PBS_UNIT_UART2_CONF_STATUS_CONF_MASK 0x0000FFFF 1201 #define PBS_UNIT_UART2_CONF_STATUS_CONF_SHIFT 0 1202 /* 1203 * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO 1204 * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21] 1205 * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] -- 1206 * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit 1207 */ 1208 #define PBS_UNIT_UART2_CONF_STATUS_STATUS_MASK 0xFFFF0000 1209 #define PBS_UNIT_UART2_CONF_STATUS_STATUS_SHIFT 16 1210 1211 /**** uart3_conf_status register ****/ 1212 /* 1213 * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3] 1214 * -- dma_tx_ack_n // [4] - dma_rx_ack_n 1215 */ 1216 #define PBS_UNIT_UART3_CONF_STATUS_CONF_MASK 0x0000FFFF 1217 #define PBS_UNIT_UART3_CONF_STATUS_CONF_SHIFT 0 1218 /* 1219 * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO 1220 * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21] 1221 * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] -- 1222 * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit 1223 */ 1224 #define PBS_UNIT_UART3_CONF_STATUS_STATUS_MASK 0xFFFF0000 1225 #define PBS_UNIT_UART3_CONF_STATUS_STATUS_SHIFT 16 1226 1227 /**** gpio0_conf_status register ****/ 1228 /* 1229 * Cntl: 1230 * // [7:0] nGPAFEN; // from regfile 1231 * // [15:8] GPAFOUT; // from regfile 1232 */ 1233 #define PBS_UNIT_GPIO0_CONF_STATUS_CONF_MASK 0x0000FFFF 1234 #define PBS_UNIT_GPIO0_CONF_STATUS_CONF_SHIFT 0 1235 /* 1236 * Status: 1237 * // [24:16] GPAFIN; // to regfile 1238 */ 1239 #define PBS_UNIT_GPIO0_CONF_STATUS_STATUS_MASK 0xFFFF0000 1240 #define PBS_UNIT_GPIO0_CONF_STATUS_STATUS_SHIFT 16 1241 1242 /**** gpio1_conf_status register ****/ 1243 /* 1244 * Cntl: 1245 * // [7:0] nGPAFEN; // from regfile 1246 * // [15:8] GPAFOUT; // from regfile 1247 */ 1248 #define PBS_UNIT_GPIO1_CONF_STATUS_CONF_MASK 0x0000FFFF 1249 #define PBS_UNIT_GPIO1_CONF_STATUS_CONF_SHIFT 0 1250 /* 1251 * Status: 1252 * // [24:16] GPAFIN; // to regfile 1253 */ 1254 #define PBS_UNIT_GPIO1_CONF_STATUS_STATUS_MASK 0xFFFF0000 1255 #define PBS_UNIT_GPIO1_CONF_STATUS_STATUS_SHIFT 16 1256 1257 /**** gpio2_conf_status register ****/ 1258 /* 1259 * Cntl: 1260 * // [7:0] nGPAFEN; // from regfile 1261 * // [15:8] GPAFOUT; // from regfile 1262 */ 1263 #define PBS_UNIT_GPIO2_CONF_STATUS_CONF_MASK 0x0000FFFF 1264 #define PBS_UNIT_GPIO2_CONF_STATUS_CONF_SHIFT 0 1265 /* 1266 * Status: 1267 * // [24:16] GPAFIN; // to regfile 1268 */ 1269 #define PBS_UNIT_GPIO2_CONF_STATUS_STATUS_MASK 0xFFFF0000 1270 #define PBS_UNIT_GPIO2_CONF_STATUS_STATUS_SHIFT 16 1271 1272 /**** gpio3_conf_status register ****/ 1273 /* 1274 * Cntl: 1275 * // [7:0] nGPAFEN; // from regfile 1276 * // [15:8] GPAFOUT; // from regfile 1277 */ 1278 #define PBS_UNIT_GPIO3_CONF_STATUS_CONF_MASK 0x0000FFFF 1279 #define PBS_UNIT_GPIO3_CONF_STATUS_CONF_SHIFT 0 1280 /* 1281 * Status: 1282 * // [24:16] GPAFIN; // to regfile 1283 */ 1284 #define PBS_UNIT_GPIO3_CONF_STATUS_STATUS_MASK 0xFFFF0000 1285 #define PBS_UNIT_GPIO3_CONF_STATUS_STATUS_SHIFT 16 1286 1287 /**** gpio4_conf_status register ****/ 1288 /* 1289 * Cntl: 1290 * // [7:0] nGPAFEN; // from regfile 1291 * // [15:8] GPAFOUT; // from regfile 1292 */ 1293 #define PBS_UNIT_GPIO4_CONF_STATUS_CONF_MASK 0x0000FFFF 1294 #define PBS_UNIT_GPIO4_CONF_STATUS_CONF_SHIFT 0 1295 /* 1296 * Status: 1297 * // [24:16] GPAFIN; // to regfile 1298 */ 1299 #define PBS_UNIT_GPIO4_CONF_STATUS_STATUS_MASK 0xFFFF0000 1300 #define PBS_UNIT_GPIO4_CONF_STATUS_STATUS_SHIFT 16 1301 1302 /**** i2c_gen_conf_status register ****/ 1303 /* 1304 * cntl 1305 * // [0] -- dma_tx_ack 1306 * // [1] -- dma_rx_ack 1307 */ 1308 #define PBS_UNIT_I2C_GEN_CONF_STATUS_CONF_MASK 0x0000FFFF 1309 #define PBS_UNIT_I2C_GEN_CONF_STATUS_CONF_SHIFT 0 1310 /* 1311 * Status 1312 * 1313 * // [16] -- dma_tx_req RO bit 1314 * // [17] -- dma_tx_single RO bit 1315 * // [18] -- dma_rx_req RO bit 1316 * // [19] -- dma_rx_single RO bit 1317 */ 1318 #define PBS_UNIT_I2C_GEN_CONF_STATUS_STATUS_MASK 0xFFFF0000 1319 #define PBS_UNIT_I2C_GEN_CONF_STATUS_STATUS_SHIFT 16 1320 1321 /**** watch_dog_reset_out register ****/ 1322 /* 1323 * [0] If set to 1'b1, WD0 cannot generate reset_out_n 1324 * [1] If set to 1'b1, WD1 cannot generate reset_out_n 1325 * [2] If set to 1'b1, WD2 cannot generate reset_out_n 1326 * [3] If set to 1'b1, WD3 cannot generate reset_out_n 1327 * [4] If set to 1'b1, WD4 cannot generate reset_out_n 1328 * [5] If set to 1'b1, WD5 cannot generate reset_out_n 1329 * [6] If set to 1'b1, WD6 cannot generate reset_out_n 1330 * [7] If set to 1'b1, WD7 cannot generate reset_out_n 1331 */ 1332 #define PBS_UNIT_WATCH_DOG_RESET_OUT_DISABLE_MASK 0x000000FF 1333 #define PBS_UNIT_WATCH_DOG_RESET_OUT_DISABLE_SHIFT 0 1334 1335 /**** otp_cntl register ****/ 1336 /* from reg file Config To bypass the copy from OTPW to OTPR */ 1337 #define PBS_UNIT_OTP_CNTL_IGNORE_OTPW (1 << 0) 1338 /* Not in use.Comes from bond. */ 1339 #define PBS_UNIT_OTP_CNTL_IGNORE_PRELOAD (1 << 1) 1340 /* Margin read from the fuse box */ 1341 #define PBS_UNIT_OTP_CNTL_OTPW_MARGIN_READ (1 << 2) 1342 /* Indicates when OTPis busy. */ 1343 #define PBS_UNIT_OTP_CNTL_OTP_BUSY (1 << 3) 1344 1345 /**** otp_cfg_0 register ****/ 1346 /* Cfg to OTP cntl. */ 1347 #define PBS_UNIT_OTP_CFG_0_CFG_OTPW_PWRDN_CNT_MASK 0x0000FFFF 1348 #define PBS_UNIT_OTP_CFG_0_CFG_OTPW_PWRDN_CNT_SHIFT 0 1349 /* Cfg to OTP cntl. */ 1350 #define PBS_UNIT_OTP_CFG_0_CFG_OTPW_READ_CNT_MASK 0xFFFF0000 1351 #define PBS_UNIT_OTP_CFG_0_CFG_OTPW_READ_CNT_SHIFT 16 1352 1353 /**** otp_cfg_1 register ****/ 1354 /* Cfg to OTP cntl. */ 1355 #define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PGM_CNT_MASK 0x0000FFFF 1356 #define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PGM_CNT_SHIFT 0 1357 /* Cfg to OTP cntl. */ 1358 #define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PREP_CNT_MASK 0xFFFF0000 1359 #define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PREP_CNT_SHIFT 16 1360 1361 /**** otp_cfg_3 register ****/ 1362 /* Cfg to OTP cntl. */ 1363 #define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PS18_CNT_MASK 0x0000FFFF 1364 #define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PS18_CNT_SHIFT 0 1365 /* Cfg to OTP cntl. */ 1366 #define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PWRUP_CNT_MASK 0xFFFF0000 1367 #define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PWRUP_CNT_SHIFT 16 1368 1369 /**** nb_nic_regs_bar_low register ****/ 1370 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1371 #define PBS_UNIT_NB_NIC_REGS_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1372 #define PBS_UNIT_NB_NIC_REGS_BAR_LOW_WIN_SIZE_SHIFT 0 1373 /* Reserved fields */ 1374 #define PBS_UNIT_NB_NIC_REGS_BAR_LOW_RSRVD_MASK 0x0000FFC0 1375 #define PBS_UNIT_NB_NIC_REGS_BAR_LOW_RSRVD_SHIFT 6 1376 /* bar low address 16 MSB bits */ 1377 #define PBS_UNIT_NB_NIC_REGS_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1378 #define PBS_UNIT_NB_NIC_REGS_BAR_LOW_ADDR_HIGH_SHIFT 16 1379 1380 /**** sb_nic_regs_bar_low register ****/ 1381 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1382 #define PBS_UNIT_SB_NIC_REGS_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1383 #define PBS_UNIT_SB_NIC_REGS_BAR_LOW_WIN_SIZE_SHIFT 0 1384 /* Reserved fields */ 1385 #define PBS_UNIT_SB_NIC_REGS_BAR_LOW_RSRVD_MASK 0x0000FFC0 1386 #define PBS_UNIT_SB_NIC_REGS_BAR_LOW_RSRVD_SHIFT 6 1387 /* bar low address 16 MSB bits */ 1388 #define PBS_UNIT_SB_NIC_REGS_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1389 #define PBS_UNIT_SB_NIC_REGS_BAR_LOW_ADDR_HIGH_SHIFT 16 1390 1391 /**** serdes_mux_multi_0 register ****/ 1392 /* SerDes one hot mux control. For details see datasheet. */ 1393 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_8_MASK 0x00000007 1394 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_8_SHIFT 0 1395 /* Reserved */ 1396 #define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_3 (1 << 3) 1397 /* SerDes one hot mux control. For details see datasheet. */ 1398 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_9_MASK 0x00000070 1399 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_9_SHIFT 4 1400 /* Reserved */ 1401 #define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_7 (1 << 7) 1402 /* SerDes one hot mux control. For details see datasheet. */ 1403 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_10_MASK 0x00000700 1404 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_10_SHIFT 8 1405 /* Reserved */ 1406 #define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_11 (1 << 11) 1407 /* SerDes one hot mux control. For details see datasheet. */ 1408 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_11_MASK 0x00007000 1409 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_11_SHIFT 12 1410 /* Reserved */ 1411 #define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_15 (1 << 15) 1412 /* SerDes one hot mux control. For details see datasheet. */ 1413 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_12_MASK 0x00030000 1414 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_12_SHIFT 16 1415 /* SerDes one hot mux control. For details see datasheet. */ 1416 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_13_MASK 0x000C0000 1417 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_13_SHIFT 18 1418 /* SerDes one hot mux control. For details see datasheet. */ 1419 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_14_MASK 0x00300000 1420 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_14_SHIFT 20 1421 /* SerDes one hot mux control. For details see datasheet. */ 1422 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_15_MASK 0x00C00000 1423 #define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_15_SHIFT 22 1424 /* Reserved */ 1425 #define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_MASK 0xFF000000 1426 #define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_SHIFT 24 1427 1428 /* 1429 * 2'b01 - select sata_b[0] 1430 * 2'b10 - select eth_a[0] 1431 */ 1432 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_8_MASK 0x00000003 1433 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_8_SHIFT 0 1434 /* 1435 * 3'b001 - select sata_b[1] 1436 * 3'b010 - select eth_b[0] 1437 * 3'b100 - select eth_a[1] 1438 */ 1439 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_9_MASK 0x00000070 1440 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_9_SHIFT 4 1441 /* 1442 * 3'b001 - select sata_b[2] 1443 * 3'b010 - select eth_c[0] 1444 * 3'b100 - select eth_a[2] 1445 */ 1446 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_10_MASK 0x00000700 1447 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_10_SHIFT 8 1448 /* 1449 * 3'b001 - select sata_b[3] 1450 * 3'b010 - select eth_d[0] 1451 * 3'b100 - select eth_a[3] 1452 */ 1453 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_11_MASK 0x00007000 1454 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_11_SHIFT 12 1455 /* 1456 * 2'b01 - select eth_a[0] 1457 * 2'b10 - select sata_a[0] 1458 */ 1459 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_12_MASK 0x00030000 1460 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_12_SHIFT 16 1461 /* 1462 * 3'b001 - select eth_b[0] 1463 * 3'b010 - select eth_c[1] 1464 * 3'b100 - select sata_a[1] 1465 */ 1466 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_13_MASK 0x00700000 1467 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_13_SHIFT 20 1468 /* 1469 * 3'b001 - select eth_a[0] 1470 * 3'b010 - select eth_c[2] 1471 * 3'b100 - select sata_a[2] 1472 */ 1473 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_14_MASK 0x07000000 1474 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_14_SHIFT 24 1475 /* 1476 * 3'b001 - select eth_d[0] 1477 * 3'b010 - select eth_c[3] 1478 * 3'b100 - select sata_a[3] 1479 */ 1480 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_15_MASK 0x70000000 1481 #define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_15_SHIFT 28 1482 1483 /**** serdes_mux_multi_1 register ****/ 1484 /* SerDes one hot mux control. For details see datasheet. */ 1485 #define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_A_0_MASK 0x00000003 1486 #define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_A_0_SHIFT 0 1487 /* Reserved */ 1488 #define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_3_2_MASK 0x0000000C 1489 #define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_3_2_SHIFT 2 1490 /* SerDes one hot mux control. For details see datasheet. */ 1491 #define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_B_0_MASK 0x00000070 1492 #define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_B_0_SHIFT 4 1493 /* Reserved */ 1494 #define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_7 (1 << 7) 1495 /* SerDes one hot mux control. For details see datasheet. */ 1496 #define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_C_0_MASK 0x00000300 1497 #define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_C_0_SHIFT 8 1498 /* Reserved */ 1499 #define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_11_10_MASK 0x00000C00 1500 #define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_11_10_SHIFT 10 1501 /* SerDes one hot mux control. For details see datasheet. */ 1502 #define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_D_0_MASK 0x00007000 1503 #define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_D_0_SHIFT 12 1504 /* Reserved */ 1505 #define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_MASK 0xFFFF8000 1506 #define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_SHIFT 15 1507 1508 /**** pbs_ulpi_mux_conf register ****/ 1509 /* 1510 * Value 0 - Select dedicated pins for the USB-1 inputs. 1511 * Value 1 - Select PBS mux pins for the USB-1 inputs. 1512 * [0] ULPI_B_CLK 1513 * [1] ULPI_B_DIR 1514 * [2] ULPI_B_NXT 1515 * [10:3] ULPI_B_DATA[7:0] 1516 */ 1517 #define PBS_UNIT_PBS_ULPI_MUX_CONF_SEL_UPLI_IN_PBSMUX_MASK 0x000007FF 1518 #define PBS_UNIT_PBS_ULPI_MUX_CONF_SEL_UPLI_IN_PBSMUX_SHIFT 0 1519 /* 1520 * [3] - Force to zero 1521 * [2] == 1 - Force register selection 1522 * [1 : 0] -Binary selection of the input in bypass mode 1523 */ 1524 #define PBS_UNIT_PBS_ULPI_MUX_CONF_REG_MDIO_BYPASS_SEL_MASK 0x0000F000 1525 #define PBS_UNIT_PBS_ULPI_MUX_CONF_REG_MDIO_BYPASS_SEL_SHIFT 12 1526 /* 1527 * [0] Sets the clk_ulpi OE for USB0, 1'b0 set to input, 1'b1 set to output. 1528 * [1] Sets the clk_ulpi OE for USB01, 1'b0 set to input, 1'b1 set to output. 1529 */ 1530 #define PBS_UNIT_PBS_ULPI_MUX_CONF_RSRVD_MASK 0xFFFF0000 1531 #define PBS_UNIT_PBS_ULPI_MUX_CONF_RSRVD_SHIFT 16 1532 1533 /**** wr_once_dbg_dis_ovrd_reg register ****/ 1534 /* This register can be written only once. Use in the secure boot process. */ 1535 #define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_WR_ONCE_DBG_DIS_OVRD (1 << 0) 1536 1537 #define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_RSRVD_MASK 0xFFFFFFFE 1538 #define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_RSRVD_SHIFT 1 1539 1540 /**** gpio5_conf_status register ****/ 1541 /* 1542 * Cntl: // [7:0] nGPAFEN; // from regfile // [15:8] GPAFOUT; // from regfile 1543 */ 1544 #define PBS_UNIT_GPIO5_CONF_STATUS_CONF_MASK 0x0000FFFF 1545 #define PBS_UNIT_GPIO5_CONF_STATUS_CONF_SHIFT 0 1546 /* Status: // [24:16] GPAFIN; // to regfile */ 1547 #define PBS_UNIT_GPIO5_CONF_STATUS_STATUS_MASK 0xFFFF0000 1548 #define PBS_UNIT_GPIO5_CONF_STATUS_STATUS_SHIFT 16 1549 1550 /**** pcie_mem3_bar_low register ****/ 1551 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1552 #define PBS_UNIT_PCIE_MEM3_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1553 #define PBS_UNIT_PCIE_MEM3_BAR_LOW_WIN_SIZE_SHIFT 0 1554 /* Reserved fields */ 1555 #define PBS_UNIT_PCIE_MEM3_BAR_LOW_RSRVD_MASK 0x0000FFC0 1556 #define PBS_UNIT_PCIE_MEM3_BAR_LOW_RSRVD_SHIFT 6 1557 /* Reserved */ 1558 #define PBS_UNIT_PCIE_MEM3_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1559 #define PBS_UNIT_PCIE_MEM3_BAR_LOW_ADDR_HIGH_SHIFT 16 1560 1561 /**** pcie_mem4_bar_low register ****/ 1562 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1563 #define PBS_UNIT_PCIE_MEM4_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1564 #define PBS_UNIT_PCIE_MEM4_BAR_LOW_WIN_SIZE_SHIFT 0 1565 /* Reserved fields */ 1566 #define PBS_UNIT_PCIE_MEM4_BAR_LOW_RSRVD_MASK 0x0000FFC0 1567 #define PBS_UNIT_PCIE_MEM4_BAR_LOW_RSRVD_SHIFT 6 1568 /* Reserved */ 1569 #define PBS_UNIT_PCIE_MEM4_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1570 #define PBS_UNIT_PCIE_MEM4_BAR_LOW_ADDR_HIGH_SHIFT 16 1571 1572 /**** pcie_mem5_bar_low register ****/ 1573 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1574 #define PBS_UNIT_PCIE_MEM5_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1575 #define PBS_UNIT_PCIE_MEM5_BAR_LOW_WIN_SIZE_SHIFT 0 1576 /* Reserved fields */ 1577 #define PBS_UNIT_PCIE_MEM5_BAR_LOW_RSRVD_MASK 0x0000FFC0 1578 #define PBS_UNIT_PCIE_MEM5_BAR_LOW_RSRVD_SHIFT 6 1579 /* Reserved */ 1580 #define PBS_UNIT_PCIE_MEM5_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1581 #define PBS_UNIT_PCIE_MEM5_BAR_LOW_ADDR_HIGH_SHIFT 16 1582 1583 /**** pcie_ext_ecam3_bar_low register ****/ 1584 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1585 #define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1586 #define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_WIN_SIZE_SHIFT 0 1587 /* Reserved fields */ 1588 #define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_RSRVD_MASK 0x0000FFC0 1589 #define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_RSRVD_SHIFT 6 1590 /* Reserved */ 1591 #define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1592 #define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_ADDR_HIGH_SHIFT 16 1593 1594 /**** pcie_ext_ecam4_bar_low register ****/ 1595 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1596 #define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1597 #define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_WIN_SIZE_SHIFT 0 1598 /* Reserved fields */ 1599 #define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_RSRVD_MASK 0x0000FFC0 1600 #define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_RSRVD_SHIFT 6 1601 /* Reserved */ 1602 #define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1603 #define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_ADDR_HIGH_SHIFT 16 1604 1605 /**** pcie_ext_ecam5_bar_low register ****/ 1606 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1607 #define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1608 #define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_WIN_SIZE_SHIFT 0 1609 /* Reserved fields */ 1610 #define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_RSRVD_MASK 0x0000FFC0 1611 #define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_RSRVD_SHIFT 6 1612 /* Reserved */ 1613 #define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1614 #define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_ADDR_HIGH_SHIFT 16 1615 1616 /**** low_latency_sram_bar_low register ****/ 1617 /* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1618 #define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1619 #define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_WIN_SIZE_SHIFT 0 1620 /* Reserved fields */ 1621 #define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_RSRVD_MASK 0x0000FFC0 1622 #define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_RSRVD_SHIFT 6 1623 /* Reserved */ 1624 #define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1625 #define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_ADDR_HIGH_SHIFT 16 1626 1627 /**** pbs_sb2nb_cfg_dram_remap register ****/ 1628 #define PBS_UNIT_SB2NB_REMAP_BASE_ADDR_SHIFT 5 1629 #define PBS_UNIT_SB2NB_REMAP_BASE_ADDR_MASK 0x0000FFE0 1630 #define PBS_UNIT_SB2NB_REMAP_TRANSL_BASE_ADDR_SHIFT 21 1631 #define PBS_UNIT_SB2NB_REMAP_TRANSL_BASE_ADDR_MASK 0xFFE00000 1632 1633 /* For remapping are used bits [39 - 29] of DRAM 40bit Physical address */ 1634 #define PBS_UNIT_DRAM_SRC_REMAP_BASE_ADDR_SHIFT 29 1635 #define PBS_UNIT_DRAM_DST_REMAP_BASE_ADDR_SHIFT 29 1636 #define PBS_UNIT_DRAM_REMAP_BASE_ADDR_MASK 0xFFE0000000UL 1637 1638 1639 /**** serdes_mux_eth register ****/ 1640 /* 1641 * 2'b01 - eth_a[0] from serdes_8 1642 * 2'b10 - eth_a[0] from serdes_14 1643 */ 1644 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_0_MASK 0x00000003 1645 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_0_SHIFT 0 1646 /* 1647 * 2'b01 - eth_b[0] from serdes_9 1648 * 2'b10 - eth_b[0] from serdes_13 1649 */ 1650 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_B_0_MASK 0x00000030 1651 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_B_0_SHIFT 4 1652 /* 1653 * 2'b01 - eth_c[0] from serdes_10 1654 * 2'b10 - eth_c[0] from serdes_12 1655 */ 1656 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_0_MASK 0x00000300 1657 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_0_SHIFT 8 1658 /* 1659 * 2'b01 - eth_d[0] from serdes_11 1660 * 2'b10 - eth_d[0] from serdes_15 1661 */ 1662 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_D_0_MASK 0x00003000 1663 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_D_0_SHIFT 12 1664 /* which lane's is master clk */ 1665 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_ICK_MASTER_MASK 0x00030000 1666 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_ICK_MASTER_SHIFT 16 1667 /* which lane's is master clk */ 1668 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_ICK_MASTER_MASK 0x00300000 1669 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_ICK_MASTER_SHIFT 20 1670 /* enable xlaui on eth a */ 1671 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_XLAUI_ENABLE (1 << 24) 1672 /* enable xlaui on eth c */ 1673 #define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_XLAUI_ENABLE (1 << 28) 1674 1675 /**** serdes_mux_pcie register ****/ 1676 /* 1677 * 2'b01 - select pcie_b[0] from serdes 2 1678 * 2'b10 - select pcie_b[0] from serdes 4 1679 */ 1680 #define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_B_0_MASK 0x00000003 1681 #define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_B_0_SHIFT 0 1682 /* 1683 * 2'b01 - select pcie_b[1] from serdes 3 1684 * 2'b10 - select pcie_b[1] from serdes 5 1685 */ 1686 #define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_B_1_MASK 0x00000030 1687 #define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_B_1_SHIFT 4 1688 /* 1689 * 2'b01 - select pcie_d[0] from serdes 10 1690 * 2'b10 - select pcie_d[0] from serdes 12 1691 */ 1692 #define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_D_0_MASK 0x00000300 1693 #define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_D_0_SHIFT 8 1694 /* 1695 * 2'b01 - select pcie_d[1] from serdes 11 1696 * 2'b10 - select pcie_d[1] from serdes 13 1697 */ 1698 #define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_D_1_MASK 0x00003000 1699 #define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_D_1_SHIFT 12 1700 1701 /**** serdes_mux_sata register ****/ 1702 /* 1703 * 2'b01 - select sata_a from serdes group 1 1704 * 2'b10 - select sata_a from serdes group 3 1705 */ 1706 #define PBS_UNIT_SERDES_MUX_SATA_SELECT_OH_SATA_A_MASK 0x00000003 1707 #define PBS_UNIT_SERDES_MUX_SATA_SELECT_OH_SATA_A_SHIFT 0 1708 /* Reserved */ 1709 #define PBS_UNIT_SERDES_MUX_SATA_RESERVED_3_2_MASK 0x0000000C 1710 #define PBS_UNIT_SERDES_MUX_SATA_RESERVED_3_2_SHIFT 2 1711 /* Reserved */ 1712 #define PBS_UNIT_SERDES_MUX_SATA_RESERVED_MASK 0xFFFFFFF0 1713 #define PBS_UNIT_SERDES_MUX_SATA_RESERVED_SHIFT 4 1714 1715 /**** bar1_orig register ****/ 1716 /* 1717 * Window size = 2 ^ (11 + win_size). 1718 * Zero value: disable the window. 1719 */ 1720 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_WIN_SIZE_MASK 0x00000007 1721 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_WIN_SIZE_SHIFT 0 1722 /* Reserved fields */ 1723 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_RSRVD_MASK 0x00000FF8 1724 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_RSRVD_SHIFT 3 1725 /* 1726 * offset within the SRAM, in resolution of 4KB. 1727 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1728 */ 1729 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1730 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_ADDR_HIGH_SHIFT 12 1731 1732 /**** bar1_remap register ****/ 1733 /* Reserved fields */ 1734 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_RSRVD_MASK 0x00000FFF 1735 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_RSRVD_SHIFT 0 1736 /* remapped address */ 1737 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1738 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_ADDR_HIGH_SHIFT 12 1739 1740 /**** bar2_orig register ****/ 1741 /* 1742 * Window size = 2 ^ (11 + win_size). 1743 * Zero value: disable the window. 1744 */ 1745 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_WIN_SIZE_MASK 0x00000007 1746 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_WIN_SIZE_SHIFT 0 1747 /* Reserved fields */ 1748 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_RSRVD_MASK 0x00000FF8 1749 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_RSRVD_SHIFT 3 1750 /* 1751 * offset within the SRAM, in resolution of 4KB. 1752 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1753 */ 1754 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1755 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_ADDR_HIGH_SHIFT 12 1756 1757 /**** bar2_remap register ****/ 1758 /* Reserved fields */ 1759 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_RSRVD_MASK 0x00000FFF 1760 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_RSRVD_SHIFT 0 1761 /* remapped address */ 1762 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1763 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_ADDR_HIGH_SHIFT 12 1764 1765 /**** bar3_orig register ****/ 1766 /* 1767 * Window size = 2 ^ (11 + win_size). 1768 * Zero value: disable the window. 1769 */ 1770 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_WIN_SIZE_MASK 0x00000007 1771 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_WIN_SIZE_SHIFT 0 1772 /* Reserved fields */ 1773 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_RSRVD_MASK 0x00000FF8 1774 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_RSRVD_SHIFT 3 1775 /* 1776 * offset within the SRAM, in resolution of 4KB. 1777 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1778 */ 1779 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1780 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_ADDR_HIGH_SHIFT 12 1781 1782 /**** bar3_remap register ****/ 1783 /* Reserved fields */ 1784 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_RSRVD_MASK 0x00000FFF 1785 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_RSRVD_SHIFT 0 1786 /* remapped address */ 1787 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1788 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_ADDR_HIGH_SHIFT 12 1789 1790 /**** bar4_orig register ****/ 1791 /* 1792 * Window size = 2 ^ (11 + win_size). 1793 * Zero value: disable the window. 1794 */ 1795 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_WIN_SIZE_MASK 0x00000007 1796 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_WIN_SIZE_SHIFT 0 1797 /* Reserved fields */ 1798 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_RSRVD_MASK 0x00000FF8 1799 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_RSRVD_SHIFT 3 1800 /* 1801 * offset within the SRAM, in resolution of 4KB. 1802 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1803 */ 1804 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1805 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_ADDR_HIGH_SHIFT 12 1806 1807 /**** bar4_remap register ****/ 1808 /* Reserved fields */ 1809 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_RSRVD_MASK 0x00000FFF 1810 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_RSRVD_SHIFT 0 1811 /* remapped address */ 1812 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1813 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_ADDR_HIGH_SHIFT 12 1814 1815 /**** bar5_orig register ****/ 1816 /* 1817 * Window size = 2 ^ (11 + win_size). 1818 * Zero value: disable the window. 1819 */ 1820 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_WIN_SIZE_MASK 0x00000007 1821 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_WIN_SIZE_SHIFT 0 1822 /* Reserved fields */ 1823 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_RSRVD_MASK 0x00000FF8 1824 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_RSRVD_SHIFT 3 1825 /* 1826 * offset within the SRAM, in resolution of 4KB. 1827 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1828 */ 1829 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1830 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_ADDR_HIGH_SHIFT 12 1831 1832 /**** bar5_remap register ****/ 1833 /* Reserved fields */ 1834 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_RSRVD_MASK 0x00000FFF 1835 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_RSRVD_SHIFT 0 1836 /* remapped address */ 1837 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1838 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_ADDR_HIGH_SHIFT 12 1839 1840 /**** bar6_orig register ****/ 1841 /* 1842 * Window size = 2 ^ (11 + win_size). 1843 * Zero value: disable the window. 1844 */ 1845 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_WIN_SIZE_MASK 0x00000007 1846 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_WIN_SIZE_SHIFT 0 1847 /* Reserved fields */ 1848 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_RSRVD_MASK 0x00000FF8 1849 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_RSRVD_SHIFT 3 1850 /* 1851 * offset within the SRAM, in resolution of 4KB. 1852 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1853 */ 1854 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1855 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_ADDR_HIGH_SHIFT 12 1856 1857 /**** bar6_remap register ****/ 1858 /* Reserved fields */ 1859 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_RSRVD_MASK 0x00000FFF 1860 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_RSRVD_SHIFT 0 1861 /* remapped address */ 1862 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1863 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_ADDR_HIGH_SHIFT 12 1864 1865 /**** bar7_orig register ****/ 1866 /* 1867 * Window size = 2 ^ (11 + win_size). 1868 * Zero value: disable the window. 1869 */ 1870 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_WIN_SIZE_MASK 0x00000007 1871 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_WIN_SIZE_SHIFT 0 1872 /* Reserved fields */ 1873 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_RSRVD_MASK 0x00000FF8 1874 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_RSRVD_SHIFT 3 1875 /* 1876 * offset within the SRAM, in resolution of 4KB. 1877 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1878 */ 1879 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1880 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_ADDR_HIGH_SHIFT 12 1881 1882 /**** bar7_remap register ****/ 1883 /* Reserved fields */ 1884 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_RSRVD_MASK 0x00000FFF 1885 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_RSRVD_SHIFT 0 1886 /* remapped address */ 1887 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1888 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_ADDR_HIGH_SHIFT 12 1889 1890 /**** bar8_orig register ****/ 1891 /* 1892 * Window size = 2 ^ (11 + win_size). 1893 * Zero value: disable the window. 1894 */ 1895 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_WIN_SIZE_MASK 0x00000007 1896 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_WIN_SIZE_SHIFT 0 1897 /* Reserved fields */ 1898 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_RSRVD_MASK 0x00000FF8 1899 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_RSRVD_SHIFT 3 1900 /* 1901 * offset within the SRAM, in resolution of 4KB. 1902 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1903 */ 1904 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1905 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_ADDR_HIGH_SHIFT 12 1906 1907 /**** bar8_remap register ****/ 1908 /* Reserved fields */ 1909 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_RSRVD_MASK 0x00000FFF 1910 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_RSRVD_SHIFT 0 1911 /* remapped address */ 1912 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1913 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_ADDR_HIGH_SHIFT 12 1914 1915 /**** bar9_orig register ****/ 1916 /* 1917 * Window size = 2 ^ (11 + win_size). 1918 * Zero value: disable the window. 1919 */ 1920 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_WIN_SIZE_MASK 0x00000007 1921 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_WIN_SIZE_SHIFT 0 1922 /* Reserved fields */ 1923 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_RSRVD_MASK 0x00000FF8 1924 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_RSRVD_SHIFT 3 1925 /* 1926 * offset within the SRAM, in resolution of 4KB. 1927 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1928 */ 1929 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1930 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_ADDR_HIGH_SHIFT 12 1931 1932 /**** bar9_remap register ****/ 1933 /* Reserved fields */ 1934 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_RSRVD_MASK 0x00000FFF 1935 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_RSRVD_SHIFT 0 1936 /* remapped address */ 1937 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1938 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_ADDR_HIGH_SHIFT 12 1939 1940 /**** bar10_orig register ****/ 1941 /* 1942 * Window size = 2 ^ (11 + win_size). 1943 * Zero value: disable the window. 1944 */ 1945 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_WIN_SIZE_MASK 0x00000007 1946 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_WIN_SIZE_SHIFT 0 1947 /* Reserved fields */ 1948 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_RSRVD_MASK 0x00000FF8 1949 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_RSRVD_SHIFT 3 1950 /* 1951 * offset within the SRAM, in resolution of 4KB. 1952 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1953 */ 1954 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1955 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_ADDR_HIGH_SHIFT 12 1956 1957 /**** bar10_remap register ****/ 1958 /* Reserved fields */ 1959 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_RSRVD_MASK 0x00000FFF 1960 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_RSRVD_SHIFT 0 1961 /* remapped address */ 1962 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1963 #define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_ADDR_HIGH_SHIFT 12 1964 1965 /**** cpu register ****/ 1966 /* map transactions according to address decoding */ 1967 #define PBS_TARGET_ID_ENFORCEMENT_CPU_NO_ENFORCEMENT_MASK 0x0000000F 1968 #define PBS_TARGET_ID_ENFORCEMENT_CPU_NO_ENFORCEMENT_SHIFT 0 1969 /* map transactions to pcie_0 */ 1970 #define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_0_MASK 0x000000F0 1971 #define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_0_SHIFT 4 1972 /* map transactions to pcie_1 */ 1973 #define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_1_MASK 0x00000F00 1974 #define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_1_SHIFT 8 1975 /* map transactions to pcie_2 */ 1976 #define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_2_MASK 0x0000F000 1977 #define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_2_SHIFT 12 1978 /* map transactions to pcie_3 */ 1979 #define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_3_MASK 0x000F0000 1980 #define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_3_SHIFT 16 1981 /* map transactions to pcie_4 */ 1982 #define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_4_MASK 0x00F00000 1983 #define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_4_SHIFT 20 1984 /* map transactions to pcie_5 */ 1985 #define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_5_MASK 0x0F000000 1986 #define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_5_SHIFT 24 1987 /* map transactions to dram */ 1988 #define PBS_TARGET_ID_ENFORCEMENT_CPU_DRAM_MASK 0xF0000000 1989 #define PBS_TARGET_ID_ENFORCEMENT_CPU_DRAM_SHIFT 28 1990 1991 /**** cpu_mask register ****/ 1992 /* map transactions according to address decoding */ 1993 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_NO_ENFORCEMENT_MASK 0x0000000F 1994 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_NO_ENFORCEMENT_SHIFT 0 1995 /* map transactions to pcie_0 */ 1996 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_0_MASK 0x000000F0 1997 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_0_SHIFT 4 1998 /* map transactions to pcie_1 */ 1999 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_1_MASK 0x00000F00 2000 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_1_SHIFT 8 2001 /* map transactions to pcie_2 */ 2002 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_2_MASK 0x0000F000 2003 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_2_SHIFT 12 2004 /* map transactions to pcie_3 */ 2005 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_3_MASK 0x000F0000 2006 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_3_SHIFT 16 2007 /* map transactions to pcie_4 */ 2008 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_4_MASK 0x00F00000 2009 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_4_SHIFT 20 2010 /* map transactions to pcie_5 */ 2011 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_5_MASK 0x0F000000 2012 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_5_SHIFT 24 2013 /* map transactions to dram */ 2014 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_DRAM_MASK 0xF0000000 2015 #define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_DRAM_SHIFT 28 2016 2017 /**** debug_nb register ****/ 2018 /* map transactions according to address decoding */ 2019 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_NO_ENFORCEMENT_MASK 0x0000000F 2020 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_NO_ENFORCEMENT_SHIFT 0 2021 /* map transactions to pcie_0 */ 2022 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_0_MASK 0x000000F0 2023 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_0_SHIFT 4 2024 /* map transactions to pcie_1 */ 2025 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_1_MASK 0x00000F00 2026 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_1_SHIFT 8 2027 /* map transactions to pcie_2 */ 2028 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_2_MASK 0x0000F000 2029 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_2_SHIFT 12 2030 /* map transactions to pcie_3 */ 2031 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_3_MASK 0x000F0000 2032 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_3_SHIFT 16 2033 /* map transactions to pcie_4 */ 2034 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_4_MASK 0x00F00000 2035 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_4_SHIFT 20 2036 /* map transactions to pcie_5 */ 2037 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_5_MASK 0x0F000000 2038 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_5_SHIFT 24 2039 /* map transactions to dram */ 2040 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_DRAM_MASK 0xF0000000 2041 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_DRAM_SHIFT 28 2042 2043 /**** debug_nb_mask register ****/ 2044 /* map transactions according to address decoding */ 2045 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2046 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_NO_ENFORCEMENT_SHIFT 0 2047 /* map transactions to pcie_0 */ 2048 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_0_MASK 0x000000F0 2049 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_0_SHIFT 4 2050 /* map transactions to pcie_1 */ 2051 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_1_MASK 0x00000F00 2052 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_1_SHIFT 8 2053 /* map transactions to pcie_2 */ 2054 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_2_MASK 0x0000F000 2055 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_2_SHIFT 12 2056 /* map transactions to pcie_3 */ 2057 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_3_MASK 0x000F0000 2058 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_3_SHIFT 16 2059 /* map transactions to pcie_4 */ 2060 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_4_MASK 0x00F00000 2061 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_4_SHIFT 20 2062 /* map transactions to pcie_5 */ 2063 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_5_MASK 0x0F000000 2064 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_5_SHIFT 24 2065 /* map transactions to dram */ 2066 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_DRAM_MASK 0xF0000000 2067 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_DRAM_SHIFT 28 2068 2069 /**** debug_sb register ****/ 2070 /* map transactions according to address decoding */ 2071 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_NO_ENFORCEMENT_MASK 0x0000000F 2072 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_NO_ENFORCEMENT_SHIFT 0 2073 /* map transactions to pcie_0 */ 2074 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_0_MASK 0x000000F0 2075 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_0_SHIFT 4 2076 /* map transactions to pcie_1 */ 2077 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_1_MASK 0x00000F00 2078 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_1_SHIFT 8 2079 /* map transactions to pcie_2 */ 2080 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_2_MASK 0x0000F000 2081 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_2_SHIFT 12 2082 /* map transactions to pcie_3 */ 2083 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_3_MASK 0x000F0000 2084 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_3_SHIFT 16 2085 /* map transactions to pcie_4 */ 2086 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_4_MASK 0x00F00000 2087 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_4_SHIFT 20 2088 /* map transactions to pcie_5 */ 2089 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_5_MASK 0x0F000000 2090 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_5_SHIFT 24 2091 /* map transactions to dram */ 2092 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_DRAM_MASK 0xF0000000 2093 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_DRAM_SHIFT 28 2094 2095 /**** debug_sb_mask register ****/ 2096 /* map transactions according to address decoding */ 2097 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2098 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_NO_ENFORCEMENT_SHIFT 0 2099 /* map transactions to pcie_0 */ 2100 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_0_MASK 0x000000F0 2101 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_0_SHIFT 4 2102 /* map transactions to pcie_1 */ 2103 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_1_MASK 0x00000F00 2104 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_1_SHIFT 8 2105 /* map transactions to pcie_2 */ 2106 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_2_MASK 0x0000F000 2107 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_2_SHIFT 12 2108 /* map transactions to pcie_3 */ 2109 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_3_MASK 0x000F0000 2110 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_3_SHIFT 16 2111 /* map transactions to pcie_4 */ 2112 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_4_MASK 0x00F00000 2113 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_4_SHIFT 20 2114 /* map transactions to pcie_5 */ 2115 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_5_MASK 0x0F000000 2116 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_5_SHIFT 24 2117 /* map transactions to dram */ 2118 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_DRAM_MASK 0xF0000000 2119 #define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_DRAM_SHIFT 28 2120 2121 /**** eth_0 register ****/ 2122 /* map transactions according to address decoding */ 2123 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_NO_ENFORCEMENT_MASK 0x0000000F 2124 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_NO_ENFORCEMENT_SHIFT 0 2125 /* map transactions to pcie_0 */ 2126 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_0_MASK 0x000000F0 2127 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_0_SHIFT 4 2128 /* map transactions to pcie_1 */ 2129 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_1_MASK 0x00000F00 2130 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_1_SHIFT 8 2131 /* map transactions to pcie_2 */ 2132 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_2_MASK 0x0000F000 2133 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_2_SHIFT 12 2134 /* map transactions to pcie_3 */ 2135 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_3_MASK 0x000F0000 2136 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_3_SHIFT 16 2137 /* map transactions to pcie_4 */ 2138 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_4_MASK 0x00F00000 2139 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_4_SHIFT 20 2140 /* map transactions to pcie_5 */ 2141 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_5_MASK 0x0F000000 2142 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_5_SHIFT 24 2143 /* map transactions to dram */ 2144 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_DRAM_MASK 0xF0000000 2145 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_DRAM_SHIFT 28 2146 2147 /**** eth_0_mask register ****/ 2148 /* map transactions according to address decoding */ 2149 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2150 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_NO_ENFORCEMENT_SHIFT 0 2151 /* map transactions to pcie_0 */ 2152 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_0_MASK 0x000000F0 2153 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_0_SHIFT 4 2154 /* map transactions to pcie_1 */ 2155 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_1_MASK 0x00000F00 2156 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_1_SHIFT 8 2157 /* map transactions to pcie_2 */ 2158 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_2_MASK 0x0000F000 2159 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_2_SHIFT 12 2160 /* map transactions to pcie_3 */ 2161 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_3_MASK 0x000F0000 2162 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_3_SHIFT 16 2163 /* map transactions to pcie_4 */ 2164 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_4_MASK 0x00F00000 2165 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_4_SHIFT 20 2166 /* map transactions to pcie_5 */ 2167 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_5_MASK 0x0F000000 2168 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_5_SHIFT 24 2169 /* map transactions to dram */ 2170 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_DRAM_MASK 0xF0000000 2171 #define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_DRAM_SHIFT 28 2172 2173 /**** eth_1 register ****/ 2174 /* map transactions according to address decoding */ 2175 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_NO_ENFORCEMENT_MASK 0x0000000F 2176 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_NO_ENFORCEMENT_SHIFT 0 2177 /* map transactions to pcie_0 */ 2178 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_0_MASK 0x000000F0 2179 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_0_SHIFT 4 2180 /* map transactions to pcie_1 */ 2181 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_1_MASK 0x00000F00 2182 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_1_SHIFT 8 2183 /* map transactions to pcie_2 */ 2184 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_2_MASK 0x0000F000 2185 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_2_SHIFT 12 2186 /* map transactions to pcie_3 */ 2187 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_3_MASK 0x000F0000 2188 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_3_SHIFT 16 2189 /* map transactions to pcie_4 */ 2190 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_4_MASK 0x00F00000 2191 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_4_SHIFT 20 2192 /* map transactions to pcie_5 */ 2193 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_5_MASK 0x0F000000 2194 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_5_SHIFT 24 2195 /* map transactions to dram */ 2196 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_DRAM_MASK 0xF0000000 2197 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_DRAM_SHIFT 28 2198 2199 /**** eth_1_mask register ****/ 2200 /* map transactions according to address decoding */ 2201 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2202 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_NO_ENFORCEMENT_SHIFT 0 2203 /* map transactions to pcie_0 */ 2204 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_0_MASK 0x000000F0 2205 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_0_SHIFT 4 2206 /* map transactions to pcie_1 */ 2207 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_1_MASK 0x00000F00 2208 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_1_SHIFT 8 2209 /* map transactions to pcie_2 */ 2210 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_2_MASK 0x0000F000 2211 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_2_SHIFT 12 2212 /* map transactions to pcie_3 */ 2213 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_3_MASK 0x000F0000 2214 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_3_SHIFT 16 2215 /* map transactions to pcie_4 */ 2216 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_4_MASK 0x00F00000 2217 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_4_SHIFT 20 2218 /* map transactions to pcie_5 */ 2219 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_5_MASK 0x0F000000 2220 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_5_SHIFT 24 2221 /* map transactions to dram */ 2222 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_DRAM_MASK 0xF0000000 2223 #define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_DRAM_SHIFT 28 2224 2225 /**** eth_2 register ****/ 2226 /* map transactions according to address decoding */ 2227 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_NO_ENFORCEMENT_MASK 0x0000000F 2228 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_NO_ENFORCEMENT_SHIFT 0 2229 /* map transactions to pcie_0 */ 2230 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_0_MASK 0x000000F0 2231 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_0_SHIFT 4 2232 /* map transactions to pcie_1 */ 2233 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_1_MASK 0x00000F00 2234 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_1_SHIFT 8 2235 /* map transactions to pcie_2 */ 2236 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_2_MASK 0x0000F000 2237 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_2_SHIFT 12 2238 /* map transactions to pcie_3 */ 2239 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_3_MASK 0x000F0000 2240 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_3_SHIFT 16 2241 /* map transactions to pcie_4 */ 2242 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_4_MASK 0x00F00000 2243 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_4_SHIFT 20 2244 /* map transactions to pcie_5 */ 2245 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_5_MASK 0x0F000000 2246 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_5_SHIFT 24 2247 /* map transactions to dram */ 2248 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_DRAM_MASK 0xF0000000 2249 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_DRAM_SHIFT 28 2250 2251 /**** eth_2_mask register ****/ 2252 /* map transactions according to address decoding */ 2253 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2254 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_NO_ENFORCEMENT_SHIFT 0 2255 /* map transactions to pcie_0 */ 2256 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_0_MASK 0x000000F0 2257 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_0_SHIFT 4 2258 /* map transactions to pcie_1 */ 2259 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_1_MASK 0x00000F00 2260 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_1_SHIFT 8 2261 /* map transactions to pcie_2 */ 2262 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_2_MASK 0x0000F000 2263 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_2_SHIFT 12 2264 /* map transactions to pcie_3 */ 2265 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_3_MASK 0x000F0000 2266 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_3_SHIFT 16 2267 /* map transactions to pcie_4 */ 2268 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_4_MASK 0x00F00000 2269 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_4_SHIFT 20 2270 /* map transactions to pcie_5 */ 2271 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_5_MASK 0x0F000000 2272 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_5_SHIFT 24 2273 /* map transactions to dram */ 2274 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_DRAM_MASK 0xF0000000 2275 #define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_DRAM_SHIFT 28 2276 2277 /**** eth_3 register ****/ 2278 /* map transactions according to address decoding */ 2279 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_NO_ENFORCEMENT_MASK 0x0000000F 2280 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_NO_ENFORCEMENT_SHIFT 0 2281 /* map transactions to pcie_0 */ 2282 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_0_MASK 0x000000F0 2283 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_0_SHIFT 4 2284 /* map transactions to pcie_1 */ 2285 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_1_MASK 0x00000F00 2286 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_1_SHIFT 8 2287 /* map transactions to pcie_2 */ 2288 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_2_MASK 0x0000F000 2289 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_2_SHIFT 12 2290 /* map transactions to pcie_3 */ 2291 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_3_MASK 0x000F0000 2292 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_3_SHIFT 16 2293 /* map transactions to pcie_4 */ 2294 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_4_MASK 0x00F00000 2295 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_4_SHIFT 20 2296 /* map transactions to pcie_5 */ 2297 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_5_MASK 0x0F000000 2298 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_5_SHIFT 24 2299 /* map transactions to dram */ 2300 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_DRAM_MASK 0xF0000000 2301 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_DRAM_SHIFT 28 2302 2303 /**** eth_3_mask register ****/ 2304 /* map transactions according to address decoding */ 2305 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2306 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_NO_ENFORCEMENT_SHIFT 0 2307 /* map transactions to pcie_0 */ 2308 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_0_MASK 0x000000F0 2309 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_0_SHIFT 4 2310 /* map transactions to pcie_1 */ 2311 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_1_MASK 0x00000F00 2312 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_1_SHIFT 8 2313 /* map transactions to pcie_2 */ 2314 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_2_MASK 0x0000F000 2315 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_2_SHIFT 12 2316 /* map transactions to pcie_3 */ 2317 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_3_MASK 0x000F0000 2318 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_3_SHIFT 16 2319 /* map transactions to pcie_4 */ 2320 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_4_MASK 0x00F00000 2321 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_4_SHIFT 20 2322 /* map transactions to pcie_5 */ 2323 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_5_MASK 0x0F000000 2324 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_5_SHIFT 24 2325 /* map transactions to dram */ 2326 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_DRAM_MASK 0xF0000000 2327 #define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_DRAM_SHIFT 28 2328 2329 /**** sata_0 register ****/ 2330 /* map transactions according to address decoding */ 2331 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_NO_ENFORCEMENT_MASK 0x0000000F 2332 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_NO_ENFORCEMENT_SHIFT 0 2333 /* map transactions to pcie_0 */ 2334 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_0_MASK 0x000000F0 2335 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_0_SHIFT 4 2336 /* map transactions to pcie_1 */ 2337 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_1_MASK 0x00000F00 2338 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_1_SHIFT 8 2339 /* map transactions to pcie_2 */ 2340 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_2_MASK 0x0000F000 2341 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_2_SHIFT 12 2342 /* map transactions to pcie_3 */ 2343 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_3_MASK 0x000F0000 2344 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_3_SHIFT 16 2345 /* map transactions to pcie_4 */ 2346 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_4_MASK 0x00F00000 2347 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_4_SHIFT 20 2348 /* map transactions to pcie_5 */ 2349 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_5_MASK 0x0F000000 2350 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_5_SHIFT 24 2351 /* map transactions to dram */ 2352 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_DRAM_MASK 0xF0000000 2353 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_DRAM_SHIFT 28 2354 2355 /**** sata_0_mask register ****/ 2356 /* map transactions according to address decoding */ 2357 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2358 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_NO_ENFORCEMENT_SHIFT 0 2359 /* map transactions to pcie_0 */ 2360 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_0_MASK 0x000000F0 2361 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_0_SHIFT 4 2362 /* map transactions to pcie_1 */ 2363 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_1_MASK 0x00000F00 2364 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_1_SHIFT 8 2365 /* map transactions to pcie_2 */ 2366 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_2_MASK 0x0000F000 2367 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_2_SHIFT 12 2368 /* map transactions to pcie_3 */ 2369 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_3_MASK 0x000F0000 2370 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_3_SHIFT 16 2371 /* map transactions to pcie_4 */ 2372 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_4_MASK 0x00F00000 2373 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_4_SHIFT 20 2374 /* map transactions to pcie_5 */ 2375 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_5_MASK 0x0F000000 2376 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_5_SHIFT 24 2377 /* map transactions to dram */ 2378 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_DRAM_MASK 0xF0000000 2379 #define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_DRAM_SHIFT 28 2380 2381 /**** sata_1 register ****/ 2382 /* map transactions according to address decoding */ 2383 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_NO_ENFORCEMENT_MASK 0x0000000F 2384 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_NO_ENFORCEMENT_SHIFT 0 2385 /* map transactions to pcie_0 */ 2386 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_0_MASK 0x000000F0 2387 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_0_SHIFT 4 2388 /* map transactions to pcie_1 */ 2389 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_1_MASK 0x00000F00 2390 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_1_SHIFT 8 2391 /* map transactions to pcie_2 */ 2392 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_2_MASK 0x0000F000 2393 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_2_SHIFT 12 2394 /* map transactions to pcie_3 */ 2395 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_3_MASK 0x000F0000 2396 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_3_SHIFT 16 2397 /* map transactions to pcie_4 */ 2398 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_4_MASK 0x00F00000 2399 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_4_SHIFT 20 2400 /* map transactions to pcie_5 */ 2401 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_5_MASK 0x0F000000 2402 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_5_SHIFT 24 2403 /* map transactions to dram */ 2404 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_DRAM_MASK 0xF0000000 2405 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_DRAM_SHIFT 28 2406 2407 /**** sata_1_mask register ****/ 2408 /* map transactions according to address decoding */ 2409 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2410 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_NO_ENFORCEMENT_SHIFT 0 2411 /* map transactions to pcie_0 */ 2412 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_0_MASK 0x000000F0 2413 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_0_SHIFT 4 2414 /* map transactions to pcie_1 */ 2415 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_1_MASK 0x00000F00 2416 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_1_SHIFT 8 2417 /* map transactions to pcie_2 */ 2418 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_2_MASK 0x0000F000 2419 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_2_SHIFT 12 2420 /* map transactions to pcie_3 */ 2421 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_3_MASK 0x000F0000 2422 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_3_SHIFT 16 2423 /* map transactions to pcie_4 */ 2424 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_4_MASK 0x00F00000 2425 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_4_SHIFT 20 2426 /* map transactions to pcie_5 */ 2427 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_5_MASK 0x0F000000 2428 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_5_SHIFT 24 2429 /* map transactions to dram */ 2430 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_DRAM_MASK 0xF0000000 2431 #define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_DRAM_SHIFT 28 2432 2433 /**** crypto_0 register ****/ 2434 /* map transactions according to address decoding */ 2435 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_NO_ENFORCEMENT_MASK 0x0000000F 2436 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_NO_ENFORCEMENT_SHIFT 0 2437 /* map transactions to pcie_0 */ 2438 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_0_MASK 0x000000F0 2439 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_0_SHIFT 4 2440 /* map transactions to pcie_1 */ 2441 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_1_MASK 0x00000F00 2442 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_1_SHIFT 8 2443 /* map transactions to pcie_2 */ 2444 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_2_MASK 0x0000F000 2445 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_2_SHIFT 12 2446 /* map transactions to pcie_3 */ 2447 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_3_MASK 0x000F0000 2448 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_3_SHIFT 16 2449 /* map transactions to pcie_4 */ 2450 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_4_MASK 0x00F00000 2451 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_4_SHIFT 20 2452 /* map transactions to pcie_5 */ 2453 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_5_MASK 0x0F000000 2454 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_5_SHIFT 24 2455 /* map transactions to dram */ 2456 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_DRAM_MASK 0xF0000000 2457 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_DRAM_SHIFT 28 2458 2459 /**** crypto_0_mask register ****/ 2460 /* map transactions according to address decoding */ 2461 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2462 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_NO_ENFORCEMENT_SHIFT 0 2463 /* map transactions to pcie_0 */ 2464 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_0_MASK 0x000000F0 2465 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_0_SHIFT 4 2466 /* map transactions to pcie_1 */ 2467 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_1_MASK 0x00000F00 2468 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_1_SHIFT 8 2469 /* map transactions to pcie_2 */ 2470 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_2_MASK 0x0000F000 2471 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_2_SHIFT 12 2472 /* map transactions to pcie_3 */ 2473 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_3_MASK 0x000F0000 2474 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_3_SHIFT 16 2475 /* map transactions to pcie_4 */ 2476 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_4_MASK 0x00F00000 2477 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_4_SHIFT 20 2478 /* map transactions to pcie_5 */ 2479 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_5_MASK 0x0F000000 2480 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_5_SHIFT 24 2481 /* map transactions to dram */ 2482 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_DRAM_MASK 0xF0000000 2483 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_DRAM_SHIFT 28 2484 2485 /**** crypto_1 register ****/ 2486 /* map transactions according to address decoding */ 2487 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_NO_ENFORCEMENT_MASK 0x0000000F 2488 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_NO_ENFORCEMENT_SHIFT 0 2489 /* map transactions to pcie_0 */ 2490 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_0_MASK 0x000000F0 2491 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_0_SHIFT 4 2492 /* map transactions to pcie_1 */ 2493 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_1_MASK 0x00000F00 2494 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_1_SHIFT 8 2495 /* map transactions to pcie_2 */ 2496 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_2_MASK 0x0000F000 2497 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_2_SHIFT 12 2498 /* map transactions to pcie_3 */ 2499 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_3_MASK 0x000F0000 2500 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_3_SHIFT 16 2501 /* map transactions to pcie_4 */ 2502 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_4_MASK 0x00F00000 2503 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_4_SHIFT 20 2504 /* map transactions to pcie_5 */ 2505 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_5_MASK 0x0F000000 2506 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_5_SHIFT 24 2507 /* map transactions to dram */ 2508 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_DRAM_MASK 0xF0000000 2509 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_DRAM_SHIFT 28 2510 2511 /**** crypto_1_mask register ****/ 2512 /* map transactions according to address decoding */ 2513 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2514 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_NO_ENFORCEMENT_SHIFT 0 2515 /* map transactions to pcie_0 */ 2516 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_0_MASK 0x000000F0 2517 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_0_SHIFT 4 2518 /* map transactions to pcie_1 */ 2519 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_1_MASK 0x00000F00 2520 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_1_SHIFT 8 2521 /* map transactions to pcie_2 */ 2522 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_2_MASK 0x0000F000 2523 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_2_SHIFT 12 2524 /* map transactions to pcie_3 */ 2525 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_3_MASK 0x000F0000 2526 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_3_SHIFT 16 2527 /* map transactions to pcie_4 */ 2528 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_4_MASK 0x00F00000 2529 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_4_SHIFT 20 2530 /* map transactions to pcie_5 */ 2531 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_5_MASK 0x0F000000 2532 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_5_SHIFT 24 2533 /* map transactions to dram */ 2534 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_DRAM_MASK 0xF0000000 2535 #define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_DRAM_SHIFT 28 2536 2537 /**** pcie_0 register ****/ 2538 /* map transactions according to address decoding */ 2539 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_NO_ENFORCEMENT_MASK 0x0000000F 2540 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_NO_ENFORCEMENT_SHIFT 0 2541 /* map transactions to pcie_0 */ 2542 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_0_MASK 0x000000F0 2543 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_0_SHIFT 4 2544 /* map transactions to pcie_1 */ 2545 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_1_MASK 0x00000F00 2546 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_1_SHIFT 8 2547 /* map transactions to pcie_2 */ 2548 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_2_MASK 0x0000F000 2549 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_2_SHIFT 12 2550 /* map transactions to pcie_3 */ 2551 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_3_MASK 0x000F0000 2552 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_3_SHIFT 16 2553 /* map transactions to pcie_4 */ 2554 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_4_MASK 0x00F00000 2555 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_4_SHIFT 20 2556 /* map transactions to pcie_5 */ 2557 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_5_MASK 0x0F000000 2558 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_5_SHIFT 24 2559 /* map transactions to dram */ 2560 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_DRAM_MASK 0xF0000000 2561 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_DRAM_SHIFT 28 2562 2563 /**** pcie_0_mask register ****/ 2564 /* map transactions according to address decoding */ 2565 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2566 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_NO_ENFORCEMENT_SHIFT 0 2567 /* map transactions to pcie_0 */ 2568 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_0_MASK 0x000000F0 2569 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_0_SHIFT 4 2570 /* map transactions to pcie_1 */ 2571 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_1_MASK 0x00000F00 2572 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_1_SHIFT 8 2573 /* map transactions to pcie_2 */ 2574 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_2_MASK 0x0000F000 2575 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_2_SHIFT 12 2576 /* map transactions to pcie_3 */ 2577 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_3_MASK 0x000F0000 2578 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_3_SHIFT 16 2579 /* map transactions to pcie_4 */ 2580 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_4_MASK 0x00F00000 2581 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_4_SHIFT 20 2582 /* map transactions to pcie_5 */ 2583 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_5_MASK 0x0F000000 2584 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_5_SHIFT 24 2585 /* map transactions to dram */ 2586 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_DRAM_MASK 0xF0000000 2587 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_DRAM_SHIFT 28 2588 2589 /**** pcie_1 register ****/ 2590 /* map transactions according to address decoding */ 2591 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_NO_ENFORCEMENT_MASK 0x0000000F 2592 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_NO_ENFORCEMENT_SHIFT 0 2593 /* map transactions to pcie_0 */ 2594 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_0_MASK 0x000000F0 2595 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_0_SHIFT 4 2596 /* map transactions to pcie_1 */ 2597 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_1_MASK 0x00000F00 2598 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_1_SHIFT 8 2599 /* map transactions to pcie_2 */ 2600 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_2_MASK 0x0000F000 2601 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_2_SHIFT 12 2602 /* map transactions to pcie_3 */ 2603 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_3_MASK 0x000F0000 2604 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_3_SHIFT 16 2605 /* map transactions to pcie_4 */ 2606 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_4_MASK 0x00F00000 2607 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_4_SHIFT 20 2608 /* map transactions to pcie_5 */ 2609 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_5_MASK 0x0F000000 2610 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_5_SHIFT 24 2611 /* map transactions to dram */ 2612 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_DRAM_MASK 0xF0000000 2613 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_DRAM_SHIFT 28 2614 2615 /**** pcie_1_mask register ****/ 2616 /* map transactions according to address decoding */ 2617 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2618 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_NO_ENFORCEMENT_SHIFT 0 2619 /* map transactions to pcie_0 */ 2620 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_0_MASK 0x000000F0 2621 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_0_SHIFT 4 2622 /* map transactions to pcie_1 */ 2623 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_1_MASK 0x00000F00 2624 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_1_SHIFT 8 2625 /* map transactions to pcie_2 */ 2626 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_2_MASK 0x0000F000 2627 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_2_SHIFT 12 2628 /* map transactions to pcie_3 */ 2629 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_3_MASK 0x000F0000 2630 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_3_SHIFT 16 2631 /* map transactions to pcie_4 */ 2632 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_4_MASK 0x00F00000 2633 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_4_SHIFT 20 2634 /* map transactions to pcie_5 */ 2635 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_5_MASK 0x0F000000 2636 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_5_SHIFT 24 2637 /* map transactions to dram */ 2638 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_DRAM_MASK 0xF0000000 2639 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_DRAM_SHIFT 28 2640 2641 /**** pcie_2 register ****/ 2642 /* map transactions according to address decoding */ 2643 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_NO_ENFORCEMENT_MASK 0x0000000F 2644 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_NO_ENFORCEMENT_SHIFT 0 2645 /* map transactions to pcie_0 */ 2646 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_0_MASK 0x000000F0 2647 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_0_SHIFT 4 2648 /* map transactions to pcie_1 */ 2649 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_1_MASK 0x00000F00 2650 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_1_SHIFT 8 2651 /* map transactions to pcie_2 */ 2652 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_2_MASK 0x0000F000 2653 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_2_SHIFT 12 2654 /* map transactions to pcie_3 */ 2655 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_3_MASK 0x000F0000 2656 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_3_SHIFT 16 2657 /* map transactions to pcie_4 */ 2658 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_4_MASK 0x00F00000 2659 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_4_SHIFT 20 2660 /* map transactions to pcie_5 */ 2661 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_5_MASK 0x0F000000 2662 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_5_SHIFT 24 2663 /* map transactions to dram */ 2664 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_DRAM_MASK 0xF0000000 2665 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_DRAM_SHIFT 28 2666 2667 /**** pcie_2_mask register ****/ 2668 /* map transactions according to address decoding */ 2669 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2670 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_NO_ENFORCEMENT_SHIFT 0 2671 /* map transactions to pcie_0 */ 2672 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_0_MASK 0x000000F0 2673 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_0_SHIFT 4 2674 /* map transactions to pcie_1 */ 2675 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_1_MASK 0x00000F00 2676 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_1_SHIFT 8 2677 /* map transactions to pcie_2 */ 2678 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_2_MASK 0x0000F000 2679 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_2_SHIFT 12 2680 /* map transactions to pcie_3 */ 2681 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_3_MASK 0x000F0000 2682 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_3_SHIFT 16 2683 /* map transactions to pcie_4 */ 2684 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_4_MASK 0x00F00000 2685 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_4_SHIFT 20 2686 /* map transactions to pcie_5 */ 2687 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_5_MASK 0x0F000000 2688 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_5_SHIFT 24 2689 /* map transactions to dram */ 2690 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_DRAM_MASK 0xF0000000 2691 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_DRAM_SHIFT 28 2692 2693 /**** pcie_3 register ****/ 2694 /* map transactions according to address decoding */ 2695 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_NO_ENFORCEMENT_MASK 0x0000000F 2696 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_NO_ENFORCEMENT_SHIFT 0 2697 /* map transactions to pcie_0 */ 2698 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_0_MASK 0x000000F0 2699 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_0_SHIFT 4 2700 /* map transactions to pcie_1 */ 2701 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_1_MASK 0x00000F00 2702 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_1_SHIFT 8 2703 /* map transactions to pcie_2 */ 2704 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_2_MASK 0x0000F000 2705 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_2_SHIFT 12 2706 /* map transactions to pcie_3 */ 2707 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_3_MASK 0x000F0000 2708 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_3_SHIFT 16 2709 /* map transactions to pcie_4 */ 2710 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_4_MASK 0x00F00000 2711 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_4_SHIFT 20 2712 /* map transactions to pcie_5 */ 2713 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_5_MASK 0x0F000000 2714 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_5_SHIFT 24 2715 /* map transactions to dram */ 2716 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_DRAM_MASK 0xF0000000 2717 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_DRAM_SHIFT 28 2718 2719 /**** pcie_3_mask register ****/ 2720 /* map transactions according to address decoding */ 2721 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2722 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_NO_ENFORCEMENT_SHIFT 0 2723 /* map transactions to pcie_0 */ 2724 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_0_MASK 0x000000F0 2725 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_0_SHIFT 4 2726 /* map transactions to pcie_1 */ 2727 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_1_MASK 0x00000F00 2728 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_1_SHIFT 8 2729 /* map transactions to pcie_2 */ 2730 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_2_MASK 0x0000F000 2731 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_2_SHIFT 12 2732 /* map transactions to pcie_3 */ 2733 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_3_MASK 0x000F0000 2734 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_3_SHIFT 16 2735 /* map transactions to pcie_4 */ 2736 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_4_MASK 0x00F00000 2737 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_4_SHIFT 20 2738 /* map transactions to pcie_5 */ 2739 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_5_MASK 0x0F000000 2740 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_5_SHIFT 24 2741 /* map transactions to dram */ 2742 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_DRAM_MASK 0xF0000000 2743 #define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_DRAM_SHIFT 28 2744 2745 /**** latch register ****/ 2746 /* 2747 * Software clears this bit before any bar update, and set it after all bars 2748 * updated. 2749 */ 2750 #define PBS_TARGET_ID_ENFORCEMENT_LATCH_ENABLE (1 << 0) 2751 2752 #ifdef __cplusplus 2753 } 2754 #endif 2755 2756 #endif /* __AL_HAL_PBS_REGS_H__ */ 2757 2758 /** @} end of ... group */ 2759 2760 2761