1 /*_ 2 ******************************************************************************** 3 Copyright (C) 2015 Annapurna Labs Ltd. 4 5 This file may be licensed under the terms of the Annapurna Labs Commercial 6 License Agreement. 7 8 Alternatively, this file can be distributed under the terms of the GNU General 9 Public License V2 as published by the Free Software Foundation and can be 10 found at http://www.gnu.org/licenses/gpl-2.0.html 11 12 Alternatively, redistribution and use in source and binary forms, with or 13 without modification, are permitted provided that the following conditions are 14 met: 15 16 * Redistributions of source code must retain the above copyright notice, 17 this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20 notice, this list of conditions and the following disclaimer in 21 the documentation and/or other materials provided with the 22 distribution. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35 *******************************************************************************/ 36 37 38 #ifndef __AL_HAL_IOFIC_REG_H 39 #define __AL_HAL_IOFIC_REG_H 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 /* 45 * Unit Registers 46 */ 47 48 struct al_iofic_grp_ctrl { 49 uint32_t int_cause_grp; /* Interrupt Cause RegisterSet by hardware */ 50 uint32_t rsrvd1; 51 uint32_t int_cause_set_grp; /* Interrupt Cause Set RegisterWriting 1 to a bit in t ... */ 52 uint32_t rsrvd2; 53 uint32_t int_mask_grp; /* Interrupt Mask RegisterIf Auto-mask control bit =TR ... */ 54 uint32_t rsrvd3; 55 uint32_t int_mask_clear_grp; /* Interrupt Mask Clear RegisterUsed when auto-mask co ... */ 56 uint32_t rsrvd4; 57 uint32_t int_status_grp; /* Interrupt status RegisterThis register latch the st ... */ 58 uint32_t rsrvd5; 59 uint32_t int_control_grp; /* Interrupt Control Register */ 60 uint32_t rsrvd6; 61 uint32_t int_abort_msk_grp; /* Interrupt Mask RegisterEach bit in this register ma ... */ 62 uint32_t rsrvd7; 63 uint32_t int_log_msk_grp; /* Interrupt Log RegisterEach bit in this register mas ... */ 64 uint32_t rsrvd8; 65 }; 66 67 struct al_iofic_grp_mod { 68 uint32_t grp_int_mod_reg; /* Interrupt moderation registerDedicated moderation in ... */ 69 uint32_t grp_int_tgtid_reg; 70 }; 71 72 struct al_iofic_regs { 73 struct al_iofic_grp_ctrl ctrl[0]; 74 uint32_t rsrvd1[0x400 >> 2]; 75 struct al_iofic_grp_mod grp_int_mod[0][32]; 76 }; 77 78 79 /* 80 * Registers Fields 81 */ 82 83 84 /**** int_control_grp register ****/ 85 /* When Clear_on_Read =1, All bits of Cause register ... */ 86 #define INT_CONTROL_GRP_CLEAR_ON_READ (1 << 0) 87 /* (must be set only when MSIX is enabled)When Auto-Ma ... */ 88 #define INT_CONTROL_GRP_AUTO_MASK (1 << 1) 89 /* Auto_Clear (RW)When Auto-Clear =1, the bits in the ... */ 90 #define INT_CONTROL_GRP_AUTO_CLEAR (1 << 2) 91 /* When Set_on_Posedge =1, the bits in the interrupt c ... */ 92 #define INT_CONTROL_GRP_SET_ON_POSEDGE (1 << 3) 93 /* When Moderation_Reset =1, all Moderation timers ass ... */ 94 #define INT_CONTROL_GRP_MOD_RST (1 << 4) 95 /* When mask_msi_x =1, No MSI-X from this group is sen ... */ 96 #define INT_CONTROL_GRP_MASK_MSI_X (1 << 5) 97 /* MSI-X AWID value, same ID for all cause bits */ 98 #define INT_CONTROL_GRP_AWID_MASK 0x00000F00 99 #define INT_CONTROL_GRP_AWID_SHIFT 8 100 /* This value determines the interval between interrup ... */ 101 #define INT_CONTROL_GRP_MOD_INTV_MASK 0x00FF0000 102 #define INT_CONTROL_GRP_MOD_INTV_SHIFT 16 103 /* This value determines the Moderation_Timer_Clock sp ... */ 104 #define INT_CONTROL_GRP_MOD_RES_MASK 0x0F000000 105 #define INT_CONTROL_GRP_MOD_RES_SHIFT 24 106 107 /**** grp_int_mod_reg register ****/ 108 /* Interrupt Moderation Interval registerDedicated reg ... */ 109 #define INT_MOD_INTV_MASK 0x000000FF 110 #define INT_MOD_INTV_SHIFT 0 111 112 /**** grp_int_tgtid_reg register ****/ 113 /* Interrupt tgtid value registerDedicated reg ... */ 114 #define INT_MSIX_TGTID_MASK 0x0000FFFF 115 #define INT_MSIX_TGTID_SHIFT 0 116 /* Interrupt tgtid_en value registerDedicated reg ... */ 117 #define INT_MSIX_TGTID_EN_SHIFT 31 118 119 #ifdef __cplusplus 120 } 121 #endif 122 123 #endif /* __AL_HAL_IOFIC_REG_H */ 124 125 126 127 128