1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/nv.h> 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 #include <linux/pm.h> 63 64 struct pci_device_id { 65 uint32_t vendor; 66 uint32_t device; 67 uint32_t subvendor; 68 uint32_t subdevice; 69 uint32_t class; 70 uint32_t class_mask; 71 uintptr_t driver_data; 72 }; 73 74 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 75 #define MODULE_DEVICE_TABLE(_bus, _table) \ 76 \ 77 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 78 DEVMETHOD_END \ 79 }; \ 80 \ 81 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 82 "lkpi_" #_bus #_table, \ 83 _ ## _bus ## _ ## _table ## _methods, \ 84 0 \ 85 }; \ 86 \ 87 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 88 0, 0); \ 89 \ 90 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 91 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 92 93 #define PCI_ANY_ID -1U 94 95 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 96 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 97 #define PCI_FUNC(devfn) ((devfn) & 0x07) 98 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 99 100 #define PCI_VDEVICE(_vendor, _device) \ 101 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 102 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 103 #define PCI_DEVICE(_vendor, _device) \ 104 .vendor = (_vendor), .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 107 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 108 109 #define PCI_VENDOR_ID PCIR_VENDOR 110 #define PCI_DEVICE_ID PCIR_DEVICE 111 #define PCI_COMMAND PCIR_COMMAND 112 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 115 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 116 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 117 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 118 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 119 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 120 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 121 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 122 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 123 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 124 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 125 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 126 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 127 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 128 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 129 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 130 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 131 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 132 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 133 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 134 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 135 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 136 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 137 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 138 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 139 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 140 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 141 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 142 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 143 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 144 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 145 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 146 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 147 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 148 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 149 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 150 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 151 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 152 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 153 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 154 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 155 #define PCI_EXP_LNKCTL2_TLS 0x000f 156 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 157 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 158 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 159 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 160 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 161 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 162 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 163 164 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 165 #define PCI_EXP_DEVSTA_TRPND 0x0020 166 167 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 168 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 169 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 170 171 enum pci_bus_speed { 172 PCI_SPEED_UNKNOWN = -1, 173 PCIE_SPEED_2_5GT, 174 PCIE_SPEED_5_0GT, 175 PCIE_SPEED_8_0GT, 176 PCIE_SPEED_16_0GT, 177 }; 178 179 enum pcie_link_width { 180 PCIE_LNK_WIDTH_RESRV = 0x00, 181 PCIE_LNK_X1 = 0x01, 182 PCIE_LNK_X2 = 0x02, 183 PCIE_LNK_X4 = 0x04, 184 PCIE_LNK_X8 = 0x08, 185 PCIE_LNK_X12 = 0x0c, 186 PCIE_LNK_X16 = 0x10, 187 PCIE_LNK_X32 = 0x20, 188 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 189 }; 190 191 #define PCIE_LINK_STATE_L0S 0x00000001 192 #define PCIE_LINK_STATE_L1 0x00000002 193 #define PCIE_LINK_STATE_CLKPM 0x00000004 194 195 typedef int pci_power_t; 196 197 #define PCI_D0 PCI_POWERSTATE_D0 198 #define PCI_D1 PCI_POWERSTATE_D1 199 #define PCI_D2 PCI_POWERSTATE_D2 200 #define PCI_D3hot PCI_POWERSTATE_D3 201 #define PCI_D3cold 4 202 203 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 204 205 extern const char *pci_power_names[6]; 206 207 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 208 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 209 210 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 211 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 212 213 #define PCI_L1SS_CTL1 0x8 214 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 215 216 #define PCI_IRQ_LEGACY 0x01 217 #define PCI_IRQ_MSI 0x02 218 #define PCI_IRQ_MSIX 0x04 219 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 220 221 struct pci_dev; 222 223 struct pci_driver { 224 struct list_head node; 225 char *name; 226 const struct pci_device_id *id_table; 227 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 228 void (*remove)(struct pci_dev *dev); 229 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 230 int (*resume) (struct pci_dev *dev); /* Device woken up */ 231 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 232 driver_t bsddriver; 233 devclass_t bsdclass; 234 struct device_driver driver; 235 const struct pci_error_handlers *err_handler; 236 bool isdrm; 237 int bsd_probe_return; 238 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 239 const nvlist_t *pf_config); 240 void (*bsd_iov_uninit)(device_t dev); 241 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 242 const nvlist_t *vf_config); 243 }; 244 245 struct pci_bus { 246 struct pci_dev *self; 247 int domain; 248 int number; 249 }; 250 251 extern struct list_head pci_drivers; 252 extern struct list_head pci_devices; 253 extern spinlock_t pci_lock; 254 255 #define __devexit_p(x) x 256 257 #define module_pci_driver(_driver) \ 258 \ 259 static inline int \ 260 _pci_init(void) \ 261 { \ 262 \ 263 return (linux_pci_register_driver(&_driver)); \ 264 } \ 265 \ 266 static inline void \ 267 _pci_exit(void) \ 268 { \ 269 \ 270 linux_pci_unregister_driver(&_driver); \ 271 } \ 272 \ 273 module_init(_pci_init); \ 274 module_exit(_pci_exit) 275 276 /* 277 * If we find drivers accessing this from multiple KPIs we may have to 278 * refcount objects of this structure. 279 */ 280 struct pci_mmio_region { 281 TAILQ_ENTRY(pci_mmio_region) next; 282 struct resource *res; 283 int rid; 284 int type; 285 }; 286 287 struct pci_dev { 288 struct device dev; 289 struct list_head links; 290 struct pci_driver *pdrv; 291 struct pci_bus *bus; 292 struct pci_dev *root; 293 pci_power_t current_state; 294 uint16_t device; 295 uint16_t vendor; 296 uint16_t subsystem_vendor; 297 uint16_t subsystem_device; 298 unsigned int irq; 299 unsigned int devfn; 300 uint32_t class; 301 uint8_t revision; 302 bool managed; /* devres "pcim_*(). */ 303 bool want_iomap_res; 304 bool msi_enabled; 305 bool msix_enabled; 306 phys_addr_t rom; 307 size_t romlen; 308 309 TAILQ_HEAD(, pci_mmio_region) mmio; 310 }; 311 312 /* We need some meta-struct to keep track of these for devres. */ 313 struct pci_devres { 314 bool enable_io; 315 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 316 uint8_t region_mask; 317 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 318 }; 319 struct pcim_iomap_devres { 320 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 321 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 322 }; 323 324 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 325 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 326 unsigned int flags); 327 328 /* Internal helper function(s). */ 329 struct pci_dev *lkpinew_pci_dev(device_t); 330 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev); 331 void lkpi_pci_devres_release(struct device *, void *); 332 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size); 333 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev); 334 void lkpi_pcim_iomap_table_release(struct device *, void *); 335 336 static inline bool 337 dev_is_pci(struct device *dev) 338 { 339 340 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 341 } 342 343 static inline int 344 pci_resource_type(struct pci_dev *pdev, int bar) 345 { 346 struct pci_map *pm; 347 348 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 349 if (!pm) 350 return (-1); 351 352 if (PCI_BAR_IO(pm->pm_value)) 353 return (SYS_RES_IOPORT); 354 else 355 return (SYS_RES_MEMORY); 356 } 357 358 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 359 struct resource_list *rl, int type, int rid); 360 361 static inline struct resource_list_entry * 362 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 363 { 364 struct pci_devinfo *dinfo; 365 struct resource_list *rl; 366 struct resource_list_entry *rle; 367 368 dinfo = device_get_ivars(pdev->dev.bsddev); 369 rl = &dinfo->resources; 370 rle = resource_list_find(rl, type, rid); 371 /* Reserve resources for this BAR if needed. */ 372 if (rle == NULL && reserve_bar) 373 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 374 return (rle); 375 } 376 377 static inline struct resource_list_entry * 378 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 379 { 380 int type; 381 382 type = pci_resource_type(pdev, bar); 383 if (type < 0) 384 return (NULL); 385 bar = PCIR_BAR(bar); 386 return (linux_pci_get_rle(pdev, type, bar, reserve)); 387 } 388 389 static inline struct device * 390 linux_pci_find_irq_dev(unsigned int irq) 391 { 392 struct pci_dev *pdev; 393 struct device *found; 394 395 found = NULL; 396 spin_lock(&pci_lock); 397 list_for_each_entry(pdev, &pci_devices, links) { 398 if (irq == pdev->dev.irq || 399 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 400 found = &pdev->dev; 401 break; 402 } 403 } 404 spin_unlock(&pci_lock); 405 return (found); 406 } 407 408 /* 409 * All drivers just seem to want to inspect the type not flags. 410 */ 411 static inline int 412 pci_resource_flags(struct pci_dev *pdev, int bar) 413 { 414 int type; 415 416 type = pci_resource_type(pdev, bar); 417 if (type < 0) 418 return (0); 419 return (1 << type); 420 } 421 422 static inline const char * 423 pci_name(struct pci_dev *d) 424 { 425 426 return device_get_desc(d->dev.bsddev); 427 } 428 429 static inline void * 430 pci_get_drvdata(struct pci_dev *pdev) 431 { 432 433 return dev_get_drvdata(&pdev->dev); 434 } 435 436 static inline void 437 pci_set_drvdata(struct pci_dev *pdev, void *data) 438 { 439 440 dev_set_drvdata(&pdev->dev, data); 441 } 442 443 static inline struct pci_dev * 444 pci_dev_get(struct pci_dev *pdev) 445 { 446 447 if (pdev != NULL) 448 get_device(&pdev->dev); 449 return (pdev); 450 } 451 452 static __inline void 453 pci_dev_put(struct pci_dev *pdev) 454 { 455 456 if (pdev != NULL) 457 put_device(&pdev->dev); 458 } 459 460 static inline int 461 pci_enable_device(struct pci_dev *pdev) 462 { 463 464 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 465 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 466 return (0); 467 } 468 469 static inline void 470 pci_disable_device(struct pci_dev *pdev) 471 { 472 473 pci_disable_busmaster(pdev->dev.bsddev); 474 } 475 476 static inline int 477 pci_set_master(struct pci_dev *pdev) 478 { 479 480 pci_enable_busmaster(pdev->dev.bsddev); 481 return (0); 482 } 483 484 static inline int 485 pci_set_power_state(struct pci_dev *pdev, int state) 486 { 487 488 pci_set_powerstate(pdev->dev.bsddev, state); 489 return (0); 490 } 491 492 static inline int 493 pci_clear_master(struct pci_dev *pdev) 494 { 495 496 pci_disable_busmaster(pdev->dev.bsddev); 497 return (0); 498 } 499 500 static inline bool 501 pci_is_root_bus(struct pci_bus *pbus) 502 { 503 504 return (pbus->self == NULL); 505 } 506 507 static inline struct pci_dev * 508 pci_upstream_bridge(struct pci_dev *pdev) 509 { 510 511 if (pci_is_root_bus(pdev->bus)) 512 return (NULL); 513 514 /* 515 * If we do not have a (proper) "upstream bridge" set, e.g., we point 516 * to ourselves, try to handle this case on the fly like we do 517 * for pcie_find_root_port(). 518 */ 519 if (pdev == pdev->bus->self) { 520 device_t bridge; 521 522 bridge = device_get_parent(pdev->dev.bsddev); 523 if (bridge == NULL) 524 goto done; 525 bridge = device_get_parent(bridge); 526 if (bridge == NULL) 527 goto done; 528 if (device_get_devclass(device_get_parent(bridge)) != 529 devclass_find("pci")) 530 goto done; 531 532 /* 533 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 534 * for it so it can be returned. 535 */ 536 pdev->bus->self = lkpinew_pci_dev(bridge); 537 } 538 done: 539 return (pdev->bus->self); 540 } 541 542 static inline struct pci_devres * 543 lkpi_pci_devres_find(struct pci_dev *pdev) 544 { 545 546 if (!pdev->managed) 547 return (NULL); 548 549 return (lkpi_pci_devres_get_alloc(pdev)); 550 } 551 552 static inline void 553 pci_release_region(struct pci_dev *pdev, int bar) 554 { 555 struct resource_list_entry *rle; 556 struct pci_devres *dr; 557 struct pci_mmio_region *mmio, *p; 558 559 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 560 return; 561 562 /* 563 * As we implicitly track the requests we also need to clear them on 564 * release. Do clear before resource release. 565 */ 566 dr = lkpi_pci_devres_find(pdev); 567 if (dr != NULL) { 568 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 569 " region_table res %p != rel->res %p\n", __func__, pdev, 570 bar, dr->region_table[bar], rle->res)); 571 dr->region_table[bar] = NULL; 572 dr->region_mask &= ~(1 << bar); 573 } 574 575 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 576 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 577 continue; 578 TAILQ_REMOVE(&pdev->mmio, mmio, next); 579 free(mmio, M_DEVBUF); 580 } 581 582 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 583 } 584 585 static inline void 586 pci_release_regions(struct pci_dev *pdev) 587 { 588 int i; 589 590 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 591 pci_release_region(pdev, i); 592 } 593 594 static inline int 595 pci_request_regions(struct pci_dev *pdev, const char *res_name) 596 { 597 int error; 598 int i; 599 600 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 601 error = pci_request_region(pdev, i, res_name); 602 if (error && error != -ENODEV) { 603 pci_release_regions(pdev); 604 return (error); 605 } 606 } 607 return (0); 608 } 609 610 static inline void 611 lkpi_pci_disable_msix(struct pci_dev *pdev) 612 { 613 614 pci_release_msi(pdev->dev.bsddev); 615 616 /* 617 * The MSIX IRQ numbers associated with this PCI device are no 618 * longer valid and might be re-assigned. Make sure 619 * linux_pci_find_irq_dev() does no longer see them by 620 * resetting their references to zero: 621 */ 622 pdev->dev.irq_start = 0; 623 pdev->dev.irq_end = 0; 624 pdev->msix_enabled = false; 625 } 626 /* Only for consistency. No conflict on that one. */ 627 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 628 629 static inline void 630 lkpi_pci_disable_msi(struct pci_dev *pdev) 631 { 632 633 pci_release_msi(pdev->dev.bsddev); 634 635 pdev->dev.irq_start = 0; 636 pdev->dev.irq_end = 0; 637 pdev->irq = pdev->dev.irq; 638 pdev->msi_enabled = false; 639 } 640 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 641 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 642 643 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 644 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 645 646 static inline bus_addr_t 647 pci_bus_address(struct pci_dev *pdev, int bar) 648 { 649 650 return (pci_resource_start(pdev, bar)); 651 } 652 653 #define PCI_CAP_ID_EXP PCIY_EXPRESS 654 #define PCI_CAP_ID_PCIX PCIY_PCIX 655 #define PCI_CAP_ID_AGP PCIY_AGP 656 #define PCI_CAP_ID_PM PCIY_PMG 657 658 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 659 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 660 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 661 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 662 #define PCI_EXP_LNKSTA PCIER_LINK_STA 663 664 static inline int 665 pci_find_capability(struct pci_dev *pdev, int capid) 666 { 667 int reg; 668 669 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 670 return (0); 671 return (reg); 672 } 673 674 static inline int pci_pcie_cap(struct pci_dev *dev) 675 { 676 return pci_find_capability(dev, PCI_CAP_ID_EXP); 677 } 678 679 static inline int 680 pci_find_ext_capability(struct pci_dev *pdev, int capid) 681 { 682 int reg; 683 684 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 685 return (0); 686 return (reg); 687 } 688 689 #define PCIM_PCAP_PME_SHIFT 11 690 static __inline bool 691 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 692 { 693 struct pci_devinfo *dinfo; 694 pcicfgregs *cfg; 695 696 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 697 return (false); 698 699 dinfo = device_get_ivars(pdev->dev.bsddev); 700 cfg = &dinfo->cfg; 701 702 if (cfg->pp.pp_cap == 0) 703 return (false); 704 705 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 706 return (true); 707 708 return (false); 709 } 710 711 static inline int 712 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 713 { 714 715 if (!pci_enable_aspm) 716 return (-EPERM); 717 718 return (-ENXIO); 719 } 720 721 static inline int 722 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 723 { 724 725 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 726 return (0); 727 } 728 729 static inline int 730 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 731 { 732 733 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 734 return (0); 735 } 736 737 static inline int 738 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 739 { 740 741 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 742 return (0); 743 } 744 745 static inline int 746 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 747 { 748 749 pci_write_config(pdev->dev.bsddev, where, val, 1); 750 return (0); 751 } 752 753 static inline int 754 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 755 { 756 757 pci_write_config(pdev->dev.bsddev, where, val, 2); 758 return (0); 759 } 760 761 static inline int 762 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 763 { 764 765 pci_write_config(pdev->dev.bsddev, where, val, 4); 766 return (0); 767 } 768 769 int linux_pci_register_driver(struct pci_driver *pdrv); 770 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 771 void linux_pci_unregister_driver(struct pci_driver *pdrv); 772 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 773 774 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 775 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 776 777 struct msix_entry { 778 int entry; 779 int vector; 780 }; 781 782 /* 783 * Enable msix, positive errors indicate actual number of available 784 * vectors. Negative errors are failures. 785 * 786 * NB: define added to prevent this definition of pci_enable_msix from 787 * clashing with the native FreeBSD version. 788 */ 789 #define pci_enable_msix(...) \ 790 linux_pci_enable_msix(__VA_ARGS__) 791 792 static inline int 793 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 794 { 795 struct resource_list_entry *rle; 796 int error; 797 int avail; 798 int i; 799 800 avail = pci_msix_count(pdev->dev.bsddev); 801 if (avail < nreq) { 802 if (avail == 0) 803 return -EINVAL; 804 return avail; 805 } 806 avail = nreq; 807 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 808 return error; 809 /* 810 * Handle case where "pci_alloc_msix()" may allocate less 811 * interrupts than available and return with no error: 812 */ 813 if (avail < nreq) { 814 pci_release_msi(pdev->dev.bsddev); 815 return avail; 816 } 817 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 818 pdev->dev.irq_start = rle->start; 819 pdev->dev.irq_end = rle->start + avail; 820 for (i = 0; i < nreq; i++) 821 entries[i].vector = pdev->dev.irq_start + i; 822 pdev->msix_enabled = true; 823 return (0); 824 } 825 826 #define pci_enable_msix_range(...) \ 827 linux_pci_enable_msix_range(__VA_ARGS__) 828 829 static inline int 830 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 831 int minvec, int maxvec) 832 { 833 int nvec = maxvec; 834 int rc; 835 836 if (maxvec < minvec) 837 return (-ERANGE); 838 839 do { 840 rc = pci_enable_msix(dev, entries, nvec); 841 if (rc < 0) { 842 return (rc); 843 } else if (rc > 0) { 844 if (rc < minvec) 845 return (-ENOSPC); 846 nvec = rc; 847 } 848 } while (rc); 849 return (nvec); 850 } 851 852 #define pci_enable_msi(pdev) \ 853 linux_pci_enable_msi(pdev) 854 855 static inline int 856 pci_enable_msi(struct pci_dev *pdev) 857 { 858 struct resource_list_entry *rle; 859 int error; 860 int avail; 861 862 avail = pci_msi_count(pdev->dev.bsddev); 863 if (avail < 1) 864 return -EINVAL; 865 866 avail = 1; /* this function only enable one MSI IRQ */ 867 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 868 return error; 869 870 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 871 pdev->dev.irq_start = rle->start; 872 pdev->dev.irq_end = rle->start + avail; 873 pdev->irq = rle->start; 874 pdev->msi_enabled = true; 875 return (0); 876 } 877 878 static inline int 879 pci_channel_offline(struct pci_dev *pdev) 880 { 881 882 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 883 } 884 885 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 886 { 887 return -ENODEV; 888 } 889 890 static inline void pci_disable_sriov(struct pci_dev *dev) 891 { 892 } 893 894 static inline void * 895 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 896 { 897 struct resource *res; 898 899 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 900 if (res == NULL) 901 return (NULL); 902 /* This is a FreeBSD extension so we can use bus_*(). */ 903 if (pdev->want_iomap_res) 904 return (res); 905 return ((void *)rman_get_bushandle(res)); 906 } 907 908 static inline void 909 pci_iounmap(struct pci_dev *pdev, void *res) 910 { 911 struct pci_mmio_region *mmio, *p; 912 913 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 914 if (res != (void *)rman_get_bushandle(mmio->res)) 915 continue; 916 bus_release_resource(pdev->dev.bsddev, 917 mmio->type, mmio->rid, mmio->res); 918 TAILQ_REMOVE(&pdev->mmio, mmio, next); 919 free(mmio, M_DEVBUF); 920 return; 921 } 922 } 923 924 static inline void 925 lkpi_pci_save_state(struct pci_dev *pdev) 926 { 927 928 pci_save_state(pdev->dev.bsddev); 929 } 930 931 static inline void 932 lkpi_pci_restore_state(struct pci_dev *pdev) 933 { 934 935 pci_restore_state(pdev->dev.bsddev); 936 } 937 938 #define pci_save_state(dev) lkpi_pci_save_state(dev) 939 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 940 941 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 942 const struct pci_device_id _table[] __devinitdata 943 944 /* XXX This should not be necessary. */ 945 #define pcix_set_mmrbc(d, v) 0 946 #define pcix_get_max_mmrbc(d) 0 947 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 948 949 #define PCI_DMA_BIDIRECTIONAL 0 950 #define PCI_DMA_TODEVICE 1 951 #define PCI_DMA_FROMDEVICE 2 952 #define PCI_DMA_NONE 3 953 954 #define pci_pool dma_pool 955 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 956 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 957 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 958 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 959 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 960 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 961 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 962 _size, _vaddr, _dma_handle) 963 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 964 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 965 _sg, _nents, (enum dma_data_direction)_dir) 966 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 967 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 968 (_ptr), (_size), (enum dma_data_direction)_dir) 969 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 970 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 971 _addr, _size, (enum dma_data_direction)_dir) 972 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 973 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 974 _sg, _nents, (enum dma_data_direction)_dir) 975 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 976 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 977 _offset, _size, (enum dma_data_direction)_dir) 978 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 979 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 980 _dma_address, _size, (enum dma_data_direction)_dir) 981 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 982 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 983 dma_mapping_error(&(_pdev)->dev, _dma_addr) 984 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 985 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 986 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 987 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 988 #define pci_unmap_addr dma_unmap_addr 989 #define pci_unmap_addr_set dma_unmap_addr_set 990 #define pci_unmap_len dma_unmap_len 991 #define pci_unmap_len_set dma_unmap_len_set 992 993 typedef unsigned int __bitwise pci_channel_state_t; 994 typedef unsigned int __bitwise pci_ers_result_t; 995 996 enum pci_channel_state { 997 pci_channel_io_normal = 1, 998 pci_channel_io_frozen = 2, 999 pci_channel_io_perm_failure = 3, 1000 }; 1001 1002 enum pci_ers_result { 1003 PCI_ERS_RESULT_NONE = 1, 1004 PCI_ERS_RESULT_CAN_RECOVER = 2, 1005 PCI_ERS_RESULT_NEED_RESET = 3, 1006 PCI_ERS_RESULT_DISCONNECT = 4, 1007 PCI_ERS_RESULT_RECOVERED = 5, 1008 }; 1009 1010 /* PCI bus error event callbacks */ 1011 struct pci_error_handlers { 1012 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1013 enum pci_channel_state error); 1014 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1015 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1016 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1017 void (*resume)(struct pci_dev *dev); 1018 }; 1019 1020 /* FreeBSD does not support SRIOV - yet */ 1021 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1022 { 1023 return dev; 1024 } 1025 1026 static inline bool pci_is_pcie(struct pci_dev *dev) 1027 { 1028 return !!pci_pcie_cap(dev); 1029 } 1030 1031 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1032 { 1033 int pos; 1034 u16 reg16; 1035 1036 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1037 if (!pos) 1038 return 0; 1039 1040 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1041 1042 return reg16; 1043 } 1044 1045 static inline int pci_pcie_type(struct pci_dev *dev) 1046 { 1047 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1048 } 1049 1050 static inline int pcie_cap_version(struct pci_dev *dev) 1051 { 1052 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1053 } 1054 1055 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1056 { 1057 int type = pci_pcie_type(dev); 1058 1059 return pcie_cap_version(dev) > 1 || 1060 type == PCI_EXP_TYPE_ROOT_PORT || 1061 type == PCI_EXP_TYPE_ENDPOINT || 1062 type == PCI_EXP_TYPE_LEG_END; 1063 } 1064 1065 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1066 { 1067 return true; 1068 } 1069 1070 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1071 { 1072 int type = pci_pcie_type(dev); 1073 1074 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1075 (type == PCI_EXP_TYPE_DOWNSTREAM && 1076 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1077 } 1078 1079 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1080 { 1081 int type = pci_pcie_type(dev); 1082 1083 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1084 type == PCI_EXP_TYPE_RC_EC; 1085 } 1086 1087 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1088 { 1089 if (!pci_is_pcie(dev)) 1090 return false; 1091 1092 switch (pos) { 1093 case PCI_EXP_FLAGS_TYPE: 1094 return true; 1095 case PCI_EXP_DEVCAP: 1096 case PCI_EXP_DEVCTL: 1097 case PCI_EXP_DEVSTA: 1098 return pcie_cap_has_devctl(dev); 1099 case PCI_EXP_LNKCAP: 1100 case PCI_EXP_LNKCTL: 1101 case PCI_EXP_LNKSTA: 1102 return pcie_cap_has_lnkctl(dev); 1103 case PCI_EXP_SLTCAP: 1104 case PCI_EXP_SLTCTL: 1105 case PCI_EXP_SLTSTA: 1106 return pcie_cap_has_sltctl(dev); 1107 case PCI_EXP_RTCTL: 1108 case PCI_EXP_RTCAP: 1109 case PCI_EXP_RTSTA: 1110 return pcie_cap_has_rtctl(dev); 1111 case PCI_EXP_DEVCAP2: 1112 case PCI_EXP_DEVCTL2: 1113 case PCI_EXP_LNKCAP2: 1114 case PCI_EXP_LNKCTL2: 1115 case PCI_EXP_LNKSTA2: 1116 return pcie_cap_version(dev) > 1; 1117 default: 1118 return false; 1119 } 1120 } 1121 1122 static inline int 1123 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1124 { 1125 if (pos & 3) 1126 return -EINVAL; 1127 1128 if (!pcie_capability_reg_implemented(dev, pos)) 1129 return -EINVAL; 1130 1131 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1132 } 1133 1134 static inline int 1135 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1136 { 1137 if (pos & 3) 1138 return -EINVAL; 1139 1140 if (!pcie_capability_reg_implemented(dev, pos)) 1141 return -EINVAL; 1142 1143 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1144 } 1145 1146 static inline int 1147 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1148 { 1149 if (pos & 1) 1150 return -EINVAL; 1151 1152 if (!pcie_capability_reg_implemented(dev, pos)) 1153 return 0; 1154 1155 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1156 } 1157 1158 static inline int 1159 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1160 { 1161 int error; 1162 uint16_t v; 1163 1164 error = pcie_capability_read_word(dev, pos, &v); 1165 if (error != 0) 1166 return (error); 1167 1168 v |= val; 1169 1170 error = pcie_capability_write_word(dev, pos, v); 1171 return (error); 1172 } 1173 1174 static inline int 1175 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1176 { 1177 int error; 1178 uint16_t v; 1179 1180 error = pcie_capability_read_word(dev, pos, &v); 1181 if (error != 0) 1182 return (error); 1183 1184 v &= ~val; 1185 1186 error = pcie_capability_write_word(dev, pos, v); 1187 return (error); 1188 } 1189 1190 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1191 enum pci_bus_speed *speed, enum pcie_link_width *width) 1192 { 1193 *speed = PCI_SPEED_UNKNOWN; 1194 *width = PCIE_LNK_WIDTH_UNKNOWN; 1195 return (0); 1196 } 1197 1198 static inline int 1199 pci_num_vf(struct pci_dev *dev) 1200 { 1201 return (0); 1202 } 1203 1204 static inline enum pci_bus_speed 1205 pcie_get_speed_cap(struct pci_dev *dev) 1206 { 1207 device_t root; 1208 uint32_t lnkcap, lnkcap2; 1209 int error, pos; 1210 1211 root = device_get_parent(dev->dev.bsddev); 1212 if (root == NULL) 1213 return (PCI_SPEED_UNKNOWN); 1214 root = device_get_parent(root); 1215 if (root == NULL) 1216 return (PCI_SPEED_UNKNOWN); 1217 root = device_get_parent(root); 1218 if (root == NULL) 1219 return (PCI_SPEED_UNKNOWN); 1220 1221 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1222 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1223 return (PCI_SPEED_UNKNOWN); 1224 1225 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1226 return (PCI_SPEED_UNKNOWN); 1227 1228 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1229 1230 if (lnkcap2) { /* PCIe r3.0-compliant */ 1231 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1232 return (PCIE_SPEED_2_5GT); 1233 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1234 return (PCIE_SPEED_5_0GT); 1235 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1236 return (PCIE_SPEED_8_0GT); 1237 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1238 return (PCIE_SPEED_16_0GT); 1239 } else { /* pre-r3.0 */ 1240 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1241 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1242 return (PCIE_SPEED_2_5GT); 1243 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1244 return (PCIE_SPEED_5_0GT); 1245 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1246 return (PCIE_SPEED_8_0GT); 1247 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1248 return (PCIE_SPEED_16_0GT); 1249 } 1250 return (PCI_SPEED_UNKNOWN); 1251 } 1252 1253 static inline enum pcie_link_width 1254 pcie_get_width_cap(struct pci_dev *dev) 1255 { 1256 uint32_t lnkcap; 1257 1258 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1259 if (lnkcap) 1260 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1261 1262 return (PCIE_LNK_WIDTH_UNKNOWN); 1263 } 1264 1265 static inline int 1266 pcie_get_mps(struct pci_dev *dev) 1267 { 1268 return (pci_get_max_payload(dev->dev.bsddev)); 1269 } 1270 1271 static inline uint32_t 1272 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1273 { 1274 1275 switch(spd) { 1276 case PCIE_SPEED_16_0GT: 1277 return (16000 * 128 / 130); 1278 case PCIE_SPEED_8_0GT: 1279 return (8000 * 128 / 130); 1280 case PCIE_SPEED_5_0GT: 1281 return (5000 * 8 / 10); 1282 case PCIE_SPEED_2_5GT: 1283 return (2500 * 8 / 10); 1284 default: 1285 return (0); 1286 } 1287 } 1288 1289 static inline uint32_t 1290 pcie_bandwidth_available(struct pci_dev *pdev, 1291 struct pci_dev **limiting, 1292 enum pci_bus_speed *speed, 1293 enum pcie_link_width *width) 1294 { 1295 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1296 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1297 1298 if (speed) 1299 *speed = nspeed; 1300 if (width) 1301 *width = nwidth; 1302 1303 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1304 } 1305 1306 static inline struct pci_dev * 1307 pcie_find_root_port(struct pci_dev *pdev) 1308 { 1309 device_t root; 1310 1311 if (pdev->root != NULL) 1312 return (pdev->root); 1313 1314 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1315 if (root == NULL) 1316 return (NULL); 1317 1318 pdev->root = lkpinew_pci_dev(root); 1319 return (pdev->root); 1320 } 1321 1322 /* This is needed when people rip out the device "HotPlug". */ 1323 static inline void 1324 pci_lock_rescan_remove(void) 1325 { 1326 } 1327 1328 static inline void 1329 pci_unlock_rescan_remove(void) 1330 { 1331 } 1332 1333 static __inline void 1334 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1335 { 1336 } 1337 1338 /* 1339 * The following functions can be used to attach/detach the LinuxKPI's 1340 * PCI device runtime. The pci_driver and pci_device_id pointer is 1341 * allowed to be NULL. Other pointers must be all valid. 1342 * The pci_dev structure should be zero-initialized before passed 1343 * to the linux_pci_attach_device function. 1344 */ 1345 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1346 const struct pci_device_id *, struct pci_dev *); 1347 extern int linux_pci_detach_device(struct pci_dev *); 1348 1349 static inline int 1350 pci_dev_present(const struct pci_device_id *cur) 1351 { 1352 while (cur != NULL && (cur->vendor || cur->device)) { 1353 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1354 return (1); 1355 } 1356 cur++; 1357 } 1358 return (0); 1359 } 1360 1361 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1362 unsigned int bus, unsigned int devfn); 1363 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1364 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1365 1366 static inline int 1367 pci_domain_nr(struct pci_bus *pbus) 1368 { 1369 1370 return (pbus->domain); 1371 } 1372 1373 static inline int 1374 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1375 int pos, uint32_t *val, int len) 1376 { 1377 1378 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1379 return (0); 1380 } 1381 1382 static inline int 1383 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1384 { 1385 uint32_t tmp; 1386 int ret; 1387 1388 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1389 *val = (u16)tmp; 1390 return (ret); 1391 } 1392 1393 static inline int 1394 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1395 { 1396 uint32_t tmp; 1397 int ret; 1398 1399 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1400 *val = (u8)tmp; 1401 return (ret); 1402 } 1403 1404 static inline int 1405 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1406 uint32_t val, int size) 1407 { 1408 1409 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1410 return (0); 1411 } 1412 1413 static inline int 1414 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1415 uint8_t val) 1416 { 1417 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1418 } 1419 1420 static inline int 1421 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1422 uint16_t val) 1423 { 1424 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1425 } 1426 1427 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1428 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1429 1430 /* -------------------------------------------------------------------------- */ 1431 1432 static inline int 1433 pcim_enable_device(struct pci_dev *pdev) 1434 { 1435 struct pci_devres *dr; 1436 int error; 1437 1438 /* Here we cannot run through the pdev->managed check. */ 1439 dr = lkpi_pci_devres_get_alloc(pdev); 1440 if (dr == NULL) 1441 return (-ENOMEM); 1442 1443 /* If resources were enabled before do not do it again. */ 1444 if (dr->enable_io) 1445 return (0); 1446 1447 error = pci_enable_device(pdev); 1448 if (error == 0) 1449 dr->enable_io = true; 1450 1451 /* This device is not managed. */ 1452 pdev->managed = true; 1453 1454 return (error); 1455 } 1456 1457 static inline void __iomem ** 1458 pcim_iomap_table(struct pci_dev *pdev) 1459 { 1460 struct pcim_iomap_devres *dr; 1461 1462 dr = lkpi_pcim_iomap_devres_find(pdev); 1463 if (dr == NULL) 1464 return (NULL); 1465 1466 /* 1467 * If the driver has manually set a flag to be able to request the 1468 * resource to use bus_read/write_<n>, return the shadow table. 1469 */ 1470 if (pdev->want_iomap_res) 1471 return ((void **)dr->res_table); 1472 1473 /* This is the Linux default. */ 1474 return (dr->mmio_table); 1475 } 1476 1477 static inline int 1478 pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, const char *name) 1479 { 1480 struct pcim_iomap_devres *dr; 1481 void *res; 1482 uint32_t mappings; 1483 int bar; 1484 1485 dr = lkpi_pcim_iomap_devres_find(pdev); 1486 if (dr == NULL) 1487 return (-ENOMEM); 1488 1489 /* Now iomap all the requested (by "mask") ones. */ 1490 for (bar = mappings = 0; mappings != mask; bar++) { 1491 if ((mask & (1 << bar)) == 0) 1492 continue; 1493 1494 /* Request double is not allowed. */ 1495 if (dr->mmio_table[bar] != NULL) { 1496 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1497 __func__, bar, dr->mmio_table[bar]); 1498 goto err; 1499 } 1500 1501 res = _lkpi_pci_iomap(pdev, bar, 0); 1502 if (res == NULL) 1503 goto err; 1504 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1505 dr->res_table[bar] = res; 1506 1507 mappings |= (1 << bar); 1508 } 1509 1510 return (0); 1511 err: 1512 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1513 if ((mappings & (1 << bar)) != 0) { 1514 res = dr->mmio_table[bar]; 1515 if (res == NULL) 1516 continue; 1517 pci_iounmap(pdev, res); 1518 } 1519 } 1520 1521 return (-EINVAL); 1522 } 1523 1524 static inline int 1525 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1526 { 1527 uint32_t requests, req_mask; 1528 int bar, error; 1529 1530 /* Request all the BARs ("regions") we do not iomap. */ 1531 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1532 for (bar = requests = 0; requests != req_mask; bar++) { 1533 if ((req_mask & (1 << bar)) == 0) 1534 continue; 1535 error = pci_request_region(pdev, bar, name); 1536 if (error != 0 && error != -ENODEV) 1537 goto err; 1538 requests |= (1 << bar); 1539 } 1540 1541 error = pcim_iomap_regions(pdev, mask, name); 1542 if (error != 0) 1543 goto err; 1544 1545 return (0); 1546 1547 err: 1548 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1549 if ((requests & (1 << bar)) != 0) 1550 pci_release_region(pdev, bar); 1551 } 1552 1553 return (-EINVAL); 1554 } 1555 1556 /* This is a FreeBSD extension so we can use bus_*(). */ 1557 static inline void 1558 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1559 { 1560 pdev->want_iomap_res = true; 1561 } 1562 1563 static inline bool 1564 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1565 { 1566 1567 return (false); 1568 } 1569 1570 static inline void * 1571 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1572 { 1573 1574 return (NULL); 1575 } 1576 1577 static inline void 1578 pci_ignore_hotplug(struct pci_dev *pdev) 1579 { 1580 } 1581 1582 static inline const char * 1583 pci_power_name(pci_power_t state) 1584 { 1585 int pstate = state + 1; 1586 1587 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1588 return (pci_power_names[pstate]); 1589 else 1590 return (pci_power_names[0]); 1591 } 1592 1593 static inline int 1594 pcie_get_readrq(struct pci_dev *dev) 1595 { 1596 u16 ctl; 1597 1598 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1599 return (-EINVAL); 1600 1601 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1602 } 1603 1604 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1605