1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2025 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 #include <linux/device/driver.h> 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_private.h> 49 50 #include <machine/resource.h> 51 52 #include <linux/list.h> 53 #include <linux/dmapool.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/compiler.h> 56 #include <linux/errno.h> 57 #include <asm/atomic.h> 58 #include <asm/memtype.h> 59 #include <linux/device.h> 60 #include <linux/pci_ids.h> 61 #include <linux/pm.h> 62 #include <linux/interrupt.h> 63 64 /* 65 * <linux/ioport.h> should be included here, like Linux, but we can't have that 66 * because Linux `struct resource` definition would conflict with FreeBSD 67 * native definition. 68 * 69 * At least the amdgpu DRM driver (amdgpu_isp.c at the time of this writing) 70 * relies on this indirect include to get the definition of Linux `struct 71 * resource`. As a workaround, we include <linux/ioport.h> from 72 * <linux/mfd/core.h>. 73 */ 74 75 #include <linux/kernel.h> /* pr_debug */ 76 77 struct pci_device_id { 78 uint32_t vendor; 79 uint32_t device; 80 uint32_t subvendor; 81 uint32_t subdevice; 82 uint32_t class; 83 uint32_t class_mask; 84 uintptr_t driver_data; 85 }; 86 87 #define MODULE_DEVICE_TABLE_BUS_pci(_bus, _table) \ 88 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 89 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 90 91 #define PCI_ANY_ID -1U 92 93 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 94 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 95 #define PCI_FUNC(devfn) ((devfn) & 0x07) 96 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 97 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 98 99 #define PCI_VDEVICE(_vendor, _device) \ 100 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 101 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 102 .class = 0, .class_mask = 0 103 #define PCI_DEVICE(_vendor, _device) \ 104 .vendor = (_vendor), .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 107 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 108 109 #define PCI_STD_NUM_BARS 6 110 #define PCI_BASE_ADDRESS_0 PCIR_BARS 111 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 112 #define PCI_VENDOR_ID PCIR_VENDOR 113 #define PCI_DEVICE_ID PCIR_DEVICE 114 #define PCI_COMMAND PCIR_COMMAND 115 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 116 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 117 #define PCI_PRIMARY_BUS PCIR_PRIBUS_1 118 #define PCI_SECONDARY_BUS PCIR_SECBUS_1 119 #define PCI_SUBORDINATE_BUS PCIR_SUBBUS_1 120 #define PCI_SEC_LATENCY_TIMER PCIR_SECLAT_1 121 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 122 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 123 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 124 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 125 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 126 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 127 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 128 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 129 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 130 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 131 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 132 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 133 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 134 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 135 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 136 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 137 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 138 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 139 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 140 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 141 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 142 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 143 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 144 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 145 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 146 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 147 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 148 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 149 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 150 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 151 #define PCI_EXP_TYPE_UPSTREAM PCIEM_TYPE_UPSTREAM_PORT /* Upstream Port */ 152 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 153 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 154 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 155 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 156 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 157 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 158 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 159 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 160 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 161 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 162 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 163 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 164 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 165 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 166 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 167 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 168 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 169 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 170 #define PCI_EXP_LNKCTL2_TLS 0x000f 171 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 172 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 173 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 174 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 175 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 176 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 177 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 178 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 179 180 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 181 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 182 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 183 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 184 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 185 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 186 187 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 188 #define PCI_EXP_DEVSTA_TRPND 0x0020 189 190 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 191 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 192 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 193 194 enum pci_bus_speed { 195 PCI_SPEED_UNKNOWN = -1, 196 PCIE_SPEED_2_5GT, 197 PCIE_SPEED_5_0GT, 198 PCIE_SPEED_8_0GT, 199 PCIE_SPEED_16_0GT, 200 PCIE_SPEED_32_0GT, 201 PCIE_SPEED_64_0GT, 202 }; 203 204 enum pcie_link_width { 205 PCIE_LNK_WIDTH_RESRV = 0x00, 206 PCIE_LNK_X1 = 0x01, 207 PCIE_LNK_X2 = 0x02, 208 PCIE_LNK_X4 = 0x04, 209 PCIE_LNK_X8 = 0x08, 210 PCIE_LNK_X12 = 0x0c, 211 PCIE_LNK_X16 = 0x10, 212 PCIE_LNK_X32 = 0x20, 213 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 214 }; 215 216 #define PCIE_LINK_STATE_L0S 0x00000001 217 #define PCIE_LINK_STATE_L1 0x00000002 218 #define PCIE_LINK_STATE_CLKPM 0x00000004 219 220 typedef int pci_power_t; 221 222 #define PCI_D0 PCI_POWERSTATE_D0 223 #define PCI_D1 PCI_POWERSTATE_D1 224 #define PCI_D2 PCI_POWERSTATE_D2 225 #define PCI_D3hot PCI_POWERSTATE_D3_HOT 226 #define PCI_D3cold PCI_POWERSTATE_D3_COLD 227 228 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 229 230 extern const char *pci_power_names[6]; 231 232 #define PCI_ERR_UNCOR_STATUS PCIR_AER_UC_STATUS 233 #define PCI_ERR_COR_STATUS PCIR_AER_COR_STATUS 234 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 235 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 236 237 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 238 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 239 240 #define PCI_L1SS_CTL1 0x8 241 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 242 243 #define PCI_IRQ_INTX 0x01 244 #define PCI_IRQ_MSI 0x02 245 #define PCI_IRQ_MSIX 0x04 246 #define PCI_IRQ_AFFINITY 0x08 247 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_INTX) 248 249 #if defined(LINUXKPI_VERSION) && (LINUXKPI_VERSION <= 61000) 250 #define PCI_IRQ_LEGACY PCI_IRQ_INTX 251 #endif 252 253 /* 254 * Linux PCI code uses `PCI_SET_ERROR_RESPONSE()` to indicate to the caller of 255 * a `pci_read_*()` function that the read failed. An example of failure is 256 * whether the device was disconnected. It is a bit weird because Linux 257 * `pci_read_*()` can return an error value, as the read value is stored in a 258 * integer passed by pointer. 259 * 260 * We don't set PCI_ERROR_RESPONSE anywhere as of this commit, but the DRM 261 * drivers started to use `PCI_POSSIBLE_ERROR()`. 262 */ 263 #define PCI_ERROR_RESPONSE (~0ULL) 264 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 265 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 266 267 struct pci_dev; 268 269 struct pci_driver { 270 struct list_head node; 271 char *name; 272 const struct pci_device_id *id_table; 273 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 274 void (*remove)(struct pci_dev *dev); 275 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 276 int (*resume) (struct pci_dev *dev); /* Device woken up */ 277 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 278 driver_t bsddriver; 279 devclass_t bsdclass; 280 struct device_driver driver; 281 const struct pci_error_handlers *err_handler; 282 bool isdrm; 283 int bsd_probe_return; 284 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 285 const nvlist_t *pf_config); 286 void (*bsd_iov_uninit)(device_t dev); 287 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 288 const nvlist_t *vf_config); 289 }; 290 291 struct pci_bus { 292 struct pci_dev *self; 293 /* struct pci_bus *parent */ 294 int domain; 295 int number; 296 }; 297 298 extern struct list_head pci_drivers; 299 extern struct list_head pci_devices; 300 extern spinlock_t pci_lock; 301 302 #define __devexit_p(x) x 303 304 #define module_pci_driver(_drv) \ 305 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver) 306 307 struct msi_msg { 308 uint32_t data; 309 }; 310 311 struct pci_msi_desc { 312 struct { 313 bool is_64; 314 } msi_attrib; 315 }; 316 317 struct msi_desc { 318 struct msi_msg msg; 319 struct pci_msi_desc pci; 320 }; 321 322 struct msix_entry { 323 int entry; 324 int vector; 325 }; 326 327 /* 328 * If we find drivers accessing this from multiple KPIs we may have to 329 * refcount objects of this structure. 330 */ 331 struct resource; 332 struct pci_mmio_region { 333 TAILQ_ENTRY(pci_mmio_region) next; 334 struct resource *res; 335 int rid; 336 int type; 337 }; 338 339 struct pci_dev { 340 struct device dev; 341 struct list_head links; 342 struct pci_driver *pdrv; 343 struct pci_bus *bus; 344 struct pci_dev *root; 345 pci_power_t current_state; 346 uint16_t device; 347 uint16_t vendor; 348 uint16_t subsystem_vendor; 349 uint16_t subsystem_device; 350 unsigned int irq; 351 unsigned int devfn; 352 uint32_t class; 353 uint8_t revision; 354 uint8_t msi_cap; 355 uint8_t msix_cap; 356 bool managed; /* devres "pcim_*(). */ 357 bool want_iomap_res; 358 bool msi_enabled; 359 bool msix_enabled; 360 phys_addr_t rom; 361 size_t romlen; 362 struct msi_desc **msi_desc; 363 char *path_name; 364 spinlock_t pcie_cap_lock; 365 366 TAILQ_HEAD(, pci_mmio_region) mmio; 367 }; 368 369 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 370 unsigned int flags); 371 bool pci_device_is_present(struct pci_dev *pdev); 372 373 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 374 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 375 void *linuxkpi_pci_iomap_range(struct pci_dev *, int, 376 unsigned long, unsigned long); 377 void *linuxkpi_pci_iomap(struct pci_dev *, int, unsigned long); 378 void *linuxkpi_pcim_iomap(struct pci_dev *, int, unsigned long); 379 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 380 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 381 const char *name); 382 int linuxkpi_pci_request_region(struct pci_dev *, int, const char *); 383 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 384 int linuxkpi_pcim_request_all_regions(struct pci_dev *, const char *); 385 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 386 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 387 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 388 int nreq); 389 390 /* Internal helper function(s). */ 391 struct pci_dev *lkpinew_pci_dev(device_t); 392 void lkpi_pci_devres_release(struct device *, void *); 393 struct pci_dev *lkpi_pci_get_device(uint32_t, uint32_t, struct pci_dev *); 394 struct msi_desc *lkpi_pci_msi_desc_alloc(unsigned int); 395 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 396 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 397 398 #define pci_err(pdev, fmt, ...) \ 399 dev_err(&(pdev)->dev, fmt, ##__VA_ARGS__) 400 #define pci_info(pdev, fmt, ...) \ 401 dev_info(&(pdev)->dev, fmt, ##__VA_ARGS__) 402 403 static inline bool 404 dev_is_pci(struct device *dev) 405 { 406 return (is_pci_device(dev->bsddev)); 407 } 408 409 static inline uint16_t 410 pci_dev_id(struct pci_dev *pdev) 411 { 412 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 413 } 414 415 static inline int 416 pci_resource_type(struct pci_dev *pdev, int bar) 417 { 418 struct pci_map *pm; 419 420 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 421 if (!pm) 422 return (-1); 423 424 if (PCI_BAR_IO(pm->pm_value)) 425 return (SYS_RES_IOPORT); 426 else 427 return (SYS_RES_MEMORY); 428 } 429 430 /* 431 * All drivers just seem to want to inspect the type not flags. 432 */ 433 static inline int 434 pci_resource_flags(struct pci_dev *pdev, int bar) 435 { 436 int type; 437 438 type = pci_resource_type(pdev, bar); 439 if (type < 0) 440 return (0); 441 return (1 << type); 442 } 443 444 static inline int 445 pci_select_bars(struct pci_dev *pdev, unsigned long flags) 446 { 447 int bars, bar; 448 449 bars = 0; 450 /* We only support BARs here; Linux may support more types. */ 451 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 452 int bar_flags; 453 454 bar_flags = pci_resource_flags(pdev, bar); 455 if ((bar_flags & flags) != 0) 456 bars |= (1 << bar); 457 } 458 459 return (bars); 460 } 461 462 static inline const char * 463 pci_name(struct pci_dev *d) 464 { 465 return d->path_name; 466 } 467 468 static inline void * 469 pci_get_drvdata(struct pci_dev *pdev) 470 { 471 472 return dev_get_drvdata(&pdev->dev); 473 } 474 475 static inline void 476 pci_set_drvdata(struct pci_dev *pdev, void *data) 477 { 478 479 dev_set_drvdata(&pdev->dev, data); 480 } 481 482 static inline struct pci_dev * 483 pci_dev_get(struct pci_dev *pdev) 484 { 485 486 if (pdev != NULL) 487 get_device(&pdev->dev); 488 return (pdev); 489 } 490 491 static __inline void 492 pci_dev_put(struct pci_dev *pdev) 493 { 494 495 if (pdev != NULL) 496 put_device(&pdev->dev); 497 } 498 499 static inline int 500 pci_enable_device(struct pci_dev *pdev) 501 { 502 503 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 504 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 505 return (0); 506 } 507 508 static inline void 509 pci_disable_device(struct pci_dev *pdev) 510 { 511 512 pci_disable_busmaster(pdev->dev.bsddev); 513 } 514 515 static inline int 516 pci_set_master(struct pci_dev *pdev) 517 { 518 519 pci_enable_busmaster(pdev->dev.bsddev); 520 return (0); 521 } 522 523 static inline int 524 pci_set_power_state(struct pci_dev *pdev, int state) 525 { 526 527 pci_set_powerstate(pdev->dev.bsddev, state); 528 return (0); 529 } 530 531 static inline int 532 pci_clear_master(struct pci_dev *pdev) 533 { 534 535 pci_disable_busmaster(pdev->dev.bsddev); 536 return (0); 537 } 538 539 static inline bool 540 pci_is_root_bus(struct pci_bus *pbus) 541 { 542 543 return (pbus->self == NULL); 544 } 545 546 static inline struct pci_dev * 547 pci_upstream_bridge(struct pci_dev *pdev) 548 { 549 550 if (pci_is_root_bus(pdev->bus)) 551 return (NULL); 552 553 /* 554 * If we do not have a (proper) "upstream bridge" set, e.g., we point 555 * to ourselves, try to handle this case on the fly like we do 556 * for pcie_find_root_port(). 557 */ 558 if (pdev == pdev->bus->self) { 559 device_t bridge; 560 561 /* 562 * In the case of DRM drivers, the passed device is a child of 563 * `vgapci`. We want to start the lookup from `vgapci`, so the 564 * parent of the passed `drmn`. 565 * 566 * We can use the `isdrm` flag to determine this. 567 */ 568 bridge = pdev->dev.bsddev; 569 if (pdev->pdrv != NULL && pdev->pdrv->isdrm) 570 bridge = device_get_parent(bridge); 571 if (bridge == NULL) 572 goto done; 573 574 bridge = device_get_parent(bridge); 575 if (bridge == NULL) 576 goto done; 577 bridge = device_get_parent(bridge); 578 if (bridge == NULL) 579 goto done; 580 if (!is_pci_device(bridge)) 581 goto done; 582 583 /* 584 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 585 * for it so it can be returned. 586 */ 587 pdev->bus->self = lkpinew_pci_dev(bridge); 588 } 589 done: 590 return (pdev->bus->self); 591 } 592 593 #define pci_request_region(pdev, bar, res_name) \ 594 linuxkpi_pci_request_region(pdev, bar, res_name) 595 #define pci_release_region(pdev, bar) \ 596 linuxkpi_pci_release_region(pdev, bar) 597 #define pci_request_regions(pdev, res_name) \ 598 linuxkpi_pci_request_regions(pdev, res_name) 599 #define pci_release_regions(pdev) \ 600 linuxkpi_pci_release_regions(pdev) 601 #define pcim_request_all_regions(pdev, name) \ 602 linuxkpi_pcim_request_all_regions(pdev, name) 603 604 static inline void 605 lkpi_pci_disable_msix(struct pci_dev *pdev) 606 { 607 608 pci_release_msi(pdev->dev.bsddev); 609 610 /* 611 * The MSIX IRQ numbers associated with this PCI device are no 612 * longer valid and might be re-assigned. Make sure 613 * lkpi_pci_find_irq_dev() does no longer see them by 614 * resetting their references to zero: 615 */ 616 pdev->dev.irq_start = 0; 617 pdev->dev.irq_end = 0; 618 pdev->msix_enabled = false; 619 } 620 /* Only for consistency. No conflict on that one. */ 621 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 622 623 static inline void 624 lkpi_pci_disable_msi(struct pci_dev *pdev) 625 { 626 627 pci_release_msi(pdev->dev.bsddev); 628 629 pdev->dev.irq_start = 0; 630 pdev->dev.irq_end = 0; 631 pdev->irq = pdev->dev.irq; 632 pdev->msi_enabled = false; 633 } 634 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 635 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 636 637 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 638 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 639 640 static inline bus_addr_t 641 pci_bus_address(struct pci_dev *pdev, int bar) 642 { 643 644 return (pci_resource_start(pdev, bar)); 645 } 646 647 #define PCI_CAP_ID_EXP PCIY_EXPRESS 648 #define PCI_CAP_ID_PCIX PCIY_PCIX 649 #define PCI_CAP_ID_AGP PCIY_AGP 650 #define PCI_CAP_ID_PM PCIY_PMG 651 652 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 653 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 654 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 655 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 656 #define PCI_EXP_LNKSTA PCIER_LINK_STA 657 658 static inline int 659 pci_find_capability(struct pci_dev *pdev, int capid) 660 { 661 int reg; 662 663 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 664 return (0); 665 return (reg); 666 } 667 668 static inline int pci_pcie_cap(struct pci_dev *dev) 669 { 670 return pci_find_capability(dev, PCI_CAP_ID_EXP); 671 } 672 673 static inline int 674 pci_find_ext_capability(struct pci_dev *pdev, int capid) 675 { 676 int reg; 677 678 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 679 return (0); 680 return (reg); 681 } 682 683 static __inline bool 684 pci_pme_capable(struct pci_dev *pdev, pci_power_t state) 685 { 686 return (pci_has_pme(pdev->dev.bsddev, state)); 687 } 688 689 static inline int 690 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 691 { 692 693 if (!pci_enable_aspm) 694 return (-EPERM); 695 696 return (-ENXIO); 697 } 698 699 static inline int 700 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 701 { 702 703 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 704 return (0); 705 } 706 707 static inline int 708 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 709 { 710 711 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 712 return (0); 713 } 714 715 static inline int 716 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 717 { 718 719 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 720 return (0); 721 } 722 723 static inline int 724 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 725 { 726 727 pci_write_config(pdev->dev.bsddev, where, val, 1); 728 return (0); 729 } 730 731 static inline int 732 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 733 { 734 735 pci_write_config(pdev->dev.bsddev, where, val, 2); 736 return (0); 737 } 738 739 static inline int 740 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 741 { 742 743 pci_write_config(pdev->dev.bsddev, where, val, 4); 744 return (0); 745 } 746 747 int linux_pci_register_driver(struct pci_driver *pdrv); 748 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 749 void linux_pci_unregister_driver(struct pci_driver *pdrv); 750 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 751 752 #define pci_register_driver(pdrv) \ 753 linux_pci_register_driver(pdrv) 754 #define pci_unregister_driver(pdrv) \ 755 linux_pci_unregister_driver(pdrv) 756 757 /* 758 * Enable msix, positive errors indicate actual number of available 759 * vectors. Negative errors are failures. 760 * 761 * NB: define added to prevent this definition of pci_enable_msix from 762 * clashing with the native FreeBSD version. 763 */ 764 #define pci_enable_msix(...) \ 765 linuxkpi_pci_enable_msix(__VA_ARGS__) 766 767 #define pci_enable_msix_range(...) \ 768 linux_pci_enable_msix_range(__VA_ARGS__) 769 770 static inline int 771 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 772 int minvec, int maxvec) 773 { 774 int nvec = maxvec; 775 int rc; 776 777 if (maxvec < minvec) 778 return (-ERANGE); 779 780 do { 781 rc = pci_enable_msix(dev, entries, nvec); 782 if (rc < 0) { 783 return (rc); 784 } else if (rc > 0) { 785 if (rc < minvec) 786 return (-ENOSPC); 787 nvec = rc; 788 } 789 } while (rc); 790 return (nvec); 791 } 792 793 #define pci_enable_msi(pdev) \ 794 linux_pci_enable_msi(pdev) 795 796 static inline int 797 pci_enable_msi(struct pci_dev *pdev) 798 { 799 800 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 801 } 802 803 static inline int 804 pci_channel_offline(struct pci_dev *pdev) 805 { 806 807 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 808 } 809 810 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 811 { 812 return -ENODEV; 813 } 814 815 static inline void pci_disable_sriov(struct pci_dev *dev) 816 { 817 } 818 819 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \ 820 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) 821 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 822 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 823 #define pcim_iomap(pdev, bar, maxlen) \ 824 linuxkpi_pcim_iomap(pdev, bar, maxlen) 825 #define pci_iounmap(pdev, res) \ 826 linuxkpi_pci_iounmap(pdev, res) 827 828 static inline void 829 lkpi_pci_save_state(struct pci_dev *pdev) 830 { 831 832 pci_save_state(pdev->dev.bsddev); 833 } 834 835 static inline void 836 lkpi_pci_restore_state(struct pci_dev *pdev) 837 { 838 839 pci_restore_state(pdev->dev.bsddev); 840 } 841 842 #define pci_save_state(dev) lkpi_pci_save_state(dev) 843 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 844 845 static inline int 846 linuxkpi_pci_enable_wake(struct pci_dev *pdev, pci_power_t state, bool ena) 847 { 848 /* 849 * We do not currently support this in device.h either to 850 * check if the device is allowed to wake up in first place. 851 */ 852 pr_debug("%s: TODO\n", __func__); 853 return (0); 854 } 855 #define pci_enable_wake(dev, state, ena) \ 856 linuxkpi_pci_enable_wake(dev, state, ena) 857 858 static inline int 859 pci_reset_function(struct pci_dev *pdev) 860 { 861 862 return (-ENOSYS); 863 } 864 865 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 866 const struct pci_device_id _table[] __devinitdata 867 868 /* XXX This should not be necessary. */ 869 #define pcix_set_mmrbc(d, v) 0 870 #define pcix_get_max_mmrbc(d) 0 871 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 872 873 #define PCI_DMA_BIDIRECTIONAL 0 874 #define PCI_DMA_TODEVICE 1 875 #define PCI_DMA_FROMDEVICE 2 876 #define PCI_DMA_NONE 3 877 878 #define pci_pool dma_pool 879 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 880 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 881 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 882 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 883 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 884 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 885 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 886 _size, _vaddr, _dma_handle) 887 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 888 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 889 _sg, _nents, (enum dma_data_direction)_dir) 890 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 891 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 892 (_ptr), (_size), (enum dma_data_direction)_dir) 893 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 894 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 895 _addr, _size, (enum dma_data_direction)_dir) 896 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 897 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 898 _sg, _nents, (enum dma_data_direction)_dir) 899 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 900 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 901 _offset, _size, (enum dma_data_direction)_dir) 902 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 903 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 904 _dma_address, _size, (enum dma_data_direction)_dir) 905 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 906 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 907 dma_mapping_error(&(_pdev)->dev, _dma_addr) 908 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 909 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 910 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 911 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 912 #define pci_unmap_addr dma_unmap_addr 913 #define pci_unmap_addr_set dma_unmap_addr_set 914 #define pci_unmap_len dma_unmap_len 915 #define pci_unmap_len_set dma_unmap_len_set 916 917 void *linuxkpi_pci_map_rom(struct pci_dev *pdev, size_t *size); 918 void linuxkpi_pci_unmap_rom(struct pci_dev *pdev, void *rom); 919 #define pci_map_rom(pdev, size) linuxkpi_pci_map_rom(pdev, size) 920 #define pci_unmap_rom(pdev, rom) linuxkpi_pci_unmap_rom(pdev, rom) 921 922 typedef unsigned int __bitwise pci_channel_state_t; 923 typedef unsigned int __bitwise pci_ers_result_t; 924 925 enum pci_channel_state { 926 pci_channel_io_normal = 1, 927 pci_channel_io_frozen = 2, 928 pci_channel_io_perm_failure = 3, 929 }; 930 931 enum pci_ers_result { 932 PCI_ERS_RESULT_NONE = 1, 933 PCI_ERS_RESULT_CAN_RECOVER = 2, 934 PCI_ERS_RESULT_NEED_RESET = 3, 935 PCI_ERS_RESULT_DISCONNECT = 4, 936 PCI_ERS_RESULT_RECOVERED = 5, 937 }; 938 939 /* PCI bus error event callbacks */ 940 struct pci_error_handlers { 941 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 942 enum pci_channel_state error); 943 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 944 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 945 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 946 void (*resume)(struct pci_dev *dev); 947 void (*reset_prepare)(struct pci_dev *); 948 void (*reset_done)(struct pci_dev *); 949 }; 950 951 /* FreeBSD does not support SRIOV - yet */ 952 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 953 { 954 return dev; 955 } 956 957 static inline bool pci_is_pcie(struct pci_dev *dev) 958 { 959 return !!pci_pcie_cap(dev); 960 } 961 962 static inline u16 pcie_flags_reg(struct pci_dev *dev) 963 { 964 int pos; 965 u16 reg16; 966 967 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 968 if (!pos) 969 return 0; 970 971 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 972 973 return reg16; 974 } 975 976 static inline int pci_pcie_type(struct pci_dev *dev) 977 { 978 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 979 } 980 981 static inline int pcie_cap_version(struct pci_dev *dev) 982 { 983 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 984 } 985 986 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 987 { 988 int type = pci_pcie_type(dev); 989 990 return pcie_cap_version(dev) > 1 || 991 type == PCI_EXP_TYPE_ROOT_PORT || 992 type == PCI_EXP_TYPE_ENDPOINT || 993 type == PCI_EXP_TYPE_LEG_END; 994 } 995 996 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 997 { 998 return true; 999 } 1000 1001 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1002 { 1003 int type = pci_pcie_type(dev); 1004 1005 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1006 (type == PCI_EXP_TYPE_DOWNSTREAM && 1007 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1008 } 1009 1010 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1011 { 1012 int type = pci_pcie_type(dev); 1013 1014 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1015 type == PCI_EXP_TYPE_RC_EC; 1016 } 1017 1018 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1019 { 1020 if (!pci_is_pcie(dev)) 1021 return false; 1022 1023 switch (pos) { 1024 case PCI_EXP_FLAGS_TYPE: 1025 return true; 1026 case PCI_EXP_DEVCAP: 1027 case PCI_EXP_DEVCTL: 1028 case PCI_EXP_DEVSTA: 1029 return pcie_cap_has_devctl(dev); 1030 case PCI_EXP_LNKCAP: 1031 case PCI_EXP_LNKCTL: 1032 case PCI_EXP_LNKSTA: 1033 return pcie_cap_has_lnkctl(dev); 1034 case PCI_EXP_SLTCAP: 1035 case PCI_EXP_SLTCTL: 1036 case PCI_EXP_SLTSTA: 1037 return pcie_cap_has_sltctl(dev); 1038 case PCI_EXP_RTCTL: 1039 case PCI_EXP_RTCAP: 1040 case PCI_EXP_RTSTA: 1041 return pcie_cap_has_rtctl(dev); 1042 case PCI_EXP_DEVCAP2: 1043 case PCI_EXP_DEVCTL2: 1044 case PCI_EXP_LNKCAP2: 1045 case PCI_EXP_LNKCTL2: 1046 case PCI_EXP_LNKSTA2: 1047 return pcie_cap_version(dev) > 1; 1048 default: 1049 return false; 1050 } 1051 } 1052 1053 static inline int 1054 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1055 { 1056 *dst = 0; 1057 if (pos & 3) 1058 return -EINVAL; 1059 1060 if (!pcie_capability_reg_implemented(dev, pos)) 1061 return -EINVAL; 1062 1063 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1064 } 1065 1066 static inline int 1067 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1068 { 1069 *dst = 0; 1070 if (pos & 3) 1071 return -EINVAL; 1072 1073 if (!pcie_capability_reg_implemented(dev, pos)) 1074 return -EINVAL; 1075 1076 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1077 } 1078 1079 static inline int 1080 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1081 { 1082 if (pos & 1) 1083 return -EINVAL; 1084 1085 if (!pcie_capability_reg_implemented(dev, pos)) 1086 return 0; 1087 1088 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1089 } 1090 1091 static inline int 1092 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1093 uint16_t clear, uint16_t set) 1094 { 1095 int error; 1096 uint16_t v; 1097 1098 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1099 spin_lock(&dev->pcie_cap_lock); 1100 1101 error = pcie_capability_read_word(dev, pos, &v); 1102 if (error == 0) { 1103 v &= ~clear; 1104 v |= set; 1105 error = pcie_capability_write_word(dev, pos, v); 1106 } 1107 1108 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1109 spin_unlock(&dev->pcie_cap_lock); 1110 1111 return (error); 1112 } 1113 1114 static inline int 1115 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1116 { 1117 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1118 } 1119 1120 static inline int 1121 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1122 { 1123 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1124 } 1125 1126 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1127 enum pci_bus_speed *speed, enum pcie_link_width *width) 1128 { 1129 *speed = PCI_SPEED_UNKNOWN; 1130 *width = PCIE_LNK_WIDTH_UNKNOWN; 1131 return (0); 1132 } 1133 1134 static inline int 1135 pci_num_vf(struct pci_dev *dev) 1136 { 1137 return (0); 1138 } 1139 1140 static inline enum pci_bus_speed 1141 pcie_get_speed_cap(struct pci_dev *dev) 1142 { 1143 struct pci_dev *pbus; 1144 device_t root; 1145 uint32_t lnkcap, lnkcap2; 1146 int error, pos; 1147 1148 /* 1149 * We should always be called on a PCI device. 1150 * The only current consumer I could find was amdgpu which either 1151 * calls us directly on a pdev(drmn?) or with the result of 1152 * pci_upstream_bridge(). 1153 * 1154 * Treat "drmn" as special again as it is not a PCI device. 1155 */ 1156 if (dev->pdrv != NULL && dev->pdrv->isdrm) { 1157 pbus = pci_upstream_bridge(dev); 1158 if (pbus == NULL) 1159 return (PCI_SPEED_UNKNOWN); 1160 } else 1161 pbus = dev; 1162 1163 /* "root" may be misleading as it may not be that. */ 1164 root = pbus->dev.bsddev; 1165 1166 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1167 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1168 return (PCI_SPEED_UNKNOWN); 1169 1170 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1171 return (PCI_SPEED_UNKNOWN); 1172 1173 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1174 1175 if (lnkcap2) { /* PCIe r3.0-compliant */ 1176 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1177 return (PCIE_SPEED_2_5GT); 1178 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1179 return (PCIE_SPEED_5_0GT); 1180 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1181 return (PCIE_SPEED_8_0GT); 1182 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1183 return (PCIE_SPEED_16_0GT); 1184 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1185 return (PCIE_SPEED_32_0GT); 1186 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1187 return (PCIE_SPEED_64_0GT); 1188 } else { /* pre-r3.0 */ 1189 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1190 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1191 return (PCIE_SPEED_2_5GT); 1192 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1193 return (PCIE_SPEED_5_0GT); 1194 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1195 return (PCIE_SPEED_8_0GT); 1196 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1197 return (PCIE_SPEED_16_0GT); 1198 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1199 return (PCIE_SPEED_32_0GT); 1200 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1201 return (PCIE_SPEED_64_0GT); 1202 } 1203 return (PCI_SPEED_UNKNOWN); 1204 } 1205 1206 static inline enum pcie_link_width 1207 pcie_get_width_cap(struct pci_dev *dev) 1208 { 1209 uint32_t lnkcap; 1210 1211 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1212 if (lnkcap) 1213 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1214 1215 return (PCIE_LNK_WIDTH_UNKNOWN); 1216 } 1217 1218 static inline int 1219 pcie_get_mps(struct pci_dev *dev) 1220 { 1221 return (pci_get_max_payload(dev->dev.bsddev)); 1222 } 1223 1224 static inline uint32_t 1225 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1226 { 1227 1228 switch(spd) { 1229 case PCIE_SPEED_64_0GT: 1230 return (64000 * 128 / 130); 1231 case PCIE_SPEED_32_0GT: 1232 return (32000 * 128 / 130); 1233 case PCIE_SPEED_16_0GT: 1234 return (16000 * 128 / 130); 1235 case PCIE_SPEED_8_0GT: 1236 return (8000 * 128 / 130); 1237 case PCIE_SPEED_5_0GT: 1238 return (5000 * 8 / 10); 1239 case PCIE_SPEED_2_5GT: 1240 return (2500 * 8 / 10); 1241 default: 1242 return (0); 1243 } 1244 } 1245 1246 static inline uint32_t 1247 pcie_bandwidth_available(struct pci_dev *pdev, 1248 struct pci_dev **limiting, 1249 enum pci_bus_speed *speed, 1250 enum pcie_link_width *width) 1251 { 1252 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1253 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1254 1255 if (speed) 1256 *speed = nspeed; 1257 if (width) 1258 *width = nwidth; 1259 1260 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1261 } 1262 1263 static inline bool 1264 pcie_aspm_enabled(struct pci_dev *pdev) 1265 { 1266 return (false); 1267 } 1268 1269 static inline struct pci_dev * 1270 pcie_find_root_port(struct pci_dev *pdev) 1271 { 1272 device_t root; 1273 1274 if (pdev->root != NULL) 1275 return (pdev->root); 1276 1277 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1278 if (root == NULL) 1279 return (NULL); 1280 1281 pdev->root = lkpinew_pci_dev(root); 1282 return (pdev->root); 1283 } 1284 1285 /* This is needed when people rip out the device "HotPlug". */ 1286 static inline void 1287 pci_lock_rescan_remove(void) 1288 { 1289 } 1290 1291 static inline void 1292 pci_unlock_rescan_remove(void) 1293 { 1294 } 1295 1296 static __inline void 1297 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1298 { 1299 } 1300 1301 static inline int 1302 pci_rescan_bus(struct pci_bus *pbus) 1303 { 1304 device_t *devlist, parent; 1305 int devcount, error; 1306 1307 if (!device_is_attached(pbus->self->dev.bsddev)) 1308 return (0); 1309 /* pci_rescan_method() will work on the pcib (parent). */ 1310 error = BUS_RESCAN(pbus->self->dev.bsddev); 1311 if (error != 0) 1312 return (0); 1313 1314 parent = device_get_parent(pbus->self->dev.bsddev); 1315 error = device_get_children(parent, &devlist, &devcount); 1316 if (error != 0) 1317 return (0); 1318 if (devcount != 0) 1319 free(devlist, M_TEMP); 1320 1321 return (devcount); 1322 } 1323 1324 /* 1325 * The following functions can be used to attach/detach the LinuxKPI's 1326 * PCI device runtime. The pci_driver and pci_device_id pointer is 1327 * allowed to be NULL. Other pointers must be all valid. 1328 * The pci_dev structure should be zero-initialized before passed 1329 * to the linux_pci_attach_device function. 1330 */ 1331 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1332 const struct pci_device_id *, struct pci_dev *); 1333 extern int linux_pci_detach_device(struct pci_dev *); 1334 1335 static inline int 1336 pci_dev_present(const struct pci_device_id *cur) 1337 { 1338 while (cur != NULL && (cur->vendor || cur->device)) { 1339 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1340 return (1); 1341 } 1342 cur++; 1343 } 1344 return (0); 1345 } 1346 1347 static inline bool 1348 pci_dev_is_disconnected(const struct pci_dev *pdev) 1349 { 1350 pr_debug("TODO: %s\n", __func__); 1351 return (false); 1352 } 1353 1354 static inline const struct pci_device_id * 1355 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 1356 { 1357 if (ids == NULL) 1358 return (NULL); 1359 1360 for (; 1361 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0; 1362 ids++) 1363 if ((ids->vendor == PCI_ANY_ID || 1364 ids->vendor == pdev->vendor) && 1365 (ids->device == PCI_ANY_ID || 1366 ids->device == pdev->device) && 1367 (ids->subvendor == PCI_ANY_ID || 1368 ids->subvendor == pdev->subsystem_vendor) && 1369 (ids->subdevice == PCI_ANY_ID || 1370 ids->subdevice == pdev->subsystem_device) && 1371 ((ids->class ^ pdev->class) & ids->class_mask) == 0) 1372 return (ids); 1373 1374 return (NULL); 1375 } 1376 1377 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1378 unsigned int bus, unsigned int devfn); 1379 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1380 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1381 1382 struct pci_dev *lkpi_pci_get_slot(struct pci_bus *, unsigned int); 1383 #ifndef WANT_NATIVE_PCI_GET_SLOT 1384 #define pci_get_slot(_pbus, _devfn) \ 1385 lkpi_pci_get_slot(_pbus, _devfn) 1386 #endif 1387 1388 static inline int 1389 pci_domain_nr(struct pci_bus *pbus) 1390 { 1391 1392 return (pbus->domain); 1393 } 1394 1395 static inline int 1396 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1397 int pos, uint32_t *val, int len) 1398 { 1399 1400 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1401 return (0); 1402 } 1403 1404 static inline int 1405 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1406 { 1407 uint32_t tmp; 1408 int ret; 1409 1410 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1411 *val = (u16)tmp; 1412 return (ret); 1413 } 1414 1415 static inline int 1416 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1417 { 1418 uint32_t tmp; 1419 int ret; 1420 1421 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1422 *val = (u8)tmp; 1423 return (ret); 1424 } 1425 1426 static inline int 1427 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1428 uint32_t val, int size) 1429 { 1430 1431 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1432 return (0); 1433 } 1434 1435 static inline int 1436 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1437 uint8_t val) 1438 { 1439 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1440 } 1441 1442 static inline int 1443 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1444 uint16_t val) 1445 { 1446 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1447 } 1448 1449 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1450 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1451 struct pci_dev *lkpi_pci_get_base_class(unsigned int class, 1452 struct pci_dev *from); 1453 #define pci_get_base_class(class, from) lkpi_pci_get_base_class(class, from) 1454 1455 /* -------------------------------------------------------------------------- */ 1456 1457 #define pcim_enable_device(pdev) \ 1458 linuxkpi_pcim_enable_device(pdev) 1459 #define pcim_iomap_table(pdev) \ 1460 linuxkpi_pcim_iomap_table(pdev) 1461 #define pcim_iomap_regions(pdev, mask, name) \ 1462 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1463 1464 static inline int 1465 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1466 { 1467 uint32_t requests, req_mask; 1468 int bar, error; 1469 1470 /* Request all the BARs ("regions") we do not iomap. */ 1471 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1472 for (bar = requests = 0; requests != req_mask; bar++) { 1473 if ((req_mask & (1 << bar)) == 0) 1474 continue; 1475 error = pci_request_region(pdev, bar, name); 1476 if (error != 0 && error != -ENODEV) 1477 goto err; 1478 requests |= (1 << bar); 1479 } 1480 1481 error = pcim_iomap_regions(pdev, mask, name); 1482 if (error != 0) 1483 goto err; 1484 1485 return (0); 1486 1487 err: 1488 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1489 if ((requests & (1 << bar)) != 0) 1490 pci_release_region(pdev, bar); 1491 } 1492 1493 return (-EINVAL); 1494 } 1495 1496 /* 1497 * We cannot simply re-define pci_get_device() as we would normally do 1498 * and then hide it in linux_pci.c as too many semi-native drivers still 1499 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1500 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1501 */ 1502 static inline struct pci_dev * 1503 linuxkpi_pci_get_device(uint32_t vendor, uint32_t device, struct pci_dev *odev) 1504 { 1505 1506 return (lkpi_pci_get_device(vendor, device, odev)); 1507 } 1508 1509 #define for_each_pci_dev(_pdev) \ 1510 while ((_pdev = linuxkpi_pci_get_device(PCI_ANY_ID, PCI_ANY_ID, _pdev)) != NULL) 1511 1512 /* This is a FreeBSD extension so we can use bus_*(). */ 1513 static inline void 1514 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1515 { 1516 pdev->want_iomap_res = true; 1517 } 1518 1519 static inline bool 1520 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1521 { 1522 1523 return (false); 1524 } 1525 1526 static inline void * 1527 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1528 { 1529 1530 return (NULL); 1531 } 1532 1533 static inline void 1534 pci_ignore_hotplug(struct pci_dev *pdev) 1535 { 1536 } 1537 1538 static inline const char * 1539 pci_power_name(pci_power_t state) 1540 { 1541 int pstate = state + 1; 1542 1543 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1544 return (pci_power_names[pstate]); 1545 else 1546 return (pci_power_names[0]); 1547 } 1548 1549 static inline int 1550 pcie_get_readrq(struct pci_dev *dev) 1551 { 1552 u16 ctl; 1553 1554 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1555 return (-EINVAL); 1556 1557 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1558 } 1559 1560 static inline bool 1561 pci_is_enabled(struct pci_dev *pdev) 1562 { 1563 1564 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1565 PCIM_CMD_BUSMASTEREN) != 0); 1566 } 1567 1568 static inline int 1569 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1570 { 1571 1572 return (0); 1573 } 1574 1575 static inline int 1576 pci_assign_resource(struct pci_dev *pdev, int bar) 1577 { 1578 1579 return (0); 1580 } 1581 1582 static inline int 1583 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1584 { 1585 1586 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1587 if (vector != 0) 1588 return (-EINVAL); 1589 return (pdev->irq); 1590 } 1591 1592 if (pdev->msix_enabled || pdev->msi_enabled) { 1593 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1594 return (-EINVAL); 1595 return (pdev->dev.irq_start + vector); 1596 } 1597 1598 return (-ENXIO); 1599 } 1600 1601 static inline int 1602 pci_msix_vec_count(struct pci_dev *pdev) 1603 { 1604 int avail; 1605 1606 avail = pci_msix_count(pdev->dev.bsddev); 1607 if (avail == 0) 1608 return (-EINVAL); 1609 return (avail); 1610 } 1611 1612 static inline int 1613 pci_wake_from_d3(struct pci_dev *pdev, bool enable) 1614 { 1615 1616 pr_debug("%s: TODO\n", __func__); 1617 return (0); 1618 } 1619 1620 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1621