1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/pciio.h> 41 #include <sys/rman.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pci_private.h> 45 46 #include <machine/resource.h> 47 48 #include <linux/list.h> 49 #include <linux/dmapool.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/compiler.h> 52 #include <linux/errno.h> 53 #include <asm/atomic.h> 54 #include <linux/device.h> 55 56 struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class; 62 uint32_t class_mask; 63 uintptr_t driver_data; 64 }; 65 66 #define MODULE_DEVICE_TABLE(bus, table) 67 68 #define PCI_BASE_CLASS_DISPLAY 0x03 69 #define PCI_CLASS_DISPLAY_VGA 0x0300 70 #define PCI_CLASS_DISPLAY_OTHER 0x0380 71 #define PCI_BASE_CLASS_BRIDGE 0x06 72 #define PCI_CLASS_BRIDGE_ISA 0x0601 73 74 #define PCI_ANY_ID -1U 75 #define PCI_VENDOR_ID_APPLE 0x106b 76 #define PCI_VENDOR_ID_ASUSTEK 0x1043 77 #define PCI_VENDOR_ID_ATI 0x1002 78 #define PCI_VENDOR_ID_DELL 0x1028 79 #define PCI_VENDOR_ID_HP 0x103c 80 #define PCI_VENDOR_ID_IBM 0x1014 81 #define PCI_VENDOR_ID_INTEL 0x8086 82 #define PCI_VENDOR_ID_MELLANOX 0x15b3 83 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 84 #define PCI_VENDOR_ID_SERVERWORKS 0x1166 85 #define PCI_VENDOR_ID_SONY 0x104d 86 #define PCI_VENDOR_ID_TOPSPIN 0x1867 87 #define PCI_VENDOR_ID_VIA 0x1106 88 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 89 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 90 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 91 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 92 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 93 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 94 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 95 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 96 #define PCI_SUBDEVICE_ID_QEMU 0x1100 97 98 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 99 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 100 #define PCI_FUNC(devfn) ((devfn) & 0x07) 101 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 102 103 #define PCI_VDEVICE(_vendor, _device) \ 104 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 #define PCI_DEVICE(_vendor, _device) \ 107 .vendor = (_vendor), .device = (_device), \ 108 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 109 110 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 111 112 #define PCI_VENDOR_ID PCIR_DEVVENDOR 113 #define PCI_COMMAND PCIR_COMMAND 114 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 115 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 116 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 117 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 118 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 119 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 120 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 121 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 122 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 123 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 124 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 125 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 126 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 127 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 128 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 129 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 130 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 131 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 132 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 133 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 134 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 135 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 136 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 137 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 138 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 139 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 140 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 141 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 142 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 143 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 144 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 145 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 146 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 147 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 148 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 149 150 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 151 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 152 #define PCI_EXP_DEVSTA_TRPND 0x0020 153 154 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 155 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 156 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 157 158 enum pci_bus_speed { 159 PCI_SPEED_UNKNOWN = -1, 160 PCIE_SPEED_2_5GT, 161 PCIE_SPEED_5_0GT, 162 PCIE_SPEED_8_0GT, 163 PCIE_SPEED_16_0GT, 164 }; 165 166 enum pcie_link_width { 167 PCIE_LNK_WIDTH_RESRV = 0x00, 168 PCIE_LNK_X1 = 0x01, 169 PCIE_LNK_X2 = 0x02, 170 PCIE_LNK_X4 = 0x04, 171 PCIE_LNK_X8 = 0x08, 172 PCIE_LNK_X12 = 0x0c, 173 PCIE_LNK_X16 = 0x10, 174 PCIE_LNK_X32 = 0x20, 175 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 176 }; 177 178 typedef int pci_power_t; 179 180 #define PCI_D0 PCI_POWERSTATE_D0 181 #define PCI_D1 PCI_POWERSTATE_D1 182 #define PCI_D2 PCI_POWERSTATE_D2 183 #define PCI_D3hot PCI_POWERSTATE_D3 184 #define PCI_D3cold 4 185 186 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 187 188 struct pci_dev; 189 190 struct pci_driver { 191 struct list_head links; 192 char *name; 193 const struct pci_device_id *id_table; 194 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 195 void (*remove)(struct pci_dev *dev); 196 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 197 int (*resume) (struct pci_dev *dev); /* Device woken up */ 198 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 199 driver_t bsddriver; 200 devclass_t bsdclass; 201 struct device_driver driver; 202 const struct pci_error_handlers *err_handler; 203 bool isdrm; 204 }; 205 206 struct pci_bus { 207 struct pci_dev *self; 208 int number; 209 }; 210 211 extern struct list_head pci_drivers; 212 extern struct list_head pci_devices; 213 extern spinlock_t pci_lock; 214 215 #define __devexit_p(x) x 216 217 struct pci_dev { 218 struct device dev; 219 struct list_head links; 220 struct pci_driver *pdrv; 221 struct pci_bus *bus; 222 uint16_t device; 223 uint16_t vendor; 224 uint16_t subsystem_vendor; 225 uint16_t subsystem_device; 226 unsigned int irq; 227 unsigned int devfn; 228 uint32_t class; 229 uint8_t revision; 230 }; 231 232 static inline struct resource_list_entry * 233 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 234 { 235 struct pci_devinfo *dinfo; 236 struct resource_list *rl; 237 238 dinfo = device_get_ivars(pdev->dev.bsddev); 239 rl = &dinfo->resources; 240 return resource_list_find(rl, type, rid); 241 } 242 243 static inline struct resource_list_entry * 244 linux_pci_get_bar(struct pci_dev *pdev, int bar) 245 { 246 struct resource_list_entry *rle; 247 248 bar = PCIR_BAR(bar); 249 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 250 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 251 return (rle); 252 } 253 254 static inline struct device * 255 linux_pci_find_irq_dev(unsigned int irq) 256 { 257 struct pci_dev *pdev; 258 struct device *found; 259 260 found = NULL; 261 spin_lock(&pci_lock); 262 list_for_each_entry(pdev, &pci_devices, links) { 263 if (irq == pdev->dev.irq || 264 (irq >= pdev->dev.msix && irq < pdev->dev.msix_max)) { 265 found = &pdev->dev; 266 break; 267 } 268 } 269 spin_unlock(&pci_lock); 270 return (found); 271 } 272 273 static inline unsigned long 274 pci_resource_start(struct pci_dev *pdev, int bar) 275 { 276 struct resource_list_entry *rle; 277 278 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 279 return (0); 280 return rle->start; 281 } 282 283 static inline unsigned long 284 pci_resource_len(struct pci_dev *pdev, int bar) 285 { 286 struct resource_list_entry *rle; 287 288 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 289 return (0); 290 return rle->count; 291 } 292 293 static inline int 294 pci_resource_type(struct pci_dev *pdev, int bar) 295 { 296 struct pci_map *pm; 297 298 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 299 if (!pm) 300 return (-1); 301 302 if (PCI_BAR_IO(pm->pm_value)) 303 return (SYS_RES_IOPORT); 304 else 305 return (SYS_RES_MEMORY); 306 } 307 308 /* 309 * All drivers just seem to want to inspect the type not flags. 310 */ 311 static inline int 312 pci_resource_flags(struct pci_dev *pdev, int bar) 313 { 314 int type; 315 316 type = pci_resource_type(pdev, bar); 317 if (type < 0) 318 return (0); 319 return (1 << type); 320 } 321 322 static inline const char * 323 pci_name(struct pci_dev *d) 324 { 325 326 return device_get_desc(d->dev.bsddev); 327 } 328 329 static inline void * 330 pci_get_drvdata(struct pci_dev *pdev) 331 { 332 333 return dev_get_drvdata(&pdev->dev); 334 } 335 336 static inline void 337 pci_set_drvdata(struct pci_dev *pdev, void *data) 338 { 339 340 dev_set_drvdata(&pdev->dev, data); 341 } 342 343 static inline int 344 pci_enable_device(struct pci_dev *pdev) 345 { 346 347 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 348 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 349 return (0); 350 } 351 352 static inline void 353 pci_disable_device(struct pci_dev *pdev) 354 { 355 356 pci_disable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 357 pci_disable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 358 pci_disable_busmaster(pdev->dev.bsddev); 359 } 360 361 static inline int 362 pci_set_master(struct pci_dev *pdev) 363 { 364 365 pci_enable_busmaster(pdev->dev.bsddev); 366 return (0); 367 } 368 369 static inline int 370 pci_set_power_state(struct pci_dev *pdev, int state) 371 { 372 373 pci_set_powerstate(pdev->dev.bsddev, state); 374 return (0); 375 } 376 377 static inline int 378 pci_clear_master(struct pci_dev *pdev) 379 { 380 381 pci_disable_busmaster(pdev->dev.bsddev); 382 return (0); 383 } 384 385 static inline int 386 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 387 { 388 int rid; 389 int type; 390 391 type = pci_resource_type(pdev, bar); 392 if (type < 0) 393 return (-ENODEV); 394 rid = PCIR_BAR(bar); 395 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 396 RF_ACTIVE) == NULL) 397 return (-EINVAL); 398 return (0); 399 } 400 401 static inline void 402 pci_release_region(struct pci_dev *pdev, int bar) 403 { 404 struct resource_list_entry *rle; 405 406 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 407 return; 408 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 409 } 410 411 static inline void 412 pci_release_regions(struct pci_dev *pdev) 413 { 414 int i; 415 416 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 417 pci_release_region(pdev, i); 418 } 419 420 static inline int 421 pci_request_regions(struct pci_dev *pdev, const char *res_name) 422 { 423 int error; 424 int i; 425 426 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 427 error = pci_request_region(pdev, i, res_name); 428 if (error && error != -ENODEV) { 429 pci_release_regions(pdev); 430 return (error); 431 } 432 } 433 return (0); 434 } 435 436 static inline void 437 pci_disable_msix(struct pci_dev *pdev) 438 { 439 440 pci_release_msi(pdev->dev.bsddev); 441 442 /* 443 * The MSIX IRQ numbers associated with this PCI device are no 444 * longer valid and might be re-assigned. Make sure 445 * linux_pci_find_irq_dev() does no longer see them by 446 * resetting their references to zero: 447 */ 448 pdev->dev.msix = 0; 449 pdev->dev.msix_max = 0; 450 } 451 452 static inline bus_addr_t 453 pci_bus_address(struct pci_dev *pdev, int bar) 454 { 455 456 return (pci_resource_start(pdev, bar)); 457 } 458 459 #define PCI_CAP_ID_EXP PCIY_EXPRESS 460 #define PCI_CAP_ID_PCIX PCIY_PCIX 461 #define PCI_CAP_ID_AGP PCIY_AGP 462 #define PCI_CAP_ID_PM PCIY_PMG 463 464 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 465 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 466 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 467 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 468 #define PCI_EXP_LNKSTA PCIER_LINK_STA 469 470 static inline int 471 pci_find_capability(struct pci_dev *pdev, int capid) 472 { 473 int reg; 474 475 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 476 return (0); 477 return (reg); 478 } 479 480 static inline int pci_pcie_cap(struct pci_dev *dev) 481 { 482 return pci_find_capability(dev, PCI_CAP_ID_EXP); 483 } 484 485 486 static inline int 487 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 488 { 489 490 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 491 return (0); 492 } 493 494 static inline int 495 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 496 { 497 498 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 499 return (0); 500 } 501 502 static inline int 503 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 504 { 505 506 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 507 return (0); 508 } 509 510 static inline int 511 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 512 { 513 514 pci_write_config(pdev->dev.bsddev, where, val, 1); 515 return (0); 516 } 517 518 static inline int 519 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 520 { 521 522 pci_write_config(pdev->dev.bsddev, where, val, 2); 523 return (0); 524 } 525 526 static inline int 527 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 528 { 529 530 pci_write_config(pdev->dev.bsddev, where, val, 4); 531 return (0); 532 } 533 534 int linux_pci_register_driver(struct pci_driver *pdrv); 535 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 536 void linux_pci_unregister_driver(struct pci_driver *pdrv); 537 538 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 539 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 540 541 struct msix_entry { 542 int entry; 543 int vector; 544 }; 545 546 /* 547 * Enable msix, positive errors indicate actual number of available 548 * vectors. Negative errors are failures. 549 * 550 * NB: define added to prevent this definition of pci_enable_msix from 551 * clashing with the native FreeBSD version. 552 */ 553 #define pci_enable_msix(...) \ 554 linux_pci_enable_msix(__VA_ARGS__) 555 556 static inline int 557 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 558 { 559 struct resource_list_entry *rle; 560 int error; 561 int avail; 562 int i; 563 564 avail = pci_msix_count(pdev->dev.bsddev); 565 if (avail < nreq) { 566 if (avail == 0) 567 return -EINVAL; 568 return avail; 569 } 570 avail = nreq; 571 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 572 return error; 573 /* 574 * Handle case where "pci_alloc_msix()" may allocate less 575 * interrupts than available and return with no error: 576 */ 577 if (avail < nreq) { 578 pci_release_msi(pdev->dev.bsddev); 579 return avail; 580 } 581 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 582 pdev->dev.msix = rle->start; 583 pdev->dev.msix_max = rle->start + avail; 584 for (i = 0; i < nreq; i++) 585 entries[i].vector = pdev->dev.msix + i; 586 return (0); 587 } 588 589 #define pci_enable_msix_range(...) \ 590 linux_pci_enable_msix_range(__VA_ARGS__) 591 592 static inline int 593 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 594 int minvec, int maxvec) 595 { 596 int nvec = maxvec; 597 int rc; 598 599 if (maxvec < minvec) 600 return (-ERANGE); 601 602 do { 603 rc = pci_enable_msix(dev, entries, nvec); 604 if (rc < 0) { 605 return (rc); 606 } else if (rc > 0) { 607 if (rc < minvec) 608 return (-ENOSPC); 609 nvec = rc; 610 } 611 } while (rc); 612 return (nvec); 613 } 614 615 static inline int 616 pci_channel_offline(struct pci_dev *pdev) 617 { 618 619 return (pci_get_vendor(pdev->dev.bsddev) == 0xffff); 620 } 621 622 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 623 { 624 return -ENODEV; 625 } 626 static inline void pci_disable_sriov(struct pci_dev *dev) 627 { 628 } 629 630 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 631 const struct pci_device_id _table[] __devinitdata 632 633 634 /* XXX This should not be necessary. */ 635 #define pcix_set_mmrbc(d, v) 0 636 #define pcix_get_max_mmrbc(d) 0 637 #define pcie_set_readrq(d, v) 0 638 639 #define PCI_DMA_BIDIRECTIONAL 0 640 #define PCI_DMA_TODEVICE 1 641 #define PCI_DMA_FROMDEVICE 2 642 #define PCI_DMA_NONE 3 643 644 #define pci_pool dma_pool 645 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 646 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 647 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 648 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 649 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 650 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 651 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 652 _size, _vaddr, _dma_handle) 653 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 654 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 655 _sg, _nents, (enum dma_data_direction)_dir) 656 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 657 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 658 (_ptr), (_size), (enum dma_data_direction)_dir) 659 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 660 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 661 _addr, _size, (enum dma_data_direction)_dir) 662 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 663 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 664 _sg, _nents, (enum dma_data_direction)_dir) 665 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 666 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 667 _offset, _size, (enum dma_data_direction)_dir) 668 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 669 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 670 _dma_address, _size, (enum dma_data_direction)_dir) 671 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 672 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 673 dma_mapping_error(&(_pdev)->dev, _dma_addr) 674 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 675 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 676 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 677 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 678 #define pci_unmap_addr dma_unmap_addr 679 #define pci_unmap_addr_set dma_unmap_addr_set 680 #define pci_unmap_len dma_unmap_len 681 #define pci_unmap_len_set dma_unmap_len_set 682 683 typedef unsigned int __bitwise pci_channel_state_t; 684 typedef unsigned int __bitwise pci_ers_result_t; 685 686 enum pci_channel_state { 687 pci_channel_io_normal = 1, 688 pci_channel_io_frozen = 2, 689 pci_channel_io_perm_failure = 3, 690 }; 691 692 enum pci_ers_result { 693 PCI_ERS_RESULT_NONE = 1, 694 PCI_ERS_RESULT_CAN_RECOVER = 2, 695 PCI_ERS_RESULT_NEED_RESET = 3, 696 PCI_ERS_RESULT_DISCONNECT = 4, 697 PCI_ERS_RESULT_RECOVERED = 5, 698 }; 699 700 701 /* PCI bus error event callbacks */ 702 struct pci_error_handlers { 703 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 704 enum pci_channel_state error); 705 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 706 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 707 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 708 void (*resume)(struct pci_dev *dev); 709 }; 710 711 /* FreeBSD does not support SRIOV - yet */ 712 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 713 { 714 return dev; 715 } 716 717 static inline bool pci_is_pcie(struct pci_dev *dev) 718 { 719 return !!pci_pcie_cap(dev); 720 } 721 722 static inline u16 pcie_flags_reg(struct pci_dev *dev) 723 { 724 int pos; 725 u16 reg16; 726 727 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 728 if (!pos) 729 return 0; 730 731 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 732 733 return reg16; 734 } 735 736 737 static inline int pci_pcie_type(struct pci_dev *dev) 738 { 739 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 740 } 741 742 static inline int pcie_cap_version(struct pci_dev *dev) 743 { 744 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 745 } 746 747 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 748 { 749 int type = pci_pcie_type(dev); 750 751 return pcie_cap_version(dev) > 1 || 752 type == PCI_EXP_TYPE_ROOT_PORT || 753 type == PCI_EXP_TYPE_ENDPOINT || 754 type == PCI_EXP_TYPE_LEG_END; 755 } 756 757 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 758 { 759 return true; 760 } 761 762 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 763 { 764 int type = pci_pcie_type(dev); 765 766 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 767 (type == PCI_EXP_TYPE_DOWNSTREAM && 768 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 769 } 770 771 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 772 { 773 int type = pci_pcie_type(dev); 774 775 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 776 type == PCI_EXP_TYPE_RC_EC; 777 } 778 779 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 780 { 781 if (!pci_is_pcie(dev)) 782 return false; 783 784 switch (pos) { 785 case PCI_EXP_FLAGS_TYPE: 786 return true; 787 case PCI_EXP_DEVCAP: 788 case PCI_EXP_DEVCTL: 789 case PCI_EXP_DEVSTA: 790 return pcie_cap_has_devctl(dev); 791 case PCI_EXP_LNKCAP: 792 case PCI_EXP_LNKCTL: 793 case PCI_EXP_LNKSTA: 794 return pcie_cap_has_lnkctl(dev); 795 case PCI_EXP_SLTCAP: 796 case PCI_EXP_SLTCTL: 797 case PCI_EXP_SLTSTA: 798 return pcie_cap_has_sltctl(dev); 799 case PCI_EXP_RTCTL: 800 case PCI_EXP_RTCAP: 801 case PCI_EXP_RTSTA: 802 return pcie_cap_has_rtctl(dev); 803 case PCI_EXP_DEVCAP2: 804 case PCI_EXP_DEVCTL2: 805 case PCI_EXP_LNKCAP2: 806 case PCI_EXP_LNKCTL2: 807 case PCI_EXP_LNKSTA2: 808 return pcie_cap_version(dev) > 1; 809 default: 810 return false; 811 } 812 } 813 814 static inline int 815 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 816 { 817 if (pos & 3) 818 return -EINVAL; 819 820 if (!pcie_capability_reg_implemented(dev, pos)) 821 return -EINVAL; 822 823 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 824 } 825 826 static inline int 827 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 828 { 829 if (pos & 3) 830 return -EINVAL; 831 832 if (!pcie_capability_reg_implemented(dev, pos)) 833 return -EINVAL; 834 835 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 836 } 837 838 static inline int 839 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 840 { 841 if (pos & 1) 842 return -EINVAL; 843 844 if (!pcie_capability_reg_implemented(dev, pos)) 845 return 0; 846 847 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 848 } 849 850 static inline int pcie_get_minimum_link(struct pci_dev *dev, 851 enum pci_bus_speed *speed, enum pcie_link_width *width) 852 { 853 *speed = PCI_SPEED_UNKNOWN; 854 *width = PCIE_LNK_WIDTH_UNKNOWN; 855 return (0); 856 } 857 858 static inline int 859 pci_num_vf(struct pci_dev *dev) 860 { 861 return (0); 862 } 863 864 static inline enum pci_bus_speed 865 pcie_get_speed_cap(struct pci_dev *dev) 866 { 867 device_t root; 868 uint32_t lnkcap, lnkcap2; 869 int error, pos; 870 871 root = device_get_parent(dev->dev.bsddev); 872 if (root == NULL) 873 return (PCI_SPEED_UNKNOWN); 874 root = device_get_parent(root); 875 if (root == NULL) 876 return (PCI_SPEED_UNKNOWN); 877 root = device_get_parent(root); 878 if (root == NULL) 879 return (PCI_SPEED_UNKNOWN); 880 881 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 882 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 883 return (PCI_SPEED_UNKNOWN); 884 885 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 886 return (PCI_SPEED_UNKNOWN); 887 888 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 889 890 if (lnkcap2) { /* PCIe r3.0-compliant */ 891 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 892 return (PCIE_SPEED_2_5GT); 893 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 894 return (PCIE_SPEED_5_0GT); 895 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 896 return (PCIE_SPEED_8_0GT); 897 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 898 return (PCIE_SPEED_16_0GT); 899 } else { /* pre-r3.0 */ 900 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 901 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 902 return (PCIE_SPEED_2_5GT); 903 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 904 return (PCIE_SPEED_5_0GT); 905 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 906 return (PCIE_SPEED_8_0GT); 907 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 908 return (PCIE_SPEED_16_0GT); 909 } 910 return (PCI_SPEED_UNKNOWN); 911 } 912 913 static inline enum pcie_link_width 914 pcie_get_width_cap(struct pci_dev *dev) 915 { 916 uint32_t lnkcap; 917 918 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 919 if (lnkcap) 920 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 921 922 return (PCIE_LNK_WIDTH_UNKNOWN); 923 } 924 925 #endif /* _LINUX_PCI_H_ */ 926