1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/module.h> 43 #include <sys/nv.h> 44 #include <sys/pciio.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pci_private.h> 48 49 #include <machine/resource.h> 50 51 #include <linux/list.h> 52 #include <linux/dmapool.h> 53 #include <linux/dma-mapping.h> 54 #include <linux/compiler.h> 55 #include <linux/errno.h> 56 #include <asm/atomic.h> 57 #include <asm/memtype.h> 58 #include <linux/device.h> 59 #include <linux/pci_ids.h> 60 #include <linux/pm.h> 61 62 struct pci_device_id { 63 uint32_t vendor; 64 uint32_t device; 65 uint32_t subvendor; 66 uint32_t subdevice; 67 uint32_t class; 68 uint32_t class_mask; 69 uintptr_t driver_data; 70 }; 71 72 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 73 #define MODULE_DEVICE_TABLE(_bus, _table) \ 74 \ 75 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 76 DEVMETHOD_END \ 77 }; \ 78 \ 79 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 80 "lkpi_" #_bus #_table, \ 81 _ ## _bus ## _ ## _table ## _methods, \ 82 0 \ 83 }; \ 84 \ 85 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 86 0, 0); \ 87 \ 88 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 89 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 90 91 #define PCI_ANY_ID -1U 92 93 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 94 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 95 #define PCI_FUNC(devfn) ((devfn) & 0x07) 96 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 97 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 98 99 #define PCI_VDEVICE(_vendor, _device) \ 100 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 101 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 102 #define PCI_DEVICE(_vendor, _device) \ 103 .vendor = (_vendor), .device = (_device), \ 104 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 105 106 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 107 108 #define PCI_STD_NUM_BARS 6 109 #define PCI_VENDOR_ID PCIR_VENDOR 110 #define PCI_DEVICE_ID PCIR_DEVICE 111 #define PCI_COMMAND PCIR_COMMAND 112 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 113 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 114 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 115 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 116 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 117 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 118 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 119 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 120 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 121 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 122 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 123 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 124 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 125 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 126 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 127 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 128 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 129 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 130 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 131 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 132 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 133 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 134 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 135 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 136 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 137 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 138 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 139 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 140 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 141 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 142 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 143 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 144 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 145 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 146 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 147 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 148 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 149 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 150 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 151 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 152 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 153 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 154 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 155 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 156 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 157 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 158 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 159 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 160 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 161 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 162 #define PCI_EXP_LNKCTL2_TLS 0x000f 163 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 164 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 165 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 166 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 167 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 168 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 169 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 170 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 171 172 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 173 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 174 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 175 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 176 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 177 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 178 179 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 180 #define PCI_EXP_DEVSTA_TRPND 0x0020 181 182 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 183 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 184 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 185 186 enum pci_bus_speed { 187 PCI_SPEED_UNKNOWN = -1, 188 PCIE_SPEED_2_5GT, 189 PCIE_SPEED_5_0GT, 190 PCIE_SPEED_8_0GT, 191 PCIE_SPEED_16_0GT, 192 PCIE_SPEED_32_0GT, 193 PCIE_SPEED_64_0GT, 194 }; 195 196 enum pcie_link_width { 197 PCIE_LNK_WIDTH_RESRV = 0x00, 198 PCIE_LNK_X1 = 0x01, 199 PCIE_LNK_X2 = 0x02, 200 PCIE_LNK_X4 = 0x04, 201 PCIE_LNK_X8 = 0x08, 202 PCIE_LNK_X12 = 0x0c, 203 PCIE_LNK_X16 = 0x10, 204 PCIE_LNK_X32 = 0x20, 205 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 206 }; 207 208 #define PCIE_LINK_STATE_L0S 0x00000001 209 #define PCIE_LINK_STATE_L1 0x00000002 210 #define PCIE_LINK_STATE_CLKPM 0x00000004 211 212 typedef int pci_power_t; 213 214 #define PCI_D0 PCI_POWERSTATE_D0 215 #define PCI_D1 PCI_POWERSTATE_D1 216 #define PCI_D2 PCI_POWERSTATE_D2 217 #define PCI_D3hot PCI_POWERSTATE_D3 218 #define PCI_D3cold 4 219 220 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 221 222 extern const char *pci_power_names[6]; 223 224 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 225 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 226 227 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 228 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 229 230 #define PCI_L1SS_CTL1 0x8 231 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 232 233 #define PCI_IRQ_LEGACY 0x01 234 #define PCI_IRQ_MSI 0x02 235 #define PCI_IRQ_MSIX 0x04 236 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 237 238 struct pci_dev; 239 240 struct pci_driver { 241 struct list_head node; 242 char *name; 243 const struct pci_device_id *id_table; 244 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 245 void (*remove)(struct pci_dev *dev); 246 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 247 int (*resume) (struct pci_dev *dev); /* Device woken up */ 248 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 249 driver_t bsddriver; 250 devclass_t bsdclass; 251 struct device_driver driver; 252 const struct pci_error_handlers *err_handler; 253 bool isdrm; 254 int bsd_probe_return; 255 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 256 const nvlist_t *pf_config); 257 void (*bsd_iov_uninit)(device_t dev); 258 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 259 const nvlist_t *vf_config); 260 }; 261 262 struct pci_bus { 263 struct pci_dev *self; 264 /* struct pci_bus *parent */ 265 int domain; 266 int number; 267 }; 268 269 extern struct list_head pci_drivers; 270 extern struct list_head pci_devices; 271 extern spinlock_t pci_lock; 272 273 #define __devexit_p(x) x 274 275 #define module_pci_driver(_driver) \ 276 \ 277 static inline int \ 278 _pci_init(void) \ 279 { \ 280 \ 281 return (linux_pci_register_driver(&_driver)); \ 282 } \ 283 \ 284 static inline void \ 285 _pci_exit(void) \ 286 { \ 287 \ 288 linux_pci_unregister_driver(&_driver); \ 289 } \ 290 \ 291 module_init(_pci_init); \ 292 module_exit(_pci_exit) 293 294 struct msi_msg { 295 uint32_t data; 296 }; 297 298 struct pci_msi_desc { 299 struct { 300 bool is_64; 301 } msi_attrib; 302 }; 303 304 struct msi_desc { 305 struct msi_msg msg; 306 struct pci_msi_desc pci; 307 }; 308 309 struct msix_entry { 310 int entry; 311 int vector; 312 }; 313 314 /* 315 * If we find drivers accessing this from multiple KPIs we may have to 316 * refcount objects of this structure. 317 */ 318 struct resource; 319 struct pci_mmio_region { 320 TAILQ_ENTRY(pci_mmio_region) next; 321 struct resource *res; 322 int rid; 323 int type; 324 }; 325 326 struct pci_dev { 327 struct device dev; 328 struct list_head links; 329 struct pci_driver *pdrv; 330 struct pci_bus *bus; 331 struct pci_dev *root; 332 pci_power_t current_state; 333 uint16_t device; 334 uint16_t vendor; 335 uint16_t subsystem_vendor; 336 uint16_t subsystem_device; 337 unsigned int irq; 338 unsigned int devfn; 339 uint32_t class; 340 uint8_t revision; 341 uint8_t msi_cap; 342 uint8_t msix_cap; 343 bool managed; /* devres "pcim_*(). */ 344 bool want_iomap_res; 345 bool msi_enabled; 346 bool msix_enabled; 347 phys_addr_t rom; 348 size_t romlen; 349 struct msi_desc **msi_desc; 350 char *path_name; 351 spinlock_t pcie_cap_lock; 352 353 TAILQ_HEAD(, pci_mmio_region) mmio; 354 }; 355 356 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 357 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 358 unsigned int flags); 359 bool pci_device_is_present(struct pci_dev *pdev); 360 361 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 362 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 363 void *linuxkpi_pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size); 364 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 365 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 366 const char *name); 367 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 368 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 369 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 370 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 371 int nreq); 372 373 /* Internal helper function(s). */ 374 struct pci_dev *lkpinew_pci_dev(device_t); 375 void lkpi_pci_devres_release(struct device *, void *); 376 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 377 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 378 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 379 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 380 381 static inline bool 382 dev_is_pci(struct device *dev) 383 { 384 385 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 386 } 387 388 static inline uint16_t 389 pci_dev_id(struct pci_dev *pdev) 390 { 391 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 392 } 393 394 static inline int 395 pci_resource_type(struct pci_dev *pdev, int bar) 396 { 397 struct pci_map *pm; 398 399 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 400 if (!pm) 401 return (-1); 402 403 if (PCI_BAR_IO(pm->pm_value)) 404 return (SYS_RES_IOPORT); 405 else 406 return (SYS_RES_MEMORY); 407 } 408 409 /* 410 * All drivers just seem to want to inspect the type not flags. 411 */ 412 static inline int 413 pci_resource_flags(struct pci_dev *pdev, int bar) 414 { 415 int type; 416 417 type = pci_resource_type(pdev, bar); 418 if (type < 0) 419 return (0); 420 return (1 << type); 421 } 422 423 static inline const char * 424 pci_name(struct pci_dev *d) 425 { 426 return d->path_name; 427 } 428 429 static inline void * 430 pci_get_drvdata(struct pci_dev *pdev) 431 { 432 433 return dev_get_drvdata(&pdev->dev); 434 } 435 436 static inline void 437 pci_set_drvdata(struct pci_dev *pdev, void *data) 438 { 439 440 dev_set_drvdata(&pdev->dev, data); 441 } 442 443 static inline struct pci_dev * 444 pci_dev_get(struct pci_dev *pdev) 445 { 446 447 if (pdev != NULL) 448 get_device(&pdev->dev); 449 return (pdev); 450 } 451 452 static __inline void 453 pci_dev_put(struct pci_dev *pdev) 454 { 455 456 if (pdev != NULL) 457 put_device(&pdev->dev); 458 } 459 460 static inline int 461 pci_enable_device(struct pci_dev *pdev) 462 { 463 464 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 465 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 466 return (0); 467 } 468 469 static inline void 470 pci_disable_device(struct pci_dev *pdev) 471 { 472 473 pci_disable_busmaster(pdev->dev.bsddev); 474 } 475 476 static inline int 477 pci_set_master(struct pci_dev *pdev) 478 { 479 480 pci_enable_busmaster(pdev->dev.bsddev); 481 return (0); 482 } 483 484 static inline int 485 pci_set_power_state(struct pci_dev *pdev, int state) 486 { 487 488 pci_set_powerstate(pdev->dev.bsddev, state); 489 return (0); 490 } 491 492 static inline int 493 pci_clear_master(struct pci_dev *pdev) 494 { 495 496 pci_disable_busmaster(pdev->dev.bsddev); 497 return (0); 498 } 499 500 static inline bool 501 pci_is_root_bus(struct pci_bus *pbus) 502 { 503 504 return (pbus->self == NULL); 505 } 506 507 static inline struct pci_dev * 508 pci_upstream_bridge(struct pci_dev *pdev) 509 { 510 511 if (pci_is_root_bus(pdev->bus)) 512 return (NULL); 513 514 /* 515 * If we do not have a (proper) "upstream bridge" set, e.g., we point 516 * to ourselves, try to handle this case on the fly like we do 517 * for pcie_find_root_port(). 518 */ 519 if (pdev == pdev->bus->self) { 520 device_t bridge; 521 522 bridge = device_get_parent(pdev->dev.bsddev); 523 if (bridge == NULL) 524 goto done; 525 bridge = device_get_parent(bridge); 526 if (bridge == NULL) 527 goto done; 528 if (device_get_devclass(device_get_parent(bridge)) != 529 devclass_find("pci")) 530 goto done; 531 532 /* 533 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 534 * for it so it can be returned. 535 */ 536 pdev->bus->self = lkpinew_pci_dev(bridge); 537 } 538 done: 539 return (pdev->bus->self); 540 } 541 542 #define pci_release_region(pdev, bar) linuxkpi_pci_release_region(pdev, bar) 543 #define pci_release_regions(pdev) linuxkpi_pci_release_regions(pdev) 544 #define pci_request_regions(pdev, res_name) \ 545 linuxkpi_pci_request_regions(pdev, res_name) 546 547 static inline void 548 lkpi_pci_disable_msix(struct pci_dev *pdev) 549 { 550 551 pci_release_msi(pdev->dev.bsddev); 552 553 /* 554 * The MSIX IRQ numbers associated with this PCI device are no 555 * longer valid and might be re-assigned. Make sure 556 * lkpi_pci_find_irq_dev() does no longer see them by 557 * resetting their references to zero: 558 */ 559 pdev->dev.irq_start = 0; 560 pdev->dev.irq_end = 0; 561 pdev->msix_enabled = false; 562 } 563 /* Only for consistency. No conflict on that one. */ 564 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 565 566 static inline void 567 lkpi_pci_disable_msi(struct pci_dev *pdev) 568 { 569 570 pci_release_msi(pdev->dev.bsddev); 571 572 pdev->dev.irq_start = 0; 573 pdev->dev.irq_end = 0; 574 pdev->irq = pdev->dev.irq; 575 pdev->msi_enabled = false; 576 } 577 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 578 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 579 580 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 581 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 582 583 static inline bus_addr_t 584 pci_bus_address(struct pci_dev *pdev, int bar) 585 { 586 587 return (pci_resource_start(pdev, bar)); 588 } 589 590 #define PCI_CAP_ID_EXP PCIY_EXPRESS 591 #define PCI_CAP_ID_PCIX PCIY_PCIX 592 #define PCI_CAP_ID_AGP PCIY_AGP 593 #define PCI_CAP_ID_PM PCIY_PMG 594 595 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 596 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 597 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 598 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 599 #define PCI_EXP_LNKSTA PCIER_LINK_STA 600 601 static inline int 602 pci_find_capability(struct pci_dev *pdev, int capid) 603 { 604 int reg; 605 606 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 607 return (0); 608 return (reg); 609 } 610 611 static inline int pci_pcie_cap(struct pci_dev *dev) 612 { 613 return pci_find_capability(dev, PCI_CAP_ID_EXP); 614 } 615 616 static inline int 617 pci_find_ext_capability(struct pci_dev *pdev, int capid) 618 { 619 int reg; 620 621 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 622 return (0); 623 return (reg); 624 } 625 626 #define PCIM_PCAP_PME_SHIFT 11 627 static __inline bool 628 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 629 { 630 struct pci_devinfo *dinfo; 631 pcicfgregs *cfg; 632 633 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 634 return (false); 635 636 dinfo = device_get_ivars(pdev->dev.bsddev); 637 cfg = &dinfo->cfg; 638 639 if (cfg->pp.pp_cap == 0) 640 return (false); 641 642 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 643 return (true); 644 645 return (false); 646 } 647 648 static inline int 649 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 650 { 651 652 if (!pci_enable_aspm) 653 return (-EPERM); 654 655 return (-ENXIO); 656 } 657 658 static inline int 659 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 660 { 661 662 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 663 return (0); 664 } 665 666 static inline int 667 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 668 { 669 670 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 671 return (0); 672 } 673 674 static inline int 675 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 676 { 677 678 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 679 return (0); 680 } 681 682 static inline int 683 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 684 { 685 686 pci_write_config(pdev->dev.bsddev, where, val, 1); 687 return (0); 688 } 689 690 static inline int 691 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 692 { 693 694 pci_write_config(pdev->dev.bsddev, where, val, 2); 695 return (0); 696 } 697 698 static inline int 699 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 700 { 701 702 pci_write_config(pdev->dev.bsddev, where, val, 4); 703 return (0); 704 } 705 706 int linux_pci_register_driver(struct pci_driver *pdrv); 707 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 708 void linux_pci_unregister_driver(struct pci_driver *pdrv); 709 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 710 711 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 712 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 713 714 /* 715 * Enable msix, positive errors indicate actual number of available 716 * vectors. Negative errors are failures. 717 * 718 * NB: define added to prevent this definition of pci_enable_msix from 719 * clashing with the native FreeBSD version. 720 */ 721 #define pci_enable_msix(...) linuxkpi_pci_enable_msix(__VA_ARGS__) 722 723 #define pci_enable_msix_range(...) \ 724 linux_pci_enable_msix_range(__VA_ARGS__) 725 726 static inline int 727 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 728 int minvec, int maxvec) 729 { 730 int nvec = maxvec; 731 int rc; 732 733 if (maxvec < minvec) 734 return (-ERANGE); 735 736 do { 737 rc = pci_enable_msix(dev, entries, nvec); 738 if (rc < 0) { 739 return (rc); 740 } else if (rc > 0) { 741 if (rc < minvec) 742 return (-ENOSPC); 743 nvec = rc; 744 } 745 } while (rc); 746 return (nvec); 747 } 748 749 #define pci_enable_msi(pdev) \ 750 linux_pci_enable_msi(pdev) 751 752 static inline int 753 pci_enable_msi(struct pci_dev *pdev) 754 { 755 756 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 757 } 758 759 static inline int 760 pci_channel_offline(struct pci_dev *pdev) 761 { 762 763 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 764 } 765 766 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 767 { 768 return -ENODEV; 769 } 770 771 static inline void pci_disable_sriov(struct pci_dev *dev) 772 { 773 } 774 775 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 776 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 777 #define pci_iounmap(pdev, res) linuxkpi_pci_iounmap(pdev, res) 778 779 static inline void 780 lkpi_pci_save_state(struct pci_dev *pdev) 781 { 782 783 pci_save_state(pdev->dev.bsddev); 784 } 785 786 static inline void 787 lkpi_pci_restore_state(struct pci_dev *pdev) 788 { 789 790 pci_restore_state(pdev->dev.bsddev); 791 } 792 793 #define pci_save_state(dev) lkpi_pci_save_state(dev) 794 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 795 796 static inline int 797 pci_reset_function(struct pci_dev *pdev) 798 { 799 800 return (-ENOSYS); 801 } 802 803 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 804 const struct pci_device_id _table[] __devinitdata 805 806 /* XXX This should not be necessary. */ 807 #define pcix_set_mmrbc(d, v) 0 808 #define pcix_get_max_mmrbc(d) 0 809 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 810 811 #define PCI_DMA_BIDIRECTIONAL 0 812 #define PCI_DMA_TODEVICE 1 813 #define PCI_DMA_FROMDEVICE 2 814 #define PCI_DMA_NONE 3 815 816 #define pci_pool dma_pool 817 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 818 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 819 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 820 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 821 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 822 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 823 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 824 _size, _vaddr, _dma_handle) 825 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 826 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 827 _sg, _nents, (enum dma_data_direction)_dir) 828 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 829 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 830 (_ptr), (_size), (enum dma_data_direction)_dir) 831 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 832 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 833 _addr, _size, (enum dma_data_direction)_dir) 834 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 835 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 836 _sg, _nents, (enum dma_data_direction)_dir) 837 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 838 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 839 _offset, _size, (enum dma_data_direction)_dir) 840 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 841 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 842 _dma_address, _size, (enum dma_data_direction)_dir) 843 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 844 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 845 dma_mapping_error(&(_pdev)->dev, _dma_addr) 846 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 847 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 848 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 849 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 850 #define pci_unmap_addr dma_unmap_addr 851 #define pci_unmap_addr_set dma_unmap_addr_set 852 #define pci_unmap_len dma_unmap_len 853 #define pci_unmap_len_set dma_unmap_len_set 854 855 typedef unsigned int __bitwise pci_channel_state_t; 856 typedef unsigned int __bitwise pci_ers_result_t; 857 858 enum pci_channel_state { 859 pci_channel_io_normal = 1, 860 pci_channel_io_frozen = 2, 861 pci_channel_io_perm_failure = 3, 862 }; 863 864 enum pci_ers_result { 865 PCI_ERS_RESULT_NONE = 1, 866 PCI_ERS_RESULT_CAN_RECOVER = 2, 867 PCI_ERS_RESULT_NEED_RESET = 3, 868 PCI_ERS_RESULT_DISCONNECT = 4, 869 PCI_ERS_RESULT_RECOVERED = 5, 870 }; 871 872 /* PCI bus error event callbacks */ 873 struct pci_error_handlers { 874 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 875 enum pci_channel_state error); 876 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 877 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 878 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 879 void (*resume)(struct pci_dev *dev); 880 }; 881 882 /* FreeBSD does not support SRIOV - yet */ 883 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 884 { 885 return dev; 886 } 887 888 static inline bool pci_is_pcie(struct pci_dev *dev) 889 { 890 return !!pci_pcie_cap(dev); 891 } 892 893 static inline u16 pcie_flags_reg(struct pci_dev *dev) 894 { 895 int pos; 896 u16 reg16; 897 898 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 899 if (!pos) 900 return 0; 901 902 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 903 904 return reg16; 905 } 906 907 static inline int pci_pcie_type(struct pci_dev *dev) 908 { 909 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 910 } 911 912 static inline int pcie_cap_version(struct pci_dev *dev) 913 { 914 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 915 } 916 917 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 918 { 919 int type = pci_pcie_type(dev); 920 921 return pcie_cap_version(dev) > 1 || 922 type == PCI_EXP_TYPE_ROOT_PORT || 923 type == PCI_EXP_TYPE_ENDPOINT || 924 type == PCI_EXP_TYPE_LEG_END; 925 } 926 927 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 928 { 929 return true; 930 } 931 932 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 933 { 934 int type = pci_pcie_type(dev); 935 936 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 937 (type == PCI_EXP_TYPE_DOWNSTREAM && 938 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 939 } 940 941 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 942 { 943 int type = pci_pcie_type(dev); 944 945 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 946 type == PCI_EXP_TYPE_RC_EC; 947 } 948 949 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 950 { 951 if (!pci_is_pcie(dev)) 952 return false; 953 954 switch (pos) { 955 case PCI_EXP_FLAGS_TYPE: 956 return true; 957 case PCI_EXP_DEVCAP: 958 case PCI_EXP_DEVCTL: 959 case PCI_EXP_DEVSTA: 960 return pcie_cap_has_devctl(dev); 961 case PCI_EXP_LNKCAP: 962 case PCI_EXP_LNKCTL: 963 case PCI_EXP_LNKSTA: 964 return pcie_cap_has_lnkctl(dev); 965 case PCI_EXP_SLTCAP: 966 case PCI_EXP_SLTCTL: 967 case PCI_EXP_SLTSTA: 968 return pcie_cap_has_sltctl(dev); 969 case PCI_EXP_RTCTL: 970 case PCI_EXP_RTCAP: 971 case PCI_EXP_RTSTA: 972 return pcie_cap_has_rtctl(dev); 973 case PCI_EXP_DEVCAP2: 974 case PCI_EXP_DEVCTL2: 975 case PCI_EXP_LNKCAP2: 976 case PCI_EXP_LNKCTL2: 977 case PCI_EXP_LNKSTA2: 978 return pcie_cap_version(dev) > 1; 979 default: 980 return false; 981 } 982 } 983 984 static inline int 985 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 986 { 987 *dst = 0; 988 if (pos & 3) 989 return -EINVAL; 990 991 if (!pcie_capability_reg_implemented(dev, pos)) 992 return -EINVAL; 993 994 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 995 } 996 997 static inline int 998 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 999 { 1000 *dst = 0; 1001 if (pos & 3) 1002 return -EINVAL; 1003 1004 if (!pcie_capability_reg_implemented(dev, pos)) 1005 return -EINVAL; 1006 1007 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1008 } 1009 1010 static inline int 1011 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1012 { 1013 if (pos & 1) 1014 return -EINVAL; 1015 1016 if (!pcie_capability_reg_implemented(dev, pos)) 1017 return 0; 1018 1019 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1020 } 1021 1022 static inline int 1023 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1024 uint16_t clear, uint16_t set) 1025 { 1026 int error; 1027 uint16_t v; 1028 1029 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1030 spin_lock(&dev->pcie_cap_lock); 1031 1032 error = pcie_capability_read_word(dev, pos, &v); 1033 if (error == 0) { 1034 v &= ~clear; 1035 v |= set; 1036 error = pcie_capability_write_word(dev, pos, v); 1037 } 1038 1039 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1040 spin_unlock(&dev->pcie_cap_lock); 1041 1042 return (error); 1043 } 1044 1045 static inline int 1046 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1047 { 1048 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1049 } 1050 1051 static inline int 1052 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1053 { 1054 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1055 } 1056 1057 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1058 enum pci_bus_speed *speed, enum pcie_link_width *width) 1059 { 1060 *speed = PCI_SPEED_UNKNOWN; 1061 *width = PCIE_LNK_WIDTH_UNKNOWN; 1062 return (0); 1063 } 1064 1065 static inline int 1066 pci_num_vf(struct pci_dev *dev) 1067 { 1068 return (0); 1069 } 1070 1071 static inline enum pci_bus_speed 1072 pcie_get_speed_cap(struct pci_dev *dev) 1073 { 1074 device_t root; 1075 uint32_t lnkcap, lnkcap2; 1076 int error, pos; 1077 1078 root = device_get_parent(dev->dev.bsddev); 1079 if (root == NULL) 1080 return (PCI_SPEED_UNKNOWN); 1081 root = device_get_parent(root); 1082 if (root == NULL) 1083 return (PCI_SPEED_UNKNOWN); 1084 root = device_get_parent(root); 1085 if (root == NULL) 1086 return (PCI_SPEED_UNKNOWN); 1087 1088 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1089 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1090 return (PCI_SPEED_UNKNOWN); 1091 1092 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1093 return (PCI_SPEED_UNKNOWN); 1094 1095 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1096 1097 if (lnkcap2) { /* PCIe r3.0-compliant */ 1098 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1099 return (PCIE_SPEED_2_5GT); 1100 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1101 return (PCIE_SPEED_5_0GT); 1102 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1103 return (PCIE_SPEED_8_0GT); 1104 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1105 return (PCIE_SPEED_16_0GT); 1106 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1107 return (PCIE_SPEED_32_0GT); 1108 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1109 return (PCIE_SPEED_64_0GT); 1110 } else { /* pre-r3.0 */ 1111 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1112 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1113 return (PCIE_SPEED_2_5GT); 1114 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1115 return (PCIE_SPEED_5_0GT); 1116 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1117 return (PCIE_SPEED_8_0GT); 1118 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1119 return (PCIE_SPEED_16_0GT); 1120 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1121 return (PCIE_SPEED_32_0GT); 1122 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1123 return (PCIE_SPEED_64_0GT); 1124 } 1125 return (PCI_SPEED_UNKNOWN); 1126 } 1127 1128 static inline enum pcie_link_width 1129 pcie_get_width_cap(struct pci_dev *dev) 1130 { 1131 uint32_t lnkcap; 1132 1133 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1134 if (lnkcap) 1135 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1136 1137 return (PCIE_LNK_WIDTH_UNKNOWN); 1138 } 1139 1140 static inline int 1141 pcie_get_mps(struct pci_dev *dev) 1142 { 1143 return (pci_get_max_payload(dev->dev.bsddev)); 1144 } 1145 1146 static inline uint32_t 1147 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1148 { 1149 1150 switch(spd) { 1151 case PCIE_SPEED_64_0GT: 1152 return (64000 * 128 / 130); 1153 case PCIE_SPEED_32_0GT: 1154 return (32000 * 128 / 130); 1155 case PCIE_SPEED_16_0GT: 1156 return (16000 * 128 / 130); 1157 case PCIE_SPEED_8_0GT: 1158 return (8000 * 128 / 130); 1159 case PCIE_SPEED_5_0GT: 1160 return (5000 * 8 / 10); 1161 case PCIE_SPEED_2_5GT: 1162 return (2500 * 8 / 10); 1163 default: 1164 return (0); 1165 } 1166 } 1167 1168 static inline uint32_t 1169 pcie_bandwidth_available(struct pci_dev *pdev, 1170 struct pci_dev **limiting, 1171 enum pci_bus_speed *speed, 1172 enum pcie_link_width *width) 1173 { 1174 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1175 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1176 1177 if (speed) 1178 *speed = nspeed; 1179 if (width) 1180 *width = nwidth; 1181 1182 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1183 } 1184 1185 static inline bool 1186 pcie_aspm_enabled(struct pci_dev *pdev) 1187 { 1188 return (false); 1189 } 1190 1191 static inline struct pci_dev * 1192 pcie_find_root_port(struct pci_dev *pdev) 1193 { 1194 device_t root; 1195 1196 if (pdev->root != NULL) 1197 return (pdev->root); 1198 1199 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1200 if (root == NULL) 1201 return (NULL); 1202 1203 pdev->root = lkpinew_pci_dev(root); 1204 return (pdev->root); 1205 } 1206 1207 /* This is needed when people rip out the device "HotPlug". */ 1208 static inline void 1209 pci_lock_rescan_remove(void) 1210 { 1211 } 1212 1213 static inline void 1214 pci_unlock_rescan_remove(void) 1215 { 1216 } 1217 1218 static __inline void 1219 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1220 { 1221 } 1222 1223 static inline int 1224 pci_rescan_bus(struct pci_bus *pbus) 1225 { 1226 device_t *devlist, parent; 1227 int devcount, error; 1228 1229 if (!device_is_attached(pbus->self->dev.bsddev)) 1230 return (0); 1231 /* pci_rescan_method() will work on the pcib (parent). */ 1232 error = BUS_RESCAN(pbus->self->dev.bsddev); 1233 if (error != 0) 1234 return (0); 1235 1236 parent = device_get_parent(pbus->self->dev.bsddev); 1237 error = device_get_children(parent, &devlist, &devcount); 1238 if (error != 0) 1239 return (0); 1240 if (devcount != 0) 1241 free(devlist, M_TEMP); 1242 1243 return (devcount); 1244 } 1245 1246 /* 1247 * The following functions can be used to attach/detach the LinuxKPI's 1248 * PCI device runtime. The pci_driver and pci_device_id pointer is 1249 * allowed to be NULL. Other pointers must be all valid. 1250 * The pci_dev structure should be zero-initialized before passed 1251 * to the linux_pci_attach_device function. 1252 */ 1253 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1254 const struct pci_device_id *, struct pci_dev *); 1255 extern int linux_pci_detach_device(struct pci_dev *); 1256 1257 static inline int 1258 pci_dev_present(const struct pci_device_id *cur) 1259 { 1260 while (cur != NULL && (cur->vendor || cur->device)) { 1261 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1262 return (1); 1263 } 1264 cur++; 1265 } 1266 return (0); 1267 } 1268 1269 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1270 unsigned int bus, unsigned int devfn); 1271 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1272 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1273 1274 static inline int 1275 pci_domain_nr(struct pci_bus *pbus) 1276 { 1277 1278 return (pbus->domain); 1279 } 1280 1281 static inline int 1282 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1283 int pos, uint32_t *val, int len) 1284 { 1285 1286 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1287 return (0); 1288 } 1289 1290 static inline int 1291 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1292 { 1293 uint32_t tmp; 1294 int ret; 1295 1296 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1297 *val = (u16)tmp; 1298 return (ret); 1299 } 1300 1301 static inline int 1302 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1303 { 1304 uint32_t tmp; 1305 int ret; 1306 1307 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1308 *val = (u8)tmp; 1309 return (ret); 1310 } 1311 1312 static inline int 1313 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1314 uint32_t val, int size) 1315 { 1316 1317 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1318 return (0); 1319 } 1320 1321 static inline int 1322 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1323 uint8_t val) 1324 { 1325 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1326 } 1327 1328 static inline int 1329 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1330 uint16_t val) 1331 { 1332 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1333 } 1334 1335 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1336 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1337 1338 /* -------------------------------------------------------------------------- */ 1339 1340 #define pcim_enable_device(pdev) linuxkpi_pcim_enable_device(pdev) 1341 #define pcim_iomap_table(pdev) linuxkpi_pcim_iomap_table(pdev) 1342 #define pcim_iomap_regions(pdev, mask, name) \ 1343 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1344 1345 static inline int 1346 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1347 { 1348 uint32_t requests, req_mask; 1349 int bar, error; 1350 1351 /* Request all the BARs ("regions") we do not iomap. */ 1352 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1353 for (bar = requests = 0; requests != req_mask; bar++) { 1354 if ((req_mask & (1 << bar)) == 0) 1355 continue; 1356 error = pci_request_region(pdev, bar, name); 1357 if (error != 0 && error != -ENODEV) 1358 goto err; 1359 requests |= (1 << bar); 1360 } 1361 1362 error = pcim_iomap_regions(pdev, mask, name); 1363 if (error != 0) 1364 goto err; 1365 1366 return (0); 1367 1368 err: 1369 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1370 if ((requests & (1 << bar)) != 0) 1371 pci_release_region(pdev, bar); 1372 } 1373 1374 return (-EINVAL); 1375 } 1376 1377 /* 1378 * We cannot simply re-define pci_get_device() as we would normally do 1379 * and then hide it in linux_pci.c as too many semi-native drivers still 1380 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1381 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1382 */ 1383 static inline struct pci_dev * 1384 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1385 { 1386 1387 return (lkpi_pci_get_device(vendor, device, odev)); 1388 } 1389 1390 /* This is a FreeBSD extension so we can use bus_*(). */ 1391 static inline void 1392 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1393 { 1394 pdev->want_iomap_res = true; 1395 } 1396 1397 static inline bool 1398 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1399 { 1400 1401 return (false); 1402 } 1403 1404 static inline void * 1405 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1406 { 1407 1408 return (NULL); 1409 } 1410 1411 static inline void 1412 pci_ignore_hotplug(struct pci_dev *pdev) 1413 { 1414 } 1415 1416 static inline const char * 1417 pci_power_name(pci_power_t state) 1418 { 1419 int pstate = state + 1; 1420 1421 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1422 return (pci_power_names[pstate]); 1423 else 1424 return (pci_power_names[0]); 1425 } 1426 1427 static inline int 1428 pcie_get_readrq(struct pci_dev *dev) 1429 { 1430 u16 ctl; 1431 1432 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1433 return (-EINVAL); 1434 1435 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1436 } 1437 1438 static inline bool 1439 pci_is_enabled(struct pci_dev *pdev) 1440 { 1441 1442 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1443 PCIM_CMD_BUSMASTEREN) != 0); 1444 } 1445 1446 static inline int 1447 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1448 { 1449 1450 return (0); 1451 } 1452 1453 static inline int 1454 pci_assign_resource(struct pci_dev *pdev, int bar) 1455 { 1456 1457 return (0); 1458 } 1459 1460 static inline int 1461 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1462 { 1463 1464 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1465 if (vector != 0) 1466 return (-EINVAL); 1467 return (pdev->irq); 1468 } 1469 1470 if (pdev->msix_enabled || pdev->msi_enabled) { 1471 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1472 return (-EINVAL); 1473 return (pdev->dev.irq_start + vector); 1474 } 1475 1476 return (-ENXIO); 1477 } 1478 1479 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1480