1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2025 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 #include <linux/device/driver.h> 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_private.h> 49 50 #include <machine/resource.h> 51 52 #include <linux/list.h> 53 #include <linux/dmapool.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/compiler.h> 56 #include <linux/errno.h> 57 #include <asm/atomic.h> 58 #include <asm/memtype.h> 59 #include <linux/device.h> 60 #include <linux/pci_ids.h> 61 #include <linux/pm.h> 62 63 #include <linux/kernel.h> /* pr_debug */ 64 65 struct pci_device_id { 66 uint32_t vendor; 67 uint32_t device; 68 uint32_t subvendor; 69 uint32_t subdevice; 70 uint32_t class; 71 uint32_t class_mask; 72 uintptr_t driver_data; 73 }; 74 75 #define MODULE_DEVICE_TABLE_BUS_pci(_bus, _table) \ 76 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 77 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 78 79 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 80 #define MODULE_DEVICE_TABLE(_bus, _table) \ 81 \ 82 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 83 DEVMETHOD_END \ 84 }; \ 85 \ 86 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 87 "lkpi_" #_bus #_table, \ 88 _ ## _bus ## _ ## _table ## _methods, \ 89 0 \ 90 }; \ 91 \ 92 DRIVER_MODULE(lkpi_ ## _table, _bus, _ ## _bus ## _ ## _table ## _driver,\ 93 0, 0); \ 94 \ 95 MODULE_DEVICE_TABLE_BUS_ ## _bus(_bus, _table) 96 97 #define PCI_ANY_ID -1U 98 99 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 100 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 101 #define PCI_FUNC(devfn) ((devfn) & 0x07) 102 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 103 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 104 105 #define PCI_VDEVICE(_vendor, _device) \ 106 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 108 #define PCI_DEVICE(_vendor, _device) \ 109 .vendor = (_vendor), .device = (_device), \ 110 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 111 112 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 113 114 #define PCI_STD_NUM_BARS 6 115 #define PCI_BASE_ADDRESS_0 PCIR_BARS 116 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 117 #define PCI_VENDOR_ID PCIR_VENDOR 118 #define PCI_DEVICE_ID PCIR_DEVICE 119 #define PCI_COMMAND PCIR_COMMAND 120 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 121 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 122 #define PCI_PRIMARY_BUS PCIR_PRIBUS_1 123 #define PCI_SECONDARY_BUS PCIR_SECBUS_1 124 #define PCI_SUBORDINATE_BUS PCIR_SUBBUS_1 125 #define PCI_SEC_LATENCY_TIMER PCIR_SECLAT_1 126 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 127 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 128 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 129 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 130 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 131 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 132 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 133 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 134 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 135 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 136 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 137 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 138 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 139 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 140 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 141 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 142 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 143 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 144 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 145 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 146 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 147 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 148 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 149 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 150 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 151 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 152 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 153 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 154 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 155 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 156 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 157 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 158 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 159 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 160 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 161 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 162 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 163 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 164 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 165 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 166 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 167 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 168 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 169 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 170 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 171 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 172 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 173 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 174 #define PCI_EXP_LNKCTL2_TLS 0x000f 175 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 176 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 177 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 178 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 179 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 180 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 181 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 182 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 183 184 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 185 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 186 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 187 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 188 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 189 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 190 191 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 192 #define PCI_EXP_DEVSTA_TRPND 0x0020 193 194 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 195 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 196 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 197 198 enum pci_bus_speed { 199 PCI_SPEED_UNKNOWN = -1, 200 PCIE_SPEED_2_5GT, 201 PCIE_SPEED_5_0GT, 202 PCIE_SPEED_8_0GT, 203 PCIE_SPEED_16_0GT, 204 PCIE_SPEED_32_0GT, 205 PCIE_SPEED_64_0GT, 206 }; 207 208 enum pcie_link_width { 209 PCIE_LNK_WIDTH_RESRV = 0x00, 210 PCIE_LNK_X1 = 0x01, 211 PCIE_LNK_X2 = 0x02, 212 PCIE_LNK_X4 = 0x04, 213 PCIE_LNK_X8 = 0x08, 214 PCIE_LNK_X12 = 0x0c, 215 PCIE_LNK_X16 = 0x10, 216 PCIE_LNK_X32 = 0x20, 217 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 218 }; 219 220 #define PCIE_LINK_STATE_L0S 0x00000001 221 #define PCIE_LINK_STATE_L1 0x00000002 222 #define PCIE_LINK_STATE_CLKPM 0x00000004 223 224 typedef int pci_power_t; 225 226 #define PCI_D0 PCI_POWERSTATE_D0 227 #define PCI_D1 PCI_POWERSTATE_D1 228 #define PCI_D2 PCI_POWERSTATE_D2 229 #define PCI_D3hot PCI_POWERSTATE_D3_HOT 230 #define PCI_D3cold PCI_POWERSTATE_D3_COLD 231 232 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 233 234 extern const char *pci_power_names[6]; 235 236 #define PCI_ERR_UNCOR_STATUS PCIR_AER_UC_STATUS 237 #define PCI_ERR_COR_STATUS PCIR_AER_COR_STATUS 238 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 239 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 240 241 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 242 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 243 244 #define PCI_L1SS_CTL1 0x8 245 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 246 247 #define PCI_IRQ_INTX 0x01 248 #define PCI_IRQ_MSI 0x02 249 #define PCI_IRQ_MSIX 0x04 250 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_INTX) 251 252 #if defined(LINUXKPI_VERSION) && (LINUXKPI_VERSION <= 61000) 253 #define PCI_IRQ_LEGACY PCI_IRQ_INTX 254 #endif 255 256 struct pci_dev; 257 258 struct pci_driver { 259 struct list_head node; 260 char *name; 261 const struct pci_device_id *id_table; 262 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 263 void (*remove)(struct pci_dev *dev); 264 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 265 int (*resume) (struct pci_dev *dev); /* Device woken up */ 266 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 267 driver_t bsddriver; 268 devclass_t bsdclass; 269 struct device_driver driver; 270 const struct pci_error_handlers *err_handler; 271 bool isdrm; 272 int bsd_probe_return; 273 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 274 const nvlist_t *pf_config); 275 void (*bsd_iov_uninit)(device_t dev); 276 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 277 const nvlist_t *vf_config); 278 }; 279 280 struct pci_bus { 281 struct pci_dev *self; 282 /* struct pci_bus *parent */ 283 int domain; 284 int number; 285 }; 286 287 extern struct list_head pci_drivers; 288 extern struct list_head pci_devices; 289 extern spinlock_t pci_lock; 290 291 #define __devexit_p(x) x 292 293 #define module_pci_driver(_drv) \ 294 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver) 295 296 struct msi_msg { 297 uint32_t data; 298 }; 299 300 struct pci_msi_desc { 301 struct { 302 bool is_64; 303 } msi_attrib; 304 }; 305 306 struct msi_desc { 307 struct msi_msg msg; 308 struct pci_msi_desc pci; 309 }; 310 311 struct msix_entry { 312 int entry; 313 int vector; 314 }; 315 316 /* 317 * If we find drivers accessing this from multiple KPIs we may have to 318 * refcount objects of this structure. 319 */ 320 struct resource; 321 struct pci_mmio_region { 322 TAILQ_ENTRY(pci_mmio_region) next; 323 struct resource *res; 324 int rid; 325 int type; 326 }; 327 328 struct pci_dev { 329 struct device dev; 330 struct list_head links; 331 struct pci_driver *pdrv; 332 struct pci_bus *bus; 333 struct pci_dev *root; 334 pci_power_t current_state; 335 uint16_t device; 336 uint16_t vendor; 337 uint16_t subsystem_vendor; 338 uint16_t subsystem_device; 339 unsigned int irq; 340 unsigned int devfn; 341 uint32_t class; 342 uint8_t revision; 343 uint8_t msi_cap; 344 uint8_t msix_cap; 345 bool managed; /* devres "pcim_*(). */ 346 bool want_iomap_res; 347 bool msi_enabled; 348 bool msix_enabled; 349 phys_addr_t rom; 350 size_t romlen; 351 struct msi_desc **msi_desc; 352 char *path_name; 353 spinlock_t pcie_cap_lock; 354 355 TAILQ_HEAD(, pci_mmio_region) mmio; 356 }; 357 358 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 359 unsigned int flags); 360 bool pci_device_is_present(struct pci_dev *pdev); 361 362 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 363 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 364 void *linuxkpi_pci_iomap_range(struct pci_dev *, int, 365 unsigned long, unsigned long); 366 void *linuxkpi_pci_iomap(struct pci_dev *, int, unsigned long); 367 void *linuxkpi_pcim_iomap(struct pci_dev *, int, unsigned long); 368 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 369 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 370 const char *name); 371 int linuxkpi_pci_request_region(struct pci_dev *, int, const char *); 372 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 373 int linuxkpi_pcim_request_all_regions(struct pci_dev *, const char *); 374 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 375 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 376 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 377 int nreq); 378 379 /* Internal helper function(s). */ 380 struct pci_dev *lkpinew_pci_dev(device_t); 381 void lkpi_pci_devres_release(struct device *, void *); 382 struct pci_dev *lkpi_pci_get_device(uint32_t, uint32_t, struct pci_dev *); 383 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 384 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 385 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 386 387 #define pci_err(pdev, fmt, ...) \ 388 dev_err(&(pdev)->dev, fmt, ##__VA_ARGS__) 389 #define pci_info(pdev, fmt, ...) \ 390 dev_info(&(pdev)->dev, fmt, ##__VA_ARGS__) 391 392 static inline bool 393 dev_is_pci(struct device *dev) 394 { 395 396 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 397 } 398 399 static inline uint16_t 400 pci_dev_id(struct pci_dev *pdev) 401 { 402 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 403 } 404 405 static inline int 406 pci_resource_type(struct pci_dev *pdev, int bar) 407 { 408 struct pci_map *pm; 409 410 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 411 if (!pm) 412 return (-1); 413 414 if (PCI_BAR_IO(pm->pm_value)) 415 return (SYS_RES_IOPORT); 416 else 417 return (SYS_RES_MEMORY); 418 } 419 420 /* 421 * All drivers just seem to want to inspect the type not flags. 422 */ 423 static inline int 424 pci_resource_flags(struct pci_dev *pdev, int bar) 425 { 426 int type; 427 428 type = pci_resource_type(pdev, bar); 429 if (type < 0) 430 return (0); 431 return (1 << type); 432 } 433 434 static inline const char * 435 pci_name(struct pci_dev *d) 436 { 437 return d->path_name; 438 } 439 440 static inline void * 441 pci_get_drvdata(struct pci_dev *pdev) 442 { 443 444 return dev_get_drvdata(&pdev->dev); 445 } 446 447 static inline void 448 pci_set_drvdata(struct pci_dev *pdev, void *data) 449 { 450 451 dev_set_drvdata(&pdev->dev, data); 452 } 453 454 static inline struct pci_dev * 455 pci_dev_get(struct pci_dev *pdev) 456 { 457 458 if (pdev != NULL) 459 get_device(&pdev->dev); 460 return (pdev); 461 } 462 463 static __inline void 464 pci_dev_put(struct pci_dev *pdev) 465 { 466 467 if (pdev != NULL) 468 put_device(&pdev->dev); 469 } 470 471 static inline int 472 pci_enable_device(struct pci_dev *pdev) 473 { 474 475 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 476 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 477 return (0); 478 } 479 480 static inline void 481 pci_disable_device(struct pci_dev *pdev) 482 { 483 484 pci_disable_busmaster(pdev->dev.bsddev); 485 } 486 487 static inline int 488 pci_set_master(struct pci_dev *pdev) 489 { 490 491 pci_enable_busmaster(pdev->dev.bsddev); 492 return (0); 493 } 494 495 static inline int 496 pci_set_power_state(struct pci_dev *pdev, int state) 497 { 498 499 pci_set_powerstate(pdev->dev.bsddev, state); 500 return (0); 501 } 502 503 static inline int 504 pci_clear_master(struct pci_dev *pdev) 505 { 506 507 pci_disable_busmaster(pdev->dev.bsddev); 508 return (0); 509 } 510 511 static inline bool 512 pci_is_root_bus(struct pci_bus *pbus) 513 { 514 515 return (pbus->self == NULL); 516 } 517 518 static inline struct pci_dev * 519 pci_upstream_bridge(struct pci_dev *pdev) 520 { 521 522 if (pci_is_root_bus(pdev->bus)) 523 return (NULL); 524 525 /* 526 * If we do not have a (proper) "upstream bridge" set, e.g., we point 527 * to ourselves, try to handle this case on the fly like we do 528 * for pcie_find_root_port(). 529 */ 530 if (pdev == pdev->bus->self) { 531 device_t bridge; 532 533 /* 534 * In the case of DRM drivers, the passed device is a child of 535 * `vgapci`. We want to start the lookup from `vgapci`, so the 536 * parent of the passed `drmn`. 537 * 538 * We can use the `isdrm` flag to determine this. 539 */ 540 bridge = pdev->dev.bsddev; 541 if (pdev->pdrv != NULL && pdev->pdrv->isdrm) 542 bridge = device_get_parent(bridge); 543 if (bridge == NULL) 544 goto done; 545 546 bridge = device_get_parent(bridge); 547 if (bridge == NULL) 548 goto done; 549 bridge = device_get_parent(bridge); 550 if (bridge == NULL) 551 goto done; 552 if (device_get_devclass(device_get_parent(bridge)) != 553 devclass_find("pci")) 554 goto done; 555 556 /* 557 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 558 * for it so it can be returned. 559 */ 560 pdev->bus->self = lkpinew_pci_dev(bridge); 561 } 562 done: 563 return (pdev->bus->self); 564 } 565 566 #define pci_request_region(pdev, bar, res_name) \ 567 linuxkpi_pci_request_region(pdev, bar, res_name) 568 #define pci_release_region(pdev, bar) \ 569 linuxkpi_pci_release_region(pdev, bar) 570 #define pci_request_regions(pdev, res_name) \ 571 linuxkpi_pci_request_regions(pdev, res_name) 572 #define pci_release_regions(pdev) \ 573 linuxkpi_pci_release_regions(pdev) 574 #define pcim_request_all_regions(pdev, name) \ 575 linuxkpi_pcim_request_all_regions(pdev, name) 576 577 static inline void 578 lkpi_pci_disable_msix(struct pci_dev *pdev) 579 { 580 581 pci_release_msi(pdev->dev.bsddev); 582 583 /* 584 * The MSIX IRQ numbers associated with this PCI device are no 585 * longer valid and might be re-assigned. Make sure 586 * lkpi_pci_find_irq_dev() does no longer see them by 587 * resetting their references to zero: 588 */ 589 pdev->dev.irq_start = 0; 590 pdev->dev.irq_end = 0; 591 pdev->msix_enabled = false; 592 } 593 /* Only for consistency. No conflict on that one. */ 594 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 595 596 static inline void 597 lkpi_pci_disable_msi(struct pci_dev *pdev) 598 { 599 600 pci_release_msi(pdev->dev.bsddev); 601 602 pdev->dev.irq_start = 0; 603 pdev->dev.irq_end = 0; 604 pdev->irq = pdev->dev.irq; 605 pdev->msi_enabled = false; 606 } 607 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 608 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 609 610 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 611 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 612 613 static inline bus_addr_t 614 pci_bus_address(struct pci_dev *pdev, int bar) 615 { 616 617 return (pci_resource_start(pdev, bar)); 618 } 619 620 #define PCI_CAP_ID_EXP PCIY_EXPRESS 621 #define PCI_CAP_ID_PCIX PCIY_PCIX 622 #define PCI_CAP_ID_AGP PCIY_AGP 623 #define PCI_CAP_ID_PM PCIY_PMG 624 625 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 626 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 627 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 628 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 629 #define PCI_EXP_LNKSTA PCIER_LINK_STA 630 631 static inline int 632 pci_find_capability(struct pci_dev *pdev, int capid) 633 { 634 int reg; 635 636 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 637 return (0); 638 return (reg); 639 } 640 641 static inline int pci_pcie_cap(struct pci_dev *dev) 642 { 643 return pci_find_capability(dev, PCI_CAP_ID_EXP); 644 } 645 646 static inline int 647 pci_find_ext_capability(struct pci_dev *pdev, int capid) 648 { 649 int reg; 650 651 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 652 return (0); 653 return (reg); 654 } 655 656 #define PCIM_PCAP_PME_SHIFT 11 657 static __inline bool 658 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 659 { 660 struct pci_devinfo *dinfo; 661 pcicfgregs *cfg; 662 663 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 664 return (false); 665 666 dinfo = device_get_ivars(pdev->dev.bsddev); 667 cfg = &dinfo->cfg; 668 669 if (cfg->pp.pp_cap == 0) 670 return (false); 671 672 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 673 return (true); 674 675 return (false); 676 } 677 678 static inline int 679 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 680 { 681 682 if (!pci_enable_aspm) 683 return (-EPERM); 684 685 return (-ENXIO); 686 } 687 688 static inline int 689 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 690 { 691 692 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 693 return (0); 694 } 695 696 static inline int 697 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 698 { 699 700 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 701 return (0); 702 } 703 704 static inline int 705 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 706 { 707 708 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 709 return (0); 710 } 711 712 static inline int 713 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 714 { 715 716 pci_write_config(pdev->dev.bsddev, where, val, 1); 717 return (0); 718 } 719 720 static inline int 721 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 722 { 723 724 pci_write_config(pdev->dev.bsddev, where, val, 2); 725 return (0); 726 } 727 728 static inline int 729 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 730 { 731 732 pci_write_config(pdev->dev.bsddev, where, val, 4); 733 return (0); 734 } 735 736 int linux_pci_register_driver(struct pci_driver *pdrv); 737 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 738 void linux_pci_unregister_driver(struct pci_driver *pdrv); 739 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 740 741 #define pci_register_driver(pdrv) \ 742 linux_pci_register_driver(pdrv) 743 #define pci_unregister_driver(pdrv) \ 744 linux_pci_unregister_driver(pdrv) 745 746 /* 747 * Enable msix, positive errors indicate actual number of available 748 * vectors. Negative errors are failures. 749 * 750 * NB: define added to prevent this definition of pci_enable_msix from 751 * clashing with the native FreeBSD version. 752 */ 753 #define pci_enable_msix(...) \ 754 linuxkpi_pci_enable_msix(__VA_ARGS__) 755 756 #define pci_enable_msix_range(...) \ 757 linux_pci_enable_msix_range(__VA_ARGS__) 758 759 static inline int 760 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 761 int minvec, int maxvec) 762 { 763 int nvec = maxvec; 764 int rc; 765 766 if (maxvec < minvec) 767 return (-ERANGE); 768 769 do { 770 rc = pci_enable_msix(dev, entries, nvec); 771 if (rc < 0) { 772 return (rc); 773 } else if (rc > 0) { 774 if (rc < minvec) 775 return (-ENOSPC); 776 nvec = rc; 777 } 778 } while (rc); 779 return (nvec); 780 } 781 782 #define pci_enable_msi(pdev) \ 783 linux_pci_enable_msi(pdev) 784 785 static inline int 786 pci_enable_msi(struct pci_dev *pdev) 787 { 788 789 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 790 } 791 792 static inline int 793 pci_channel_offline(struct pci_dev *pdev) 794 { 795 796 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 797 } 798 799 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 800 { 801 return -ENODEV; 802 } 803 804 static inline void pci_disable_sriov(struct pci_dev *dev) 805 { 806 } 807 808 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \ 809 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) 810 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 811 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 812 #define pcim_iomap(pdev, bar, maxlen) \ 813 linuxkpi_pcim_iomap(pdev, bar, maxlen) 814 #define pci_iounmap(pdev, res) \ 815 linuxkpi_pci_iounmap(pdev, res) 816 817 static inline void 818 lkpi_pci_save_state(struct pci_dev *pdev) 819 { 820 821 pci_save_state(pdev->dev.bsddev); 822 } 823 824 static inline void 825 lkpi_pci_restore_state(struct pci_dev *pdev) 826 { 827 828 pci_restore_state(pdev->dev.bsddev); 829 } 830 831 #define pci_save_state(dev) lkpi_pci_save_state(dev) 832 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 833 834 static inline int 835 linuxkpi_pci_enable_wake(struct pci_dev *pdev, pci_power_t state, bool ena) 836 { 837 /* 838 * We do not currently support this in device.h either to 839 * check if the device is allowed to wake up in first place. 840 */ 841 pr_debug("%s: TODO\n", __func__); 842 return (0); 843 } 844 #define pci_enable_wake(dev, state, ena) \ 845 linuxkpi_pci_enable_wake(dev, state, ena) 846 847 static inline int 848 pci_reset_function(struct pci_dev *pdev) 849 { 850 851 return (-ENOSYS); 852 } 853 854 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 855 const struct pci_device_id _table[] __devinitdata 856 857 /* XXX This should not be necessary. */ 858 #define pcix_set_mmrbc(d, v) 0 859 #define pcix_get_max_mmrbc(d) 0 860 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 861 862 #define PCI_DMA_BIDIRECTIONAL 0 863 #define PCI_DMA_TODEVICE 1 864 #define PCI_DMA_FROMDEVICE 2 865 #define PCI_DMA_NONE 3 866 867 #define pci_pool dma_pool 868 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 869 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 870 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 871 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 872 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 873 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 874 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 875 _size, _vaddr, _dma_handle) 876 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 877 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 878 _sg, _nents, (enum dma_data_direction)_dir) 879 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 880 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 881 (_ptr), (_size), (enum dma_data_direction)_dir) 882 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 883 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 884 _addr, _size, (enum dma_data_direction)_dir) 885 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 886 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 887 _sg, _nents, (enum dma_data_direction)_dir) 888 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 889 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 890 _offset, _size, (enum dma_data_direction)_dir) 891 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 892 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 893 _dma_address, _size, (enum dma_data_direction)_dir) 894 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 895 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 896 dma_mapping_error(&(_pdev)->dev, _dma_addr) 897 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 898 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 899 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 900 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 901 #define pci_unmap_addr dma_unmap_addr 902 #define pci_unmap_addr_set dma_unmap_addr_set 903 #define pci_unmap_len dma_unmap_len 904 #define pci_unmap_len_set dma_unmap_len_set 905 906 typedef unsigned int __bitwise pci_channel_state_t; 907 typedef unsigned int __bitwise pci_ers_result_t; 908 909 enum pci_channel_state { 910 pci_channel_io_normal = 1, 911 pci_channel_io_frozen = 2, 912 pci_channel_io_perm_failure = 3, 913 }; 914 915 enum pci_ers_result { 916 PCI_ERS_RESULT_NONE = 1, 917 PCI_ERS_RESULT_CAN_RECOVER = 2, 918 PCI_ERS_RESULT_NEED_RESET = 3, 919 PCI_ERS_RESULT_DISCONNECT = 4, 920 PCI_ERS_RESULT_RECOVERED = 5, 921 }; 922 923 /* PCI bus error event callbacks */ 924 struct pci_error_handlers { 925 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 926 enum pci_channel_state error); 927 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 928 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 929 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 930 void (*resume)(struct pci_dev *dev); 931 }; 932 933 /* FreeBSD does not support SRIOV - yet */ 934 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 935 { 936 return dev; 937 } 938 939 static inline bool pci_is_pcie(struct pci_dev *dev) 940 { 941 return !!pci_pcie_cap(dev); 942 } 943 944 static inline u16 pcie_flags_reg(struct pci_dev *dev) 945 { 946 int pos; 947 u16 reg16; 948 949 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 950 if (!pos) 951 return 0; 952 953 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 954 955 return reg16; 956 } 957 958 static inline int pci_pcie_type(struct pci_dev *dev) 959 { 960 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 961 } 962 963 static inline int pcie_cap_version(struct pci_dev *dev) 964 { 965 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 966 } 967 968 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 969 { 970 int type = pci_pcie_type(dev); 971 972 return pcie_cap_version(dev) > 1 || 973 type == PCI_EXP_TYPE_ROOT_PORT || 974 type == PCI_EXP_TYPE_ENDPOINT || 975 type == PCI_EXP_TYPE_LEG_END; 976 } 977 978 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 979 { 980 return true; 981 } 982 983 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 984 { 985 int type = pci_pcie_type(dev); 986 987 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 988 (type == PCI_EXP_TYPE_DOWNSTREAM && 989 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 990 } 991 992 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 993 { 994 int type = pci_pcie_type(dev); 995 996 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 997 type == PCI_EXP_TYPE_RC_EC; 998 } 999 1000 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1001 { 1002 if (!pci_is_pcie(dev)) 1003 return false; 1004 1005 switch (pos) { 1006 case PCI_EXP_FLAGS_TYPE: 1007 return true; 1008 case PCI_EXP_DEVCAP: 1009 case PCI_EXP_DEVCTL: 1010 case PCI_EXP_DEVSTA: 1011 return pcie_cap_has_devctl(dev); 1012 case PCI_EXP_LNKCAP: 1013 case PCI_EXP_LNKCTL: 1014 case PCI_EXP_LNKSTA: 1015 return pcie_cap_has_lnkctl(dev); 1016 case PCI_EXP_SLTCAP: 1017 case PCI_EXP_SLTCTL: 1018 case PCI_EXP_SLTSTA: 1019 return pcie_cap_has_sltctl(dev); 1020 case PCI_EXP_RTCTL: 1021 case PCI_EXP_RTCAP: 1022 case PCI_EXP_RTSTA: 1023 return pcie_cap_has_rtctl(dev); 1024 case PCI_EXP_DEVCAP2: 1025 case PCI_EXP_DEVCTL2: 1026 case PCI_EXP_LNKCAP2: 1027 case PCI_EXP_LNKCTL2: 1028 case PCI_EXP_LNKSTA2: 1029 return pcie_cap_version(dev) > 1; 1030 default: 1031 return false; 1032 } 1033 } 1034 1035 static inline int 1036 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1037 { 1038 *dst = 0; 1039 if (pos & 3) 1040 return -EINVAL; 1041 1042 if (!pcie_capability_reg_implemented(dev, pos)) 1043 return -EINVAL; 1044 1045 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1046 } 1047 1048 static inline int 1049 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1050 { 1051 *dst = 0; 1052 if (pos & 3) 1053 return -EINVAL; 1054 1055 if (!pcie_capability_reg_implemented(dev, pos)) 1056 return -EINVAL; 1057 1058 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1059 } 1060 1061 static inline int 1062 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1063 { 1064 if (pos & 1) 1065 return -EINVAL; 1066 1067 if (!pcie_capability_reg_implemented(dev, pos)) 1068 return 0; 1069 1070 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1071 } 1072 1073 static inline int 1074 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1075 uint16_t clear, uint16_t set) 1076 { 1077 int error; 1078 uint16_t v; 1079 1080 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1081 spin_lock(&dev->pcie_cap_lock); 1082 1083 error = pcie_capability_read_word(dev, pos, &v); 1084 if (error == 0) { 1085 v &= ~clear; 1086 v |= set; 1087 error = pcie_capability_write_word(dev, pos, v); 1088 } 1089 1090 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1091 spin_unlock(&dev->pcie_cap_lock); 1092 1093 return (error); 1094 } 1095 1096 static inline int 1097 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1098 { 1099 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1100 } 1101 1102 static inline int 1103 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1104 { 1105 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1106 } 1107 1108 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1109 enum pci_bus_speed *speed, enum pcie_link_width *width) 1110 { 1111 *speed = PCI_SPEED_UNKNOWN; 1112 *width = PCIE_LNK_WIDTH_UNKNOWN; 1113 return (0); 1114 } 1115 1116 static inline int 1117 pci_num_vf(struct pci_dev *dev) 1118 { 1119 return (0); 1120 } 1121 1122 static inline enum pci_bus_speed 1123 pcie_get_speed_cap(struct pci_dev *dev) 1124 { 1125 device_t root; 1126 uint32_t lnkcap, lnkcap2; 1127 int error, pos; 1128 1129 root = device_get_parent(dev->dev.bsddev); 1130 if (root == NULL) 1131 return (PCI_SPEED_UNKNOWN); 1132 root = device_get_parent(root); 1133 if (root == NULL) 1134 return (PCI_SPEED_UNKNOWN); 1135 root = device_get_parent(root); 1136 if (root == NULL) 1137 return (PCI_SPEED_UNKNOWN); 1138 1139 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1140 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1141 return (PCI_SPEED_UNKNOWN); 1142 1143 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1144 return (PCI_SPEED_UNKNOWN); 1145 1146 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1147 1148 if (lnkcap2) { /* PCIe r3.0-compliant */ 1149 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1150 return (PCIE_SPEED_2_5GT); 1151 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1152 return (PCIE_SPEED_5_0GT); 1153 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1154 return (PCIE_SPEED_8_0GT); 1155 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1156 return (PCIE_SPEED_16_0GT); 1157 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1158 return (PCIE_SPEED_32_0GT); 1159 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1160 return (PCIE_SPEED_64_0GT); 1161 } else { /* pre-r3.0 */ 1162 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1163 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1164 return (PCIE_SPEED_2_5GT); 1165 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1166 return (PCIE_SPEED_5_0GT); 1167 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1168 return (PCIE_SPEED_8_0GT); 1169 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1170 return (PCIE_SPEED_16_0GT); 1171 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1172 return (PCIE_SPEED_32_0GT); 1173 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1174 return (PCIE_SPEED_64_0GT); 1175 } 1176 return (PCI_SPEED_UNKNOWN); 1177 } 1178 1179 static inline enum pcie_link_width 1180 pcie_get_width_cap(struct pci_dev *dev) 1181 { 1182 uint32_t lnkcap; 1183 1184 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1185 if (lnkcap) 1186 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1187 1188 return (PCIE_LNK_WIDTH_UNKNOWN); 1189 } 1190 1191 static inline int 1192 pcie_get_mps(struct pci_dev *dev) 1193 { 1194 return (pci_get_max_payload(dev->dev.bsddev)); 1195 } 1196 1197 static inline uint32_t 1198 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1199 { 1200 1201 switch(spd) { 1202 case PCIE_SPEED_64_0GT: 1203 return (64000 * 128 / 130); 1204 case PCIE_SPEED_32_0GT: 1205 return (32000 * 128 / 130); 1206 case PCIE_SPEED_16_0GT: 1207 return (16000 * 128 / 130); 1208 case PCIE_SPEED_8_0GT: 1209 return (8000 * 128 / 130); 1210 case PCIE_SPEED_5_0GT: 1211 return (5000 * 8 / 10); 1212 case PCIE_SPEED_2_5GT: 1213 return (2500 * 8 / 10); 1214 default: 1215 return (0); 1216 } 1217 } 1218 1219 static inline uint32_t 1220 pcie_bandwidth_available(struct pci_dev *pdev, 1221 struct pci_dev **limiting, 1222 enum pci_bus_speed *speed, 1223 enum pcie_link_width *width) 1224 { 1225 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1226 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1227 1228 if (speed) 1229 *speed = nspeed; 1230 if (width) 1231 *width = nwidth; 1232 1233 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1234 } 1235 1236 static inline bool 1237 pcie_aspm_enabled(struct pci_dev *pdev) 1238 { 1239 return (false); 1240 } 1241 1242 static inline struct pci_dev * 1243 pcie_find_root_port(struct pci_dev *pdev) 1244 { 1245 device_t root; 1246 1247 if (pdev->root != NULL) 1248 return (pdev->root); 1249 1250 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1251 if (root == NULL) 1252 return (NULL); 1253 1254 pdev->root = lkpinew_pci_dev(root); 1255 return (pdev->root); 1256 } 1257 1258 /* This is needed when people rip out the device "HotPlug". */ 1259 static inline void 1260 pci_lock_rescan_remove(void) 1261 { 1262 } 1263 1264 static inline void 1265 pci_unlock_rescan_remove(void) 1266 { 1267 } 1268 1269 static __inline void 1270 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1271 { 1272 } 1273 1274 static inline int 1275 pci_rescan_bus(struct pci_bus *pbus) 1276 { 1277 device_t *devlist, parent; 1278 int devcount, error; 1279 1280 if (!device_is_attached(pbus->self->dev.bsddev)) 1281 return (0); 1282 /* pci_rescan_method() will work on the pcib (parent). */ 1283 error = BUS_RESCAN(pbus->self->dev.bsddev); 1284 if (error != 0) 1285 return (0); 1286 1287 parent = device_get_parent(pbus->self->dev.bsddev); 1288 error = device_get_children(parent, &devlist, &devcount); 1289 if (error != 0) 1290 return (0); 1291 if (devcount != 0) 1292 free(devlist, M_TEMP); 1293 1294 return (devcount); 1295 } 1296 1297 /* 1298 * The following functions can be used to attach/detach the LinuxKPI's 1299 * PCI device runtime. The pci_driver and pci_device_id pointer is 1300 * allowed to be NULL. Other pointers must be all valid. 1301 * The pci_dev structure should be zero-initialized before passed 1302 * to the linux_pci_attach_device function. 1303 */ 1304 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1305 const struct pci_device_id *, struct pci_dev *); 1306 extern int linux_pci_detach_device(struct pci_dev *); 1307 1308 static inline int 1309 pci_dev_present(const struct pci_device_id *cur) 1310 { 1311 while (cur != NULL && (cur->vendor || cur->device)) { 1312 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1313 return (1); 1314 } 1315 cur++; 1316 } 1317 return (0); 1318 } 1319 1320 static inline const struct pci_device_id * 1321 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 1322 { 1323 if (ids == NULL) 1324 return (NULL); 1325 1326 for (; 1327 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0; 1328 ids++) 1329 if ((ids->vendor == PCI_ANY_ID || 1330 ids->vendor == pdev->vendor) && 1331 (ids->device == PCI_ANY_ID || 1332 ids->device == pdev->device) && 1333 (ids->subvendor == PCI_ANY_ID || 1334 ids->subvendor == pdev->subsystem_vendor) && 1335 (ids->subdevice == PCI_ANY_ID || 1336 ids->subdevice == pdev->subsystem_device) && 1337 ((ids->class ^ pdev->class) & ids->class_mask) == 0) 1338 return (ids); 1339 1340 return (NULL); 1341 } 1342 1343 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1344 unsigned int bus, unsigned int devfn); 1345 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1346 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1347 1348 struct pci_dev *lkpi_pci_get_slot(struct pci_bus *, unsigned int); 1349 #ifndef WANT_NATIVE_PCI_GET_SLOT 1350 #define pci_get_slot(_pbus, _devfn) \ 1351 lkpi_pci_get_slot(_pbus, _devfn) 1352 #endif 1353 1354 static inline int 1355 pci_domain_nr(struct pci_bus *pbus) 1356 { 1357 1358 return (pbus->domain); 1359 } 1360 1361 static inline int 1362 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1363 int pos, uint32_t *val, int len) 1364 { 1365 1366 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1367 return (0); 1368 } 1369 1370 static inline int 1371 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1372 { 1373 uint32_t tmp; 1374 int ret; 1375 1376 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1377 *val = (u16)tmp; 1378 return (ret); 1379 } 1380 1381 static inline int 1382 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1383 { 1384 uint32_t tmp; 1385 int ret; 1386 1387 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1388 *val = (u8)tmp; 1389 return (ret); 1390 } 1391 1392 static inline int 1393 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1394 uint32_t val, int size) 1395 { 1396 1397 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1398 return (0); 1399 } 1400 1401 static inline int 1402 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1403 uint8_t val) 1404 { 1405 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1406 } 1407 1408 static inline int 1409 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1410 uint16_t val) 1411 { 1412 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1413 } 1414 1415 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1416 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1417 struct pci_dev *lkpi_pci_get_base_class(unsigned int class, 1418 struct pci_dev *from); 1419 #define pci_get_base_class(class, from) lkpi_pci_get_base_class(class, from) 1420 1421 /* -------------------------------------------------------------------------- */ 1422 1423 #define pcim_enable_device(pdev) \ 1424 linuxkpi_pcim_enable_device(pdev) 1425 #define pcim_iomap_table(pdev) \ 1426 linuxkpi_pcim_iomap_table(pdev) 1427 #define pcim_iomap_regions(pdev, mask, name) \ 1428 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1429 1430 static inline int 1431 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1432 { 1433 uint32_t requests, req_mask; 1434 int bar, error; 1435 1436 /* Request all the BARs ("regions") we do not iomap. */ 1437 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1438 for (bar = requests = 0; requests != req_mask; bar++) { 1439 if ((req_mask & (1 << bar)) == 0) 1440 continue; 1441 error = pci_request_region(pdev, bar, name); 1442 if (error != 0 && error != -ENODEV) 1443 goto err; 1444 requests |= (1 << bar); 1445 } 1446 1447 error = pcim_iomap_regions(pdev, mask, name); 1448 if (error != 0) 1449 goto err; 1450 1451 return (0); 1452 1453 err: 1454 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1455 if ((requests & (1 << bar)) != 0) 1456 pci_release_region(pdev, bar); 1457 } 1458 1459 return (-EINVAL); 1460 } 1461 1462 /* 1463 * We cannot simply re-define pci_get_device() as we would normally do 1464 * and then hide it in linux_pci.c as too many semi-native drivers still 1465 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1466 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1467 */ 1468 static inline struct pci_dev * 1469 linuxkpi_pci_get_device(uint32_t vendor, uint32_t device, struct pci_dev *odev) 1470 { 1471 1472 return (lkpi_pci_get_device(vendor, device, odev)); 1473 } 1474 1475 #define for_each_pci_dev(_pdev) \ 1476 while ((_pdev = linuxkpi_pci_get_device(PCI_ANY_ID, PCI_ANY_ID, _pdev)) != NULL) 1477 1478 /* This is a FreeBSD extension so we can use bus_*(). */ 1479 static inline void 1480 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1481 { 1482 pdev->want_iomap_res = true; 1483 } 1484 1485 static inline bool 1486 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1487 { 1488 1489 return (false); 1490 } 1491 1492 static inline void * 1493 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1494 { 1495 1496 return (NULL); 1497 } 1498 1499 static inline void 1500 pci_ignore_hotplug(struct pci_dev *pdev) 1501 { 1502 } 1503 1504 static inline const char * 1505 pci_power_name(pci_power_t state) 1506 { 1507 int pstate = state + 1; 1508 1509 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1510 return (pci_power_names[pstate]); 1511 else 1512 return (pci_power_names[0]); 1513 } 1514 1515 static inline int 1516 pcie_get_readrq(struct pci_dev *dev) 1517 { 1518 u16 ctl; 1519 1520 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1521 return (-EINVAL); 1522 1523 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1524 } 1525 1526 static inline bool 1527 pci_is_enabled(struct pci_dev *pdev) 1528 { 1529 1530 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1531 PCIM_CMD_BUSMASTEREN) != 0); 1532 } 1533 1534 static inline int 1535 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1536 { 1537 1538 return (0); 1539 } 1540 1541 static inline int 1542 pci_assign_resource(struct pci_dev *pdev, int bar) 1543 { 1544 1545 return (0); 1546 } 1547 1548 static inline int 1549 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1550 { 1551 1552 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1553 if (vector != 0) 1554 return (-EINVAL); 1555 return (pdev->irq); 1556 } 1557 1558 if (pdev->msix_enabled || pdev->msi_enabled) { 1559 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1560 return (-EINVAL); 1561 return (pdev->dev.irq_start + vector); 1562 } 1563 1564 return (-ENXIO); 1565 } 1566 1567 static inline int 1568 pci_wake_from_d3(struct pci_dev *pdev, bool enable) 1569 { 1570 1571 pr_debug("%s: TODO\n", __func__); 1572 return (0); 1573 } 1574 1575 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1576