1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/pciio.h> 41 #include <sys/rman.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pci_private.h> 45 46 #include <machine/resource.h> 47 48 #include <linux/list.h> 49 #include <linux/dmapool.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/compiler.h> 52 #include <linux/errno.h> 53 #include <asm/atomic.h> 54 #include <linux/device.h> 55 56 struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class; 62 uint32_t class_mask; 63 uintptr_t driver_data; 64 }; 65 66 #define MODULE_DEVICE_TABLE(bus, table) 67 68 #define PCI_BASE_CLASS_DISPLAY 0x03 69 #define PCI_CLASS_DISPLAY_VGA 0x0300 70 #define PCI_CLASS_DISPLAY_OTHER 0x0380 71 #define PCI_BASE_CLASS_BRIDGE 0x06 72 #define PCI_CLASS_BRIDGE_ISA 0x0601 73 74 #define PCI_ANY_ID (-1) 75 #define PCI_VENDOR_ID_APPLE 0x106b 76 #define PCI_VENDOR_ID_ASUSTEK 0x1043 77 #define PCI_VENDOR_ID_ATI 0x1002 78 #define PCI_VENDOR_ID_DELL 0x1028 79 #define PCI_VENDOR_ID_HP 0x103c 80 #define PCI_VENDOR_ID_IBM 0x1014 81 #define PCI_VENDOR_ID_INTEL 0x8086 82 #define PCI_VENDOR_ID_MELLANOX 0x15b3 83 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 84 #define PCI_VENDOR_ID_SERVERWORKS 0x1166 85 #define PCI_VENDOR_ID_SONY 0x104d 86 #define PCI_VENDOR_ID_TOPSPIN 0x1867 87 #define PCI_VENDOR_ID_VIA 0x1106 88 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 89 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 90 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 91 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 92 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 93 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 94 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 95 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 96 #define PCI_SUBDEVICE_ID_QEMU 0x1100 97 98 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 99 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 100 #define PCI_FUNC(devfn) ((devfn) & 0x07) 101 102 #define PCI_VDEVICE(_vendor, _device) \ 103 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 104 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 105 #define PCI_DEVICE(_vendor, _device) \ 106 .vendor = (_vendor), .device = (_device), \ 107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 108 109 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 110 111 #define PCI_VENDOR_ID PCIR_DEVVENDOR 112 #define PCI_COMMAND PCIR_COMMAND 113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 115 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 116 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 117 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 118 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 119 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 120 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 121 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 122 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 123 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 124 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 125 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 126 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 127 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 128 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 129 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 130 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 131 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 132 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 133 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 134 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 135 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 136 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 137 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 138 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 139 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 140 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 141 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 142 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 143 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 144 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 145 146 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 147 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 148 #define PCI_EXP_DEVSTA_TRPND 0x0020 149 150 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 151 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 152 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 153 154 enum pci_bus_speed { 155 PCI_SPEED_UNKNOWN = -1, 156 PCIE_SPEED_2_5GT, 157 PCIE_SPEED_5_0GT, 158 PCIE_SPEED_8_0GT, 159 }; 160 161 enum pcie_link_width { 162 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 163 }; 164 165 typedef int pci_power_t; 166 167 #define PCI_D0 PCI_POWERSTATE_D0 168 #define PCI_D1 PCI_POWERSTATE_D1 169 #define PCI_D2 PCI_POWERSTATE_D2 170 #define PCI_D3hot PCI_POWERSTATE_D3 171 #define PCI_D3cold 4 172 173 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 174 175 struct pci_dev; 176 177 struct pci_driver { 178 struct list_head links; 179 char *name; 180 const struct pci_device_id *id_table; 181 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 182 void (*remove)(struct pci_dev *dev); 183 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 184 int (*resume) (struct pci_dev *dev); /* Device woken up */ 185 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 186 driver_t bsddriver; 187 devclass_t bsdclass; 188 struct device_driver driver; 189 const struct pci_error_handlers *err_handler; 190 }; 191 192 extern struct list_head pci_drivers; 193 extern struct list_head pci_devices; 194 extern spinlock_t pci_lock; 195 196 #define __devexit_p(x) x 197 198 struct pci_dev { 199 struct device dev; 200 struct list_head links; 201 struct pci_driver *pdrv; 202 uint64_t dma_mask; 203 uint16_t device; 204 uint16_t vendor; 205 uint16_t subsystem_vendor; 206 uint16_t subsystem_device; 207 unsigned int irq; 208 unsigned int devfn; 209 uint32_t class; 210 uint8_t revision; 211 }; 212 213 static inline struct resource_list_entry * 214 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 215 { 216 struct pci_devinfo *dinfo; 217 struct resource_list *rl; 218 219 dinfo = device_get_ivars(pdev->dev.bsddev); 220 rl = &dinfo->resources; 221 return resource_list_find(rl, type, rid); 222 } 223 224 static inline struct resource_list_entry * 225 linux_pci_get_bar(struct pci_dev *pdev, int bar) 226 { 227 struct resource_list_entry *rle; 228 229 bar = PCIR_BAR(bar); 230 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 231 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 232 return (rle); 233 } 234 235 static inline struct device * 236 linux_pci_find_irq_dev(unsigned int irq) 237 { 238 struct pci_dev *pdev; 239 struct device *found; 240 241 found = NULL; 242 spin_lock(&pci_lock); 243 list_for_each_entry(pdev, &pci_devices, links) { 244 if (irq == pdev->dev.irq || 245 (irq >= pdev->dev.msix && irq < pdev->dev.msix_max)) { 246 found = &pdev->dev; 247 break; 248 } 249 } 250 spin_unlock(&pci_lock); 251 return (found); 252 } 253 254 static inline unsigned long 255 pci_resource_start(struct pci_dev *pdev, int bar) 256 { 257 struct resource_list_entry *rle; 258 259 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 260 return (0); 261 return rle->start; 262 } 263 264 static inline unsigned long 265 pci_resource_len(struct pci_dev *pdev, int bar) 266 { 267 struct resource_list_entry *rle; 268 269 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 270 return (0); 271 return rle->count; 272 } 273 274 static inline int 275 pci_resource_type(struct pci_dev *pdev, int bar) 276 { 277 struct pci_map *pm; 278 279 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 280 if (!pm) 281 return (-1); 282 283 if (PCI_BAR_IO(pm->pm_value)) 284 return (SYS_RES_IOPORT); 285 else 286 return (SYS_RES_MEMORY); 287 } 288 289 /* 290 * All drivers just seem to want to inspect the type not flags. 291 */ 292 static inline int 293 pci_resource_flags(struct pci_dev *pdev, int bar) 294 { 295 int type; 296 297 type = pci_resource_type(pdev, bar); 298 if (type < 0) 299 return (0); 300 return (1 << type); 301 } 302 303 static inline const char * 304 pci_name(struct pci_dev *d) 305 { 306 307 return device_get_desc(d->dev.bsddev); 308 } 309 310 static inline void * 311 pci_get_drvdata(struct pci_dev *pdev) 312 { 313 314 return dev_get_drvdata(&pdev->dev); 315 } 316 317 static inline void 318 pci_set_drvdata(struct pci_dev *pdev, void *data) 319 { 320 321 dev_set_drvdata(&pdev->dev, data); 322 } 323 324 static inline int 325 pci_enable_device(struct pci_dev *pdev) 326 { 327 328 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 329 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 330 return (0); 331 } 332 333 static inline void 334 pci_disable_device(struct pci_dev *pdev) 335 { 336 337 pci_disable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 338 pci_disable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 339 } 340 341 static inline int 342 pci_set_master(struct pci_dev *pdev) 343 { 344 345 pci_enable_busmaster(pdev->dev.bsddev); 346 return (0); 347 } 348 349 static inline int 350 pci_set_power_state(struct pci_dev *pdev, int state) 351 { 352 353 pci_set_powerstate(pdev->dev.bsddev, state); 354 return (0); 355 } 356 357 static inline int 358 pci_clear_master(struct pci_dev *pdev) 359 { 360 361 pci_disable_busmaster(pdev->dev.bsddev); 362 return (0); 363 } 364 365 static inline int 366 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 367 { 368 int rid; 369 int type; 370 371 type = pci_resource_type(pdev, bar); 372 if (type < 0) 373 return (-ENODEV); 374 rid = PCIR_BAR(bar); 375 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 376 RF_ACTIVE) == NULL) 377 return (-EINVAL); 378 return (0); 379 } 380 381 static inline void 382 pci_release_region(struct pci_dev *pdev, int bar) 383 { 384 struct resource_list_entry *rle; 385 386 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 387 return; 388 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 389 } 390 391 static inline void 392 pci_release_regions(struct pci_dev *pdev) 393 { 394 int i; 395 396 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 397 pci_release_region(pdev, i); 398 } 399 400 static inline int 401 pci_request_regions(struct pci_dev *pdev, const char *res_name) 402 { 403 int error; 404 int i; 405 406 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 407 error = pci_request_region(pdev, i, res_name); 408 if (error && error != -ENODEV) { 409 pci_release_regions(pdev); 410 return (error); 411 } 412 } 413 return (0); 414 } 415 416 static inline void 417 pci_disable_msix(struct pci_dev *pdev) 418 { 419 420 pci_release_msi(pdev->dev.bsddev); 421 } 422 423 static inline bus_addr_t 424 pci_bus_address(struct pci_dev *pdev, int bar) 425 { 426 427 return (pci_resource_start(pdev, bar)); 428 } 429 430 #define PCI_CAP_ID_EXP PCIY_EXPRESS 431 #define PCI_CAP_ID_PCIX PCIY_PCIX 432 #define PCI_CAP_ID_AGP PCIY_AGP 433 #define PCI_CAP_ID_PM PCIY_PMG 434 435 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 436 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 437 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 438 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 439 #define PCI_EXP_LNKSTA PCIER_LINK_STA 440 441 static inline int 442 pci_find_capability(struct pci_dev *pdev, int capid) 443 { 444 int reg; 445 446 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 447 return (0); 448 return (reg); 449 } 450 451 static inline int pci_pcie_cap(struct pci_dev *dev) 452 { 453 return pci_find_capability(dev, PCI_CAP_ID_EXP); 454 } 455 456 457 static inline int 458 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 459 { 460 461 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 462 return (0); 463 } 464 465 static inline int 466 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 467 { 468 469 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 470 return (0); 471 } 472 473 static inline int 474 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 475 { 476 477 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 478 return (0); 479 } 480 481 static inline int 482 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 483 { 484 485 pci_write_config(pdev->dev.bsddev, where, val, 1); 486 return (0); 487 } 488 489 static inline int 490 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 491 { 492 493 pci_write_config(pdev->dev.bsddev, where, val, 2); 494 return (0); 495 } 496 497 static inline int 498 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 499 { 500 501 pci_write_config(pdev->dev.bsddev, where, val, 4); 502 return (0); 503 } 504 505 extern int pci_register_driver(struct pci_driver *pdrv); 506 extern void pci_unregister_driver(struct pci_driver *pdrv); 507 508 struct msix_entry { 509 int entry; 510 int vector; 511 }; 512 513 /* 514 * Enable msix, positive errors indicate actual number of available 515 * vectors. Negative errors are failures. 516 * 517 * NB: define added to prevent this definition of pci_enable_msix from 518 * clashing with the native FreeBSD version. 519 */ 520 #define pci_enable_msix linux_pci_enable_msix 521 static inline int 522 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 523 { 524 struct resource_list_entry *rle; 525 int error; 526 int avail; 527 int i; 528 529 avail = pci_msix_count(pdev->dev.bsddev); 530 if (avail < nreq) { 531 if (avail == 0) 532 return -EINVAL; 533 return avail; 534 } 535 avail = nreq; 536 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 537 return error; 538 /* 539 * Handle case where "pci_alloc_msix()" may allocate less 540 * interrupts than available and return with no error: 541 */ 542 if (avail < nreq) { 543 pci_release_msi(pdev->dev.bsddev); 544 return avail; 545 } 546 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 547 pdev->dev.msix = rle->start; 548 pdev->dev.msix_max = rle->start + avail; 549 for (i = 0; i < nreq; i++) 550 entries[i].vector = pdev->dev.msix + i; 551 return (0); 552 } 553 554 #define pci_enable_msix_range linux_pci_enable_msix_range 555 static inline int 556 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 557 int minvec, int maxvec) 558 { 559 int nvec = maxvec; 560 int rc; 561 562 if (maxvec < minvec) 563 return (-ERANGE); 564 565 do { 566 rc = pci_enable_msix(dev, entries, nvec); 567 if (rc < 0) { 568 return (rc); 569 } else if (rc > 0) { 570 if (rc < minvec) 571 return (-ENOSPC); 572 nvec = rc; 573 } 574 } while (rc); 575 return (nvec); 576 } 577 578 static inline int pci_channel_offline(struct pci_dev *pdev) 579 { 580 return false; 581 } 582 583 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 584 { 585 return -ENODEV; 586 } 587 static inline void pci_disable_sriov(struct pci_dev *dev) 588 { 589 } 590 591 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 592 const struct pci_device_id _table[] __devinitdata 593 594 595 /* XXX This should not be necessary. */ 596 #define pcix_set_mmrbc(d, v) 0 597 #define pcix_get_max_mmrbc(d) 0 598 #define pcie_set_readrq(d, v) 0 599 600 #define PCI_DMA_BIDIRECTIONAL 0 601 #define PCI_DMA_TODEVICE 1 602 #define PCI_DMA_FROMDEVICE 2 603 #define PCI_DMA_NONE 3 604 605 #define pci_pool dma_pool 606 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 607 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 608 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 609 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 610 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 611 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 612 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 613 _size, _vaddr, _dma_handle) 614 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 615 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 616 _sg, _nents, (enum dma_data_direction)_dir) 617 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 618 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 619 (_ptr), (_size), (enum dma_data_direction)_dir) 620 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 621 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 622 _addr, _size, (enum dma_data_direction)_dir) 623 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 624 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 625 _sg, _nents, (enum dma_data_direction)_dir) 626 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 627 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 628 _offset, _size, (enum dma_data_direction)_dir) 629 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 630 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 631 _dma_address, _size, (enum dma_data_direction)_dir) 632 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 633 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 634 dma_mapping_error(&(_pdev)->dev, _dma_addr) 635 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 636 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 637 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 638 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 639 #define pci_unmap_addr dma_unmap_addr 640 #define pci_unmap_addr_set dma_unmap_addr_set 641 #define pci_unmap_len dma_unmap_len 642 #define pci_unmap_len_set dma_unmap_len_set 643 644 typedef unsigned int __bitwise pci_channel_state_t; 645 typedef unsigned int __bitwise pci_ers_result_t; 646 647 enum pci_channel_state { 648 pci_channel_io_normal = 1, 649 pci_channel_io_frozen = 2, 650 pci_channel_io_perm_failure = 3, 651 }; 652 653 enum pci_ers_result { 654 PCI_ERS_RESULT_NONE = 1, 655 PCI_ERS_RESULT_CAN_RECOVER = 2, 656 PCI_ERS_RESULT_NEED_RESET = 3, 657 PCI_ERS_RESULT_DISCONNECT = 4, 658 PCI_ERS_RESULT_RECOVERED = 5, 659 }; 660 661 662 /* PCI bus error event callbacks */ 663 struct pci_error_handlers { 664 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 665 enum pci_channel_state error); 666 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 667 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 668 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 669 void (*resume)(struct pci_dev *dev); 670 }; 671 672 /* FreeBSD does not support SRIOV - yet */ 673 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 674 { 675 return dev; 676 } 677 678 static inline bool pci_is_pcie(struct pci_dev *dev) 679 { 680 return !!pci_pcie_cap(dev); 681 } 682 683 static inline u16 pcie_flags_reg(struct pci_dev *dev) 684 { 685 int pos; 686 u16 reg16; 687 688 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 689 if (!pos) 690 return 0; 691 692 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 693 694 return reg16; 695 } 696 697 698 static inline int pci_pcie_type(struct pci_dev *dev) 699 { 700 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 701 } 702 703 static inline int pcie_cap_version(struct pci_dev *dev) 704 { 705 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 706 } 707 708 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 709 { 710 int type = pci_pcie_type(dev); 711 712 return pcie_cap_version(dev) > 1 || 713 type == PCI_EXP_TYPE_ROOT_PORT || 714 type == PCI_EXP_TYPE_ENDPOINT || 715 type == PCI_EXP_TYPE_LEG_END; 716 } 717 718 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 719 { 720 return true; 721 } 722 723 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 724 { 725 int type = pci_pcie_type(dev); 726 727 return pcie_cap_version(dev) > 1 || 728 type == PCI_EXP_TYPE_ROOT_PORT || 729 (type == PCI_EXP_TYPE_DOWNSTREAM && 730 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 731 } 732 733 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 734 { 735 int type = pci_pcie_type(dev); 736 737 return pcie_cap_version(dev) > 1 || 738 type == PCI_EXP_TYPE_ROOT_PORT || 739 type == PCI_EXP_TYPE_RC_EC; 740 } 741 742 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 743 { 744 if (!pci_is_pcie(dev)) 745 return false; 746 747 switch (pos) { 748 case PCI_EXP_FLAGS_TYPE: 749 return true; 750 case PCI_EXP_DEVCAP: 751 case PCI_EXP_DEVCTL: 752 case PCI_EXP_DEVSTA: 753 return pcie_cap_has_devctl(dev); 754 case PCI_EXP_LNKCAP: 755 case PCI_EXP_LNKCTL: 756 case PCI_EXP_LNKSTA: 757 return pcie_cap_has_lnkctl(dev); 758 case PCI_EXP_SLTCAP: 759 case PCI_EXP_SLTCTL: 760 case PCI_EXP_SLTSTA: 761 return pcie_cap_has_sltctl(dev); 762 case PCI_EXP_RTCTL: 763 case PCI_EXP_RTCAP: 764 case PCI_EXP_RTSTA: 765 return pcie_cap_has_rtctl(dev); 766 case PCI_EXP_DEVCAP2: 767 case PCI_EXP_DEVCTL2: 768 case PCI_EXP_LNKCAP2: 769 case PCI_EXP_LNKCTL2: 770 case PCI_EXP_LNKSTA2: 771 return pcie_cap_version(dev) > 1; 772 default: 773 return false; 774 } 775 } 776 777 static inline int 778 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 779 { 780 if (pos & 3) 781 return -EINVAL; 782 783 if (!pcie_capability_reg_implemented(dev, pos)) 784 return -EINVAL; 785 786 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 787 } 788 789 static inline int 790 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 791 { 792 if (pos & 3) 793 return -EINVAL; 794 795 if (!pcie_capability_reg_implemented(dev, pos)) 796 return -EINVAL; 797 798 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 799 } 800 801 static inline int 802 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 803 { 804 if (pos & 1) 805 return -EINVAL; 806 807 if (!pcie_capability_reg_implemented(dev, pos)) 808 return 0; 809 810 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 811 } 812 813 static inline int pcie_get_minimum_link(struct pci_dev *dev, 814 enum pci_bus_speed *speed, enum pcie_link_width *width) 815 { 816 *speed = PCI_SPEED_UNKNOWN; 817 *width = PCIE_LNK_WIDTH_UNKNOWN; 818 return (0); 819 } 820 821 static inline int 822 pci_num_vf(struct pci_dev *dev) 823 { 824 return (0); 825 } 826 827 #endif /* _LINUX_PCI_H_ */ 828