1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 #include <linux/device/driver.h> 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_private.h> 49 50 #include <machine/resource.h> 51 52 #include <linux/list.h> 53 #include <linux/dmapool.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/compiler.h> 56 #include <linux/errno.h> 57 #include <asm/atomic.h> 58 #include <asm/memtype.h> 59 #include <linux/device.h> 60 #include <linux/pci_ids.h> 61 #include <linux/pm.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 74 #define MODULE_DEVICE_TABLE(_bus, _table) \ 75 \ 76 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 77 DEVMETHOD_END \ 78 }; \ 79 \ 80 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 81 "lkpi_" #_bus #_table, \ 82 _ ## _bus ## _ ## _table ## _methods, \ 83 0 \ 84 }; \ 85 \ 86 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 87 0, 0); \ 88 \ 89 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 90 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 91 92 #define PCI_ANY_ID -1U 93 94 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 95 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 96 #define PCI_FUNC(devfn) ((devfn) & 0x07) 97 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 98 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 99 100 #define PCI_VDEVICE(_vendor, _device) \ 101 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 102 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 103 #define PCI_DEVICE(_vendor, _device) \ 104 .vendor = (_vendor), .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 107 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 108 109 #define PCI_STD_NUM_BARS 6 110 #define PCI_BASE_ADDRESS_0 PCIR_BARS 111 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 112 #define PCI_VENDOR_ID PCIR_VENDOR 113 #define PCI_DEVICE_ID PCIR_DEVICE 114 #define PCI_COMMAND PCIR_COMMAND 115 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 116 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 117 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 118 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 119 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 120 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 121 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 122 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 123 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 124 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 125 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 126 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 127 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 128 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 129 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 130 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 131 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 132 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 133 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 134 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 135 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 136 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 137 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 138 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 139 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 140 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 141 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 142 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 143 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 144 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 145 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 146 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 147 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 148 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 149 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 150 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 151 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 152 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 153 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 154 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 155 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 156 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 157 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 158 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 159 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 160 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 161 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 162 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 163 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 164 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 165 #define PCI_EXP_LNKCTL2_TLS 0x000f 166 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 167 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 168 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 169 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 170 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 171 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 172 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 173 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 174 175 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 176 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 177 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 178 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 179 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 180 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 181 182 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 183 #define PCI_EXP_DEVSTA_TRPND 0x0020 184 185 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 186 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 187 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 188 189 enum pci_bus_speed { 190 PCI_SPEED_UNKNOWN = -1, 191 PCIE_SPEED_2_5GT, 192 PCIE_SPEED_5_0GT, 193 PCIE_SPEED_8_0GT, 194 PCIE_SPEED_16_0GT, 195 PCIE_SPEED_32_0GT, 196 PCIE_SPEED_64_0GT, 197 }; 198 199 enum pcie_link_width { 200 PCIE_LNK_WIDTH_RESRV = 0x00, 201 PCIE_LNK_X1 = 0x01, 202 PCIE_LNK_X2 = 0x02, 203 PCIE_LNK_X4 = 0x04, 204 PCIE_LNK_X8 = 0x08, 205 PCIE_LNK_X12 = 0x0c, 206 PCIE_LNK_X16 = 0x10, 207 PCIE_LNK_X32 = 0x20, 208 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 209 }; 210 211 #define PCIE_LINK_STATE_L0S 0x00000001 212 #define PCIE_LINK_STATE_L1 0x00000002 213 #define PCIE_LINK_STATE_CLKPM 0x00000004 214 215 typedef int pci_power_t; 216 217 #define PCI_D0 PCI_POWERSTATE_D0 218 #define PCI_D1 PCI_POWERSTATE_D1 219 #define PCI_D2 PCI_POWERSTATE_D2 220 #define PCI_D3hot PCI_POWERSTATE_D3 221 #define PCI_D3cold 4 222 223 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 224 225 extern const char *pci_power_names[6]; 226 227 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 228 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 229 230 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 231 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 232 233 #define PCI_L1SS_CTL1 0x8 234 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 235 236 #define PCI_IRQ_LEGACY 0x01 237 #define PCI_IRQ_MSI 0x02 238 #define PCI_IRQ_MSIX 0x04 239 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 240 241 struct pci_dev; 242 243 struct pci_driver { 244 struct list_head node; 245 char *name; 246 const struct pci_device_id *id_table; 247 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 248 void (*remove)(struct pci_dev *dev); 249 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 250 int (*resume) (struct pci_dev *dev); /* Device woken up */ 251 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 252 driver_t bsddriver; 253 devclass_t bsdclass; 254 struct device_driver driver; 255 const struct pci_error_handlers *err_handler; 256 bool isdrm; 257 int bsd_probe_return; 258 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 259 const nvlist_t *pf_config); 260 void (*bsd_iov_uninit)(device_t dev); 261 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 262 const nvlist_t *vf_config); 263 }; 264 265 struct pci_bus { 266 struct pci_dev *self; 267 /* struct pci_bus *parent */ 268 int domain; 269 int number; 270 }; 271 272 extern struct list_head pci_drivers; 273 extern struct list_head pci_devices; 274 extern spinlock_t pci_lock; 275 276 #define __devexit_p(x) x 277 278 #define module_pci_driver(_drv) \ 279 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver) 280 281 struct msi_msg { 282 uint32_t data; 283 }; 284 285 struct pci_msi_desc { 286 struct { 287 bool is_64; 288 } msi_attrib; 289 }; 290 291 struct msi_desc { 292 struct msi_msg msg; 293 struct pci_msi_desc pci; 294 }; 295 296 struct msix_entry { 297 int entry; 298 int vector; 299 }; 300 301 /* 302 * If we find drivers accessing this from multiple KPIs we may have to 303 * refcount objects of this structure. 304 */ 305 struct resource; 306 struct pci_mmio_region { 307 TAILQ_ENTRY(pci_mmio_region) next; 308 struct resource *res; 309 int rid; 310 int type; 311 }; 312 313 struct pci_dev { 314 struct device dev; 315 struct list_head links; 316 struct pci_driver *pdrv; 317 struct pci_bus *bus; 318 struct pci_dev *root; 319 pci_power_t current_state; 320 uint16_t device; 321 uint16_t vendor; 322 uint16_t subsystem_vendor; 323 uint16_t subsystem_device; 324 unsigned int irq; 325 unsigned int devfn; 326 uint32_t class; 327 uint8_t revision; 328 uint8_t msi_cap; 329 uint8_t msix_cap; 330 bool managed; /* devres "pcim_*(). */ 331 bool want_iomap_res; 332 bool msi_enabled; 333 bool msix_enabled; 334 phys_addr_t rom; 335 size_t romlen; 336 struct msi_desc **msi_desc; 337 char *path_name; 338 spinlock_t pcie_cap_lock; 339 340 TAILQ_HEAD(, pci_mmio_region) mmio; 341 }; 342 343 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 344 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 345 unsigned int flags); 346 bool pci_device_is_present(struct pci_dev *pdev); 347 348 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 349 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 350 void *linuxkpi_pci_iomap_range(struct pci_dev *pdev, int mmio_bar, 351 unsigned long mmio_off, unsigned long mmio_size); 352 void *linuxkpi_pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size); 353 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 354 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 355 const char *name); 356 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 357 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 358 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 359 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 360 int nreq); 361 362 /* Internal helper function(s). */ 363 struct pci_dev *lkpinew_pci_dev(device_t); 364 void lkpi_pci_devres_release(struct device *, void *); 365 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 366 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 367 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 368 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 369 370 static inline bool 371 dev_is_pci(struct device *dev) 372 { 373 374 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 375 } 376 377 static inline uint16_t 378 pci_dev_id(struct pci_dev *pdev) 379 { 380 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 381 } 382 383 static inline int 384 pci_resource_type(struct pci_dev *pdev, int bar) 385 { 386 struct pci_map *pm; 387 388 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 389 if (!pm) 390 return (-1); 391 392 if (PCI_BAR_IO(pm->pm_value)) 393 return (SYS_RES_IOPORT); 394 else 395 return (SYS_RES_MEMORY); 396 } 397 398 /* 399 * All drivers just seem to want to inspect the type not flags. 400 */ 401 static inline int 402 pci_resource_flags(struct pci_dev *pdev, int bar) 403 { 404 int type; 405 406 type = pci_resource_type(pdev, bar); 407 if (type < 0) 408 return (0); 409 return (1 << type); 410 } 411 412 static inline const char * 413 pci_name(struct pci_dev *d) 414 { 415 return d->path_name; 416 } 417 418 static inline void * 419 pci_get_drvdata(struct pci_dev *pdev) 420 { 421 422 return dev_get_drvdata(&pdev->dev); 423 } 424 425 static inline void 426 pci_set_drvdata(struct pci_dev *pdev, void *data) 427 { 428 429 dev_set_drvdata(&pdev->dev, data); 430 } 431 432 static inline struct pci_dev * 433 pci_dev_get(struct pci_dev *pdev) 434 { 435 436 if (pdev != NULL) 437 get_device(&pdev->dev); 438 return (pdev); 439 } 440 441 static __inline void 442 pci_dev_put(struct pci_dev *pdev) 443 { 444 445 if (pdev != NULL) 446 put_device(&pdev->dev); 447 } 448 449 static inline int 450 pci_enable_device(struct pci_dev *pdev) 451 { 452 453 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 454 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 455 return (0); 456 } 457 458 static inline void 459 pci_disable_device(struct pci_dev *pdev) 460 { 461 462 pci_disable_busmaster(pdev->dev.bsddev); 463 } 464 465 static inline int 466 pci_set_master(struct pci_dev *pdev) 467 { 468 469 pci_enable_busmaster(pdev->dev.bsddev); 470 return (0); 471 } 472 473 static inline int 474 pci_set_power_state(struct pci_dev *pdev, int state) 475 { 476 477 pci_set_powerstate(pdev->dev.bsddev, state); 478 return (0); 479 } 480 481 static inline int 482 pci_clear_master(struct pci_dev *pdev) 483 { 484 485 pci_disable_busmaster(pdev->dev.bsddev); 486 return (0); 487 } 488 489 static inline bool 490 pci_is_root_bus(struct pci_bus *pbus) 491 { 492 493 return (pbus->self == NULL); 494 } 495 496 static inline struct pci_dev * 497 pci_upstream_bridge(struct pci_dev *pdev) 498 { 499 500 if (pci_is_root_bus(pdev->bus)) 501 return (NULL); 502 503 /* 504 * If we do not have a (proper) "upstream bridge" set, e.g., we point 505 * to ourselves, try to handle this case on the fly like we do 506 * for pcie_find_root_port(). 507 */ 508 if (pdev == pdev->bus->self) { 509 device_t bridge; 510 511 bridge = device_get_parent(pdev->dev.bsddev); 512 if (bridge == NULL) 513 goto done; 514 bridge = device_get_parent(bridge); 515 if (bridge == NULL) 516 goto done; 517 if (device_get_devclass(device_get_parent(bridge)) != 518 devclass_find("pci")) 519 goto done; 520 521 /* 522 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 523 * for it so it can be returned. 524 */ 525 pdev->bus->self = lkpinew_pci_dev(bridge); 526 } 527 done: 528 return (pdev->bus->self); 529 } 530 531 #define pci_release_region(pdev, bar) linuxkpi_pci_release_region(pdev, bar) 532 #define pci_release_regions(pdev) linuxkpi_pci_release_regions(pdev) 533 #define pci_request_regions(pdev, res_name) \ 534 linuxkpi_pci_request_regions(pdev, res_name) 535 536 static inline void 537 lkpi_pci_disable_msix(struct pci_dev *pdev) 538 { 539 540 pci_release_msi(pdev->dev.bsddev); 541 542 /* 543 * The MSIX IRQ numbers associated with this PCI device are no 544 * longer valid and might be re-assigned. Make sure 545 * lkpi_pci_find_irq_dev() does no longer see them by 546 * resetting their references to zero: 547 */ 548 pdev->dev.irq_start = 0; 549 pdev->dev.irq_end = 0; 550 pdev->msix_enabled = false; 551 } 552 /* Only for consistency. No conflict on that one. */ 553 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 554 555 static inline void 556 lkpi_pci_disable_msi(struct pci_dev *pdev) 557 { 558 559 pci_release_msi(pdev->dev.bsddev); 560 561 pdev->dev.irq_start = 0; 562 pdev->dev.irq_end = 0; 563 pdev->irq = pdev->dev.irq; 564 pdev->msi_enabled = false; 565 } 566 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 567 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 568 569 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 570 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 571 572 static inline bus_addr_t 573 pci_bus_address(struct pci_dev *pdev, int bar) 574 { 575 576 return (pci_resource_start(pdev, bar)); 577 } 578 579 #define PCI_CAP_ID_EXP PCIY_EXPRESS 580 #define PCI_CAP_ID_PCIX PCIY_PCIX 581 #define PCI_CAP_ID_AGP PCIY_AGP 582 #define PCI_CAP_ID_PM PCIY_PMG 583 584 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 585 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 586 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 587 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 588 #define PCI_EXP_LNKSTA PCIER_LINK_STA 589 590 static inline int 591 pci_find_capability(struct pci_dev *pdev, int capid) 592 { 593 int reg; 594 595 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 596 return (0); 597 return (reg); 598 } 599 600 static inline int pci_pcie_cap(struct pci_dev *dev) 601 { 602 return pci_find_capability(dev, PCI_CAP_ID_EXP); 603 } 604 605 static inline int 606 pci_find_ext_capability(struct pci_dev *pdev, int capid) 607 { 608 int reg; 609 610 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 611 return (0); 612 return (reg); 613 } 614 615 #define PCIM_PCAP_PME_SHIFT 11 616 static __inline bool 617 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 618 { 619 struct pci_devinfo *dinfo; 620 pcicfgregs *cfg; 621 622 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 623 return (false); 624 625 dinfo = device_get_ivars(pdev->dev.bsddev); 626 cfg = &dinfo->cfg; 627 628 if (cfg->pp.pp_cap == 0) 629 return (false); 630 631 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 632 return (true); 633 634 return (false); 635 } 636 637 static inline int 638 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 639 { 640 641 if (!pci_enable_aspm) 642 return (-EPERM); 643 644 return (-ENXIO); 645 } 646 647 static inline int 648 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 649 { 650 651 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 652 return (0); 653 } 654 655 static inline int 656 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 657 { 658 659 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 660 return (0); 661 } 662 663 static inline int 664 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 665 { 666 667 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 668 return (0); 669 } 670 671 static inline int 672 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 673 { 674 675 pci_write_config(pdev->dev.bsddev, where, val, 1); 676 return (0); 677 } 678 679 static inline int 680 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 681 { 682 683 pci_write_config(pdev->dev.bsddev, where, val, 2); 684 return (0); 685 } 686 687 static inline int 688 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 689 { 690 691 pci_write_config(pdev->dev.bsddev, where, val, 4); 692 return (0); 693 } 694 695 int linux_pci_register_driver(struct pci_driver *pdrv); 696 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 697 void linux_pci_unregister_driver(struct pci_driver *pdrv); 698 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 699 700 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 701 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 702 703 /* 704 * Enable msix, positive errors indicate actual number of available 705 * vectors. Negative errors are failures. 706 * 707 * NB: define added to prevent this definition of pci_enable_msix from 708 * clashing with the native FreeBSD version. 709 */ 710 #define pci_enable_msix(...) linuxkpi_pci_enable_msix(__VA_ARGS__) 711 712 #define pci_enable_msix_range(...) \ 713 linux_pci_enable_msix_range(__VA_ARGS__) 714 715 static inline int 716 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 717 int minvec, int maxvec) 718 { 719 int nvec = maxvec; 720 int rc; 721 722 if (maxvec < minvec) 723 return (-ERANGE); 724 725 do { 726 rc = pci_enable_msix(dev, entries, nvec); 727 if (rc < 0) { 728 return (rc); 729 } else if (rc > 0) { 730 if (rc < minvec) 731 return (-ENOSPC); 732 nvec = rc; 733 } 734 } while (rc); 735 return (nvec); 736 } 737 738 #define pci_enable_msi(pdev) \ 739 linux_pci_enable_msi(pdev) 740 741 static inline int 742 pci_enable_msi(struct pci_dev *pdev) 743 { 744 745 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 746 } 747 748 static inline int 749 pci_channel_offline(struct pci_dev *pdev) 750 { 751 752 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 753 } 754 755 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 756 { 757 return -ENODEV; 758 } 759 760 static inline void pci_disable_sriov(struct pci_dev *dev) 761 { 762 } 763 764 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \ 765 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) 766 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 767 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 768 #define pci_iounmap(pdev, res) linuxkpi_pci_iounmap(pdev, res) 769 770 static inline void 771 lkpi_pci_save_state(struct pci_dev *pdev) 772 { 773 774 pci_save_state(pdev->dev.bsddev); 775 } 776 777 static inline void 778 lkpi_pci_restore_state(struct pci_dev *pdev) 779 { 780 781 pci_restore_state(pdev->dev.bsddev); 782 } 783 784 #define pci_save_state(dev) lkpi_pci_save_state(dev) 785 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 786 787 static inline int 788 pci_reset_function(struct pci_dev *pdev) 789 { 790 791 return (-ENOSYS); 792 } 793 794 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 795 const struct pci_device_id _table[] __devinitdata 796 797 /* XXX This should not be necessary. */ 798 #define pcix_set_mmrbc(d, v) 0 799 #define pcix_get_max_mmrbc(d) 0 800 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 801 802 #define PCI_DMA_BIDIRECTIONAL 0 803 #define PCI_DMA_TODEVICE 1 804 #define PCI_DMA_FROMDEVICE 2 805 #define PCI_DMA_NONE 3 806 807 #define pci_pool dma_pool 808 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 809 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 810 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 811 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 812 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 813 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 814 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 815 _size, _vaddr, _dma_handle) 816 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 817 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 818 _sg, _nents, (enum dma_data_direction)_dir) 819 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 820 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 821 (_ptr), (_size), (enum dma_data_direction)_dir) 822 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 823 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 824 _addr, _size, (enum dma_data_direction)_dir) 825 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 826 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 827 _sg, _nents, (enum dma_data_direction)_dir) 828 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 829 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 830 _offset, _size, (enum dma_data_direction)_dir) 831 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 832 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 833 _dma_address, _size, (enum dma_data_direction)_dir) 834 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 835 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 836 dma_mapping_error(&(_pdev)->dev, _dma_addr) 837 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 838 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 839 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 840 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 841 #define pci_unmap_addr dma_unmap_addr 842 #define pci_unmap_addr_set dma_unmap_addr_set 843 #define pci_unmap_len dma_unmap_len 844 #define pci_unmap_len_set dma_unmap_len_set 845 846 typedef unsigned int __bitwise pci_channel_state_t; 847 typedef unsigned int __bitwise pci_ers_result_t; 848 849 enum pci_channel_state { 850 pci_channel_io_normal = 1, 851 pci_channel_io_frozen = 2, 852 pci_channel_io_perm_failure = 3, 853 }; 854 855 enum pci_ers_result { 856 PCI_ERS_RESULT_NONE = 1, 857 PCI_ERS_RESULT_CAN_RECOVER = 2, 858 PCI_ERS_RESULT_NEED_RESET = 3, 859 PCI_ERS_RESULT_DISCONNECT = 4, 860 PCI_ERS_RESULT_RECOVERED = 5, 861 }; 862 863 /* PCI bus error event callbacks */ 864 struct pci_error_handlers { 865 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 866 enum pci_channel_state error); 867 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 868 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 869 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 870 void (*resume)(struct pci_dev *dev); 871 }; 872 873 /* FreeBSD does not support SRIOV - yet */ 874 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 875 { 876 return dev; 877 } 878 879 static inline bool pci_is_pcie(struct pci_dev *dev) 880 { 881 return !!pci_pcie_cap(dev); 882 } 883 884 static inline u16 pcie_flags_reg(struct pci_dev *dev) 885 { 886 int pos; 887 u16 reg16; 888 889 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 890 if (!pos) 891 return 0; 892 893 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 894 895 return reg16; 896 } 897 898 static inline int pci_pcie_type(struct pci_dev *dev) 899 { 900 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 901 } 902 903 static inline int pcie_cap_version(struct pci_dev *dev) 904 { 905 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 906 } 907 908 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 909 { 910 int type = pci_pcie_type(dev); 911 912 return pcie_cap_version(dev) > 1 || 913 type == PCI_EXP_TYPE_ROOT_PORT || 914 type == PCI_EXP_TYPE_ENDPOINT || 915 type == PCI_EXP_TYPE_LEG_END; 916 } 917 918 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 919 { 920 return true; 921 } 922 923 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 924 { 925 int type = pci_pcie_type(dev); 926 927 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 928 (type == PCI_EXP_TYPE_DOWNSTREAM && 929 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 930 } 931 932 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 933 { 934 int type = pci_pcie_type(dev); 935 936 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 937 type == PCI_EXP_TYPE_RC_EC; 938 } 939 940 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 941 { 942 if (!pci_is_pcie(dev)) 943 return false; 944 945 switch (pos) { 946 case PCI_EXP_FLAGS_TYPE: 947 return true; 948 case PCI_EXP_DEVCAP: 949 case PCI_EXP_DEVCTL: 950 case PCI_EXP_DEVSTA: 951 return pcie_cap_has_devctl(dev); 952 case PCI_EXP_LNKCAP: 953 case PCI_EXP_LNKCTL: 954 case PCI_EXP_LNKSTA: 955 return pcie_cap_has_lnkctl(dev); 956 case PCI_EXP_SLTCAP: 957 case PCI_EXP_SLTCTL: 958 case PCI_EXP_SLTSTA: 959 return pcie_cap_has_sltctl(dev); 960 case PCI_EXP_RTCTL: 961 case PCI_EXP_RTCAP: 962 case PCI_EXP_RTSTA: 963 return pcie_cap_has_rtctl(dev); 964 case PCI_EXP_DEVCAP2: 965 case PCI_EXP_DEVCTL2: 966 case PCI_EXP_LNKCAP2: 967 case PCI_EXP_LNKCTL2: 968 case PCI_EXP_LNKSTA2: 969 return pcie_cap_version(dev) > 1; 970 default: 971 return false; 972 } 973 } 974 975 static inline int 976 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 977 { 978 *dst = 0; 979 if (pos & 3) 980 return -EINVAL; 981 982 if (!pcie_capability_reg_implemented(dev, pos)) 983 return -EINVAL; 984 985 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 986 } 987 988 static inline int 989 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 990 { 991 *dst = 0; 992 if (pos & 3) 993 return -EINVAL; 994 995 if (!pcie_capability_reg_implemented(dev, pos)) 996 return -EINVAL; 997 998 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 999 } 1000 1001 static inline int 1002 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1003 { 1004 if (pos & 1) 1005 return -EINVAL; 1006 1007 if (!pcie_capability_reg_implemented(dev, pos)) 1008 return 0; 1009 1010 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1011 } 1012 1013 static inline int 1014 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1015 uint16_t clear, uint16_t set) 1016 { 1017 int error; 1018 uint16_t v; 1019 1020 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1021 spin_lock(&dev->pcie_cap_lock); 1022 1023 error = pcie_capability_read_word(dev, pos, &v); 1024 if (error == 0) { 1025 v &= ~clear; 1026 v |= set; 1027 error = pcie_capability_write_word(dev, pos, v); 1028 } 1029 1030 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1031 spin_unlock(&dev->pcie_cap_lock); 1032 1033 return (error); 1034 } 1035 1036 static inline int 1037 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1038 { 1039 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1040 } 1041 1042 static inline int 1043 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1044 { 1045 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1046 } 1047 1048 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1049 enum pci_bus_speed *speed, enum pcie_link_width *width) 1050 { 1051 *speed = PCI_SPEED_UNKNOWN; 1052 *width = PCIE_LNK_WIDTH_UNKNOWN; 1053 return (0); 1054 } 1055 1056 static inline int 1057 pci_num_vf(struct pci_dev *dev) 1058 { 1059 return (0); 1060 } 1061 1062 static inline enum pci_bus_speed 1063 pcie_get_speed_cap(struct pci_dev *dev) 1064 { 1065 device_t root; 1066 uint32_t lnkcap, lnkcap2; 1067 int error, pos; 1068 1069 root = device_get_parent(dev->dev.bsddev); 1070 if (root == NULL) 1071 return (PCI_SPEED_UNKNOWN); 1072 root = device_get_parent(root); 1073 if (root == NULL) 1074 return (PCI_SPEED_UNKNOWN); 1075 root = device_get_parent(root); 1076 if (root == NULL) 1077 return (PCI_SPEED_UNKNOWN); 1078 1079 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1080 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1081 return (PCI_SPEED_UNKNOWN); 1082 1083 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1084 return (PCI_SPEED_UNKNOWN); 1085 1086 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1087 1088 if (lnkcap2) { /* PCIe r3.0-compliant */ 1089 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1090 return (PCIE_SPEED_2_5GT); 1091 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1092 return (PCIE_SPEED_5_0GT); 1093 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1094 return (PCIE_SPEED_8_0GT); 1095 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1096 return (PCIE_SPEED_16_0GT); 1097 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1098 return (PCIE_SPEED_32_0GT); 1099 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1100 return (PCIE_SPEED_64_0GT); 1101 } else { /* pre-r3.0 */ 1102 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1103 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1104 return (PCIE_SPEED_2_5GT); 1105 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1106 return (PCIE_SPEED_5_0GT); 1107 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1108 return (PCIE_SPEED_8_0GT); 1109 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1110 return (PCIE_SPEED_16_0GT); 1111 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1112 return (PCIE_SPEED_32_0GT); 1113 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1114 return (PCIE_SPEED_64_0GT); 1115 } 1116 return (PCI_SPEED_UNKNOWN); 1117 } 1118 1119 static inline enum pcie_link_width 1120 pcie_get_width_cap(struct pci_dev *dev) 1121 { 1122 uint32_t lnkcap; 1123 1124 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1125 if (lnkcap) 1126 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1127 1128 return (PCIE_LNK_WIDTH_UNKNOWN); 1129 } 1130 1131 static inline int 1132 pcie_get_mps(struct pci_dev *dev) 1133 { 1134 return (pci_get_max_payload(dev->dev.bsddev)); 1135 } 1136 1137 static inline uint32_t 1138 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1139 { 1140 1141 switch(spd) { 1142 case PCIE_SPEED_64_0GT: 1143 return (64000 * 128 / 130); 1144 case PCIE_SPEED_32_0GT: 1145 return (32000 * 128 / 130); 1146 case PCIE_SPEED_16_0GT: 1147 return (16000 * 128 / 130); 1148 case PCIE_SPEED_8_0GT: 1149 return (8000 * 128 / 130); 1150 case PCIE_SPEED_5_0GT: 1151 return (5000 * 8 / 10); 1152 case PCIE_SPEED_2_5GT: 1153 return (2500 * 8 / 10); 1154 default: 1155 return (0); 1156 } 1157 } 1158 1159 static inline uint32_t 1160 pcie_bandwidth_available(struct pci_dev *pdev, 1161 struct pci_dev **limiting, 1162 enum pci_bus_speed *speed, 1163 enum pcie_link_width *width) 1164 { 1165 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1166 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1167 1168 if (speed) 1169 *speed = nspeed; 1170 if (width) 1171 *width = nwidth; 1172 1173 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1174 } 1175 1176 static inline bool 1177 pcie_aspm_enabled(struct pci_dev *pdev) 1178 { 1179 return (false); 1180 } 1181 1182 static inline struct pci_dev * 1183 pcie_find_root_port(struct pci_dev *pdev) 1184 { 1185 device_t root; 1186 1187 if (pdev->root != NULL) 1188 return (pdev->root); 1189 1190 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1191 if (root == NULL) 1192 return (NULL); 1193 1194 pdev->root = lkpinew_pci_dev(root); 1195 return (pdev->root); 1196 } 1197 1198 /* This is needed when people rip out the device "HotPlug". */ 1199 static inline void 1200 pci_lock_rescan_remove(void) 1201 { 1202 } 1203 1204 static inline void 1205 pci_unlock_rescan_remove(void) 1206 { 1207 } 1208 1209 static __inline void 1210 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1211 { 1212 } 1213 1214 static inline int 1215 pci_rescan_bus(struct pci_bus *pbus) 1216 { 1217 device_t *devlist, parent; 1218 int devcount, error; 1219 1220 if (!device_is_attached(pbus->self->dev.bsddev)) 1221 return (0); 1222 /* pci_rescan_method() will work on the pcib (parent). */ 1223 error = BUS_RESCAN(pbus->self->dev.bsddev); 1224 if (error != 0) 1225 return (0); 1226 1227 parent = device_get_parent(pbus->self->dev.bsddev); 1228 error = device_get_children(parent, &devlist, &devcount); 1229 if (error != 0) 1230 return (0); 1231 if (devcount != 0) 1232 free(devlist, M_TEMP); 1233 1234 return (devcount); 1235 } 1236 1237 /* 1238 * The following functions can be used to attach/detach the LinuxKPI's 1239 * PCI device runtime. The pci_driver and pci_device_id pointer is 1240 * allowed to be NULL. Other pointers must be all valid. 1241 * The pci_dev structure should be zero-initialized before passed 1242 * to the linux_pci_attach_device function. 1243 */ 1244 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1245 const struct pci_device_id *, struct pci_dev *); 1246 extern int linux_pci_detach_device(struct pci_dev *); 1247 1248 static inline int 1249 pci_dev_present(const struct pci_device_id *cur) 1250 { 1251 while (cur != NULL && (cur->vendor || cur->device)) { 1252 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1253 return (1); 1254 } 1255 cur++; 1256 } 1257 return (0); 1258 } 1259 1260 static inline const struct pci_device_id * 1261 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 1262 { 1263 if (ids == NULL) 1264 return (NULL); 1265 1266 for (; 1267 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0; 1268 ids++) 1269 if ((ids->vendor == PCI_ANY_ID || 1270 ids->vendor == pdev->vendor) && 1271 (ids->device == PCI_ANY_ID || 1272 ids->device == pdev->device) && 1273 (ids->subvendor == PCI_ANY_ID || 1274 ids->subvendor == pdev->subsystem_vendor) && 1275 (ids->subdevice == PCI_ANY_ID || 1276 ids->subdevice == pdev->subsystem_device) && 1277 ((ids->class ^ pdev->class) & ids->class_mask) == 0) 1278 return (ids); 1279 1280 return (NULL); 1281 } 1282 1283 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1284 unsigned int bus, unsigned int devfn); 1285 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1286 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1287 1288 static inline int 1289 pci_domain_nr(struct pci_bus *pbus) 1290 { 1291 1292 return (pbus->domain); 1293 } 1294 1295 static inline int 1296 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1297 int pos, uint32_t *val, int len) 1298 { 1299 1300 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1301 return (0); 1302 } 1303 1304 static inline int 1305 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1306 { 1307 uint32_t tmp; 1308 int ret; 1309 1310 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1311 *val = (u16)tmp; 1312 return (ret); 1313 } 1314 1315 static inline int 1316 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1317 { 1318 uint32_t tmp; 1319 int ret; 1320 1321 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1322 *val = (u8)tmp; 1323 return (ret); 1324 } 1325 1326 static inline int 1327 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1328 uint32_t val, int size) 1329 { 1330 1331 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1332 return (0); 1333 } 1334 1335 static inline int 1336 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1337 uint8_t val) 1338 { 1339 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1340 } 1341 1342 static inline int 1343 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1344 uint16_t val) 1345 { 1346 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1347 } 1348 1349 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1350 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1351 1352 /* -------------------------------------------------------------------------- */ 1353 1354 #define pcim_enable_device(pdev) linuxkpi_pcim_enable_device(pdev) 1355 #define pcim_iomap_table(pdev) linuxkpi_pcim_iomap_table(pdev) 1356 #define pcim_iomap_regions(pdev, mask, name) \ 1357 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1358 1359 static inline int 1360 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1361 { 1362 uint32_t requests, req_mask; 1363 int bar, error; 1364 1365 /* Request all the BARs ("regions") we do not iomap. */ 1366 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1367 for (bar = requests = 0; requests != req_mask; bar++) { 1368 if ((req_mask & (1 << bar)) == 0) 1369 continue; 1370 error = pci_request_region(pdev, bar, name); 1371 if (error != 0 && error != -ENODEV) 1372 goto err; 1373 requests |= (1 << bar); 1374 } 1375 1376 error = pcim_iomap_regions(pdev, mask, name); 1377 if (error != 0) 1378 goto err; 1379 1380 return (0); 1381 1382 err: 1383 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1384 if ((requests & (1 << bar)) != 0) 1385 pci_release_region(pdev, bar); 1386 } 1387 1388 return (-EINVAL); 1389 } 1390 1391 /* 1392 * We cannot simply re-define pci_get_device() as we would normally do 1393 * and then hide it in linux_pci.c as too many semi-native drivers still 1394 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1395 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1396 */ 1397 static inline struct pci_dev * 1398 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1399 { 1400 1401 return (lkpi_pci_get_device(vendor, device, odev)); 1402 } 1403 1404 /* This is a FreeBSD extension so we can use bus_*(). */ 1405 static inline void 1406 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1407 { 1408 pdev->want_iomap_res = true; 1409 } 1410 1411 static inline bool 1412 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1413 { 1414 1415 return (false); 1416 } 1417 1418 static inline void * 1419 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1420 { 1421 1422 return (NULL); 1423 } 1424 1425 static inline void 1426 pci_ignore_hotplug(struct pci_dev *pdev) 1427 { 1428 } 1429 1430 static inline const char * 1431 pci_power_name(pci_power_t state) 1432 { 1433 int pstate = state + 1; 1434 1435 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1436 return (pci_power_names[pstate]); 1437 else 1438 return (pci_power_names[0]); 1439 } 1440 1441 static inline int 1442 pcie_get_readrq(struct pci_dev *dev) 1443 { 1444 u16 ctl; 1445 1446 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1447 return (-EINVAL); 1448 1449 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1450 } 1451 1452 static inline bool 1453 pci_is_enabled(struct pci_dev *pdev) 1454 { 1455 1456 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1457 PCIM_CMD_BUSMASTEREN) != 0); 1458 } 1459 1460 static inline int 1461 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1462 { 1463 1464 return (0); 1465 } 1466 1467 static inline int 1468 pci_assign_resource(struct pci_dev *pdev, int bar) 1469 { 1470 1471 return (0); 1472 } 1473 1474 static inline int 1475 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1476 { 1477 1478 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1479 if (vector != 0) 1480 return (-EINVAL); 1481 return (pdev->irq); 1482 } 1483 1484 if (pdev->msix_enabled || pdev->msi_enabled) { 1485 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1486 return (-EINVAL); 1487 return (pdev->dev.irq_start + vector); 1488 } 1489 1490 return (-ENXIO); 1491 } 1492 1493 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1494