1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/nv.h> 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 #include <linux/pm.h> 63 64 struct pci_device_id { 65 uint32_t vendor; 66 uint32_t device; 67 uint32_t subvendor; 68 uint32_t subdevice; 69 uint32_t class; 70 uint32_t class_mask; 71 uintptr_t driver_data; 72 }; 73 74 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 75 #define MODULE_DEVICE_TABLE(_bus, _table) \ 76 \ 77 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 78 DEVMETHOD_END \ 79 }; \ 80 \ 81 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 82 "lkpi_" #_bus #_table, \ 83 _ ## _bus ## _ ## _table ## _methods, \ 84 0 \ 85 }; \ 86 \ 87 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 88 0, 0); \ 89 \ 90 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 91 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 92 93 #define PCI_ANY_ID -1U 94 95 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 96 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 97 #define PCI_FUNC(devfn) ((devfn) & 0x07) 98 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 99 100 #define PCI_VDEVICE(_vendor, _device) \ 101 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 102 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 103 #define PCI_DEVICE(_vendor, _device) \ 104 .vendor = (_vendor), .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 107 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 108 109 #define PCI_VENDOR_ID PCIR_VENDOR 110 #define PCI_DEVICE_ID PCIR_DEVICE 111 #define PCI_COMMAND PCIR_COMMAND 112 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 115 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 116 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 117 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 118 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 119 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 120 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 121 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 122 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 123 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 124 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 125 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 126 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 127 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 128 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 129 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 130 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 131 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 132 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 133 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 134 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 135 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 136 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 137 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 138 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 139 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 140 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 141 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 142 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 143 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 144 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 145 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 146 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 147 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 148 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 149 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 150 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 151 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 152 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 153 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 154 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 155 #define PCI_EXP_LNKCTL2_TLS 0x000f 156 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 157 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 158 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 159 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 160 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 161 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 162 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 163 164 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 165 #define PCI_EXP_DEVSTA_TRPND 0x0020 166 167 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 168 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 169 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 170 171 enum pci_bus_speed { 172 PCI_SPEED_UNKNOWN = -1, 173 PCIE_SPEED_2_5GT, 174 PCIE_SPEED_5_0GT, 175 PCIE_SPEED_8_0GT, 176 PCIE_SPEED_16_0GT, 177 }; 178 179 enum pcie_link_width { 180 PCIE_LNK_WIDTH_RESRV = 0x00, 181 PCIE_LNK_X1 = 0x01, 182 PCIE_LNK_X2 = 0x02, 183 PCIE_LNK_X4 = 0x04, 184 PCIE_LNK_X8 = 0x08, 185 PCIE_LNK_X12 = 0x0c, 186 PCIE_LNK_X16 = 0x10, 187 PCIE_LNK_X32 = 0x20, 188 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 189 }; 190 191 #define PCIE_LINK_STATE_L0S 0x00000001 192 #define PCIE_LINK_STATE_L1 0x00000002 193 #define PCIE_LINK_STATE_CLKPM 0x00000004 194 195 typedef int pci_power_t; 196 197 #define PCI_D0 PCI_POWERSTATE_D0 198 #define PCI_D1 PCI_POWERSTATE_D1 199 #define PCI_D2 PCI_POWERSTATE_D2 200 #define PCI_D3hot PCI_POWERSTATE_D3 201 #define PCI_D3cold 4 202 203 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 204 205 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 206 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 207 208 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 209 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 210 211 #define PCI_L1SS_CTL1 0x8 212 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 213 214 #define PCI_IRQ_LEGACY 0x01 215 #define PCI_IRQ_MSI 0x02 216 #define PCI_IRQ_MSIX 0x04 217 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 218 219 struct pci_dev; 220 221 struct pci_driver { 222 struct list_head node; 223 char *name; 224 const struct pci_device_id *id_table; 225 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 226 void (*remove)(struct pci_dev *dev); 227 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 228 int (*resume) (struct pci_dev *dev); /* Device woken up */ 229 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 230 driver_t bsddriver; 231 devclass_t bsdclass; 232 struct device_driver driver; 233 const struct pci_error_handlers *err_handler; 234 bool isdrm; 235 int bsd_probe_return; 236 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 237 const nvlist_t *pf_config); 238 void (*bsd_iov_uninit)(device_t dev); 239 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 240 const nvlist_t *vf_config); 241 }; 242 243 struct pci_bus { 244 struct pci_dev *self; 245 int domain; 246 int number; 247 }; 248 249 extern struct list_head pci_drivers; 250 extern struct list_head pci_devices; 251 extern spinlock_t pci_lock; 252 253 #define __devexit_p(x) x 254 255 #define module_pci_driver(_driver) \ 256 \ 257 static inline int \ 258 _pci_init(void) \ 259 { \ 260 \ 261 return (linux_pci_register_driver(&_driver)); \ 262 } \ 263 \ 264 static inline void \ 265 _pci_exit(void) \ 266 { \ 267 \ 268 linux_pci_unregister_driver(&_driver); \ 269 } \ 270 \ 271 module_init(_pci_init); \ 272 module_exit(_pci_exit) 273 274 /* 275 * If we find drivers accessing this from multiple KPIs we may have to 276 * refcount objects of this structure. 277 */ 278 struct pci_mmio_region { 279 TAILQ_ENTRY(pci_mmio_region) next; 280 struct resource *res; 281 int rid; 282 int type; 283 }; 284 285 struct pci_dev { 286 struct device dev; 287 struct list_head links; 288 struct pci_driver *pdrv; 289 struct pci_bus *bus; 290 struct pci_dev *root; 291 uint16_t device; 292 uint16_t vendor; 293 uint16_t subsystem_vendor; 294 uint16_t subsystem_device; 295 unsigned int irq; 296 unsigned int devfn; 297 uint32_t class; 298 uint8_t revision; 299 bool managed; /* devres "pcim_*(). */ 300 bool want_iomap_res; 301 bool msi_enabled; 302 bool msix_enabled; 303 phys_addr_t rom; 304 size_t romlen; 305 306 TAILQ_HEAD(, pci_mmio_region) mmio; 307 }; 308 309 /* We need some meta-struct to keep track of these for devres. */ 310 struct pci_devres { 311 bool enable_io; 312 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 313 uint8_t region_mask; 314 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 315 }; 316 struct pcim_iomap_devres { 317 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 318 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 319 }; 320 321 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 322 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 323 unsigned int flags); 324 325 /* Internal helper function(s). */ 326 struct pci_dev *lkpinew_pci_dev(device_t); 327 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev); 328 void lkpi_pci_devres_release(struct device *, void *); 329 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size); 330 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev); 331 void lkpi_pcim_iomap_table_release(struct device *, void *); 332 333 static inline bool 334 dev_is_pci(struct device *dev) 335 { 336 337 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 338 } 339 340 static inline int 341 pci_resource_type(struct pci_dev *pdev, int bar) 342 { 343 struct pci_map *pm; 344 345 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 346 if (!pm) 347 return (-1); 348 349 if (PCI_BAR_IO(pm->pm_value)) 350 return (SYS_RES_IOPORT); 351 else 352 return (SYS_RES_MEMORY); 353 } 354 355 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 356 struct resource_list *rl, int type, int rid); 357 358 static inline struct resource_list_entry * 359 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 360 { 361 struct pci_devinfo *dinfo; 362 struct resource_list *rl; 363 struct resource_list_entry *rle; 364 365 dinfo = device_get_ivars(pdev->dev.bsddev); 366 rl = &dinfo->resources; 367 rle = resource_list_find(rl, type, rid); 368 /* Reserve resources for this BAR if needed. */ 369 if (rle == NULL && reserve_bar) 370 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 371 return (rle); 372 } 373 374 static inline struct resource_list_entry * 375 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 376 { 377 int type; 378 379 type = pci_resource_type(pdev, bar); 380 if (type < 0) 381 return (NULL); 382 bar = PCIR_BAR(bar); 383 return (linux_pci_get_rle(pdev, type, bar, reserve)); 384 } 385 386 static inline struct device * 387 linux_pci_find_irq_dev(unsigned int irq) 388 { 389 struct pci_dev *pdev; 390 struct device *found; 391 392 found = NULL; 393 spin_lock(&pci_lock); 394 list_for_each_entry(pdev, &pci_devices, links) { 395 if (irq == pdev->dev.irq || 396 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 397 found = &pdev->dev; 398 break; 399 } 400 } 401 spin_unlock(&pci_lock); 402 return (found); 403 } 404 405 /* 406 * All drivers just seem to want to inspect the type not flags. 407 */ 408 static inline int 409 pci_resource_flags(struct pci_dev *pdev, int bar) 410 { 411 int type; 412 413 type = pci_resource_type(pdev, bar); 414 if (type < 0) 415 return (0); 416 return (1 << type); 417 } 418 419 static inline const char * 420 pci_name(struct pci_dev *d) 421 { 422 423 return device_get_desc(d->dev.bsddev); 424 } 425 426 static inline void * 427 pci_get_drvdata(struct pci_dev *pdev) 428 { 429 430 return dev_get_drvdata(&pdev->dev); 431 } 432 433 static inline void 434 pci_set_drvdata(struct pci_dev *pdev, void *data) 435 { 436 437 dev_set_drvdata(&pdev->dev, data); 438 } 439 440 static inline struct pci_dev * 441 pci_dev_get(struct pci_dev *pdev) 442 { 443 444 if (pdev != NULL) 445 get_device(&pdev->dev); 446 return (pdev); 447 } 448 449 static __inline void 450 pci_dev_put(struct pci_dev *pdev) 451 { 452 453 if (pdev != NULL) 454 put_device(&pdev->dev); 455 } 456 457 static inline int 458 pci_enable_device(struct pci_dev *pdev) 459 { 460 461 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 462 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 463 return (0); 464 } 465 466 static inline void 467 pci_disable_device(struct pci_dev *pdev) 468 { 469 470 pci_disable_busmaster(pdev->dev.bsddev); 471 } 472 473 static inline int 474 pci_set_master(struct pci_dev *pdev) 475 { 476 477 pci_enable_busmaster(pdev->dev.bsddev); 478 return (0); 479 } 480 481 static inline int 482 pci_set_power_state(struct pci_dev *pdev, int state) 483 { 484 485 pci_set_powerstate(pdev->dev.bsddev, state); 486 return (0); 487 } 488 489 static inline int 490 pci_clear_master(struct pci_dev *pdev) 491 { 492 493 pci_disable_busmaster(pdev->dev.bsddev); 494 return (0); 495 } 496 497 static inline bool 498 pci_is_root_bus(struct pci_bus *pbus) 499 { 500 501 return (pbus->self == NULL); 502 } 503 504 static inline struct pci_dev * 505 pci_upstream_bridge(struct pci_dev *pdev) 506 { 507 508 if (pci_is_root_bus(pdev->bus)) 509 return (NULL); 510 511 /* 512 * If we do not have a (proper) "upstream bridge" set, e.g., we point 513 * to ourselves, try to handle this case on the fly like we do 514 * for pcie_find_root_port(). 515 */ 516 if (pdev == pdev->bus->self) { 517 device_t bridge; 518 519 bridge = device_get_parent(pdev->dev.bsddev); 520 if (bridge == NULL) 521 goto done; 522 bridge = device_get_parent(bridge); 523 if (bridge == NULL) 524 goto done; 525 if (device_get_devclass(device_get_parent(bridge)) != 526 devclass_find("pci")) 527 goto done; 528 529 /* 530 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 531 * for it so it can be returned. 532 */ 533 pdev->bus->self = lkpinew_pci_dev(bridge); 534 } 535 done: 536 return (pdev->bus->self); 537 } 538 539 static inline struct pci_devres * 540 lkpi_pci_devres_find(struct pci_dev *pdev) 541 { 542 543 if (!pdev->managed) 544 return (NULL); 545 546 return (lkpi_pci_devres_get_alloc(pdev)); 547 } 548 549 static inline void 550 pci_release_region(struct pci_dev *pdev, int bar) 551 { 552 struct resource_list_entry *rle; 553 struct pci_devres *dr; 554 struct pci_mmio_region *mmio, *p; 555 556 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 557 return; 558 559 /* 560 * As we implicitly track the requests we also need to clear them on 561 * release. Do clear before resource release. 562 */ 563 dr = lkpi_pci_devres_find(pdev); 564 if (dr != NULL) { 565 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 566 " region_table res %p != rel->res %p\n", __func__, pdev, 567 bar, dr->region_table[bar], rle->res)); 568 dr->region_table[bar] = NULL; 569 dr->region_mask &= ~(1 << bar); 570 } 571 572 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 573 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 574 continue; 575 TAILQ_REMOVE(&pdev->mmio, mmio, next); 576 free(mmio, M_DEVBUF); 577 } 578 579 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 580 } 581 582 static inline void 583 pci_release_regions(struct pci_dev *pdev) 584 { 585 int i; 586 587 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 588 pci_release_region(pdev, i); 589 } 590 591 static inline int 592 pci_request_regions(struct pci_dev *pdev, const char *res_name) 593 { 594 int error; 595 int i; 596 597 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 598 error = pci_request_region(pdev, i, res_name); 599 if (error && error != -ENODEV) { 600 pci_release_regions(pdev); 601 return (error); 602 } 603 } 604 return (0); 605 } 606 607 static inline void 608 lkpi_pci_disable_msix(struct pci_dev *pdev) 609 { 610 611 pci_release_msi(pdev->dev.bsddev); 612 613 /* 614 * The MSIX IRQ numbers associated with this PCI device are no 615 * longer valid and might be re-assigned. Make sure 616 * linux_pci_find_irq_dev() does no longer see them by 617 * resetting their references to zero: 618 */ 619 pdev->dev.irq_start = 0; 620 pdev->dev.irq_end = 0; 621 pdev->msix_enabled = false; 622 } 623 /* Only for consistency. No conflict on that one. */ 624 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 625 626 static inline void 627 lkpi_pci_disable_msi(struct pci_dev *pdev) 628 { 629 630 pci_release_msi(pdev->dev.bsddev); 631 632 pdev->dev.irq_start = 0; 633 pdev->dev.irq_end = 0; 634 pdev->irq = pdev->dev.irq; 635 pdev->msi_enabled = false; 636 } 637 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 638 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 639 640 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 641 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 642 643 static inline bus_addr_t 644 pci_bus_address(struct pci_dev *pdev, int bar) 645 { 646 647 return (pci_resource_start(pdev, bar)); 648 } 649 650 #define PCI_CAP_ID_EXP PCIY_EXPRESS 651 #define PCI_CAP_ID_PCIX PCIY_PCIX 652 #define PCI_CAP_ID_AGP PCIY_AGP 653 #define PCI_CAP_ID_PM PCIY_PMG 654 655 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 656 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 657 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 658 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 659 #define PCI_EXP_LNKSTA PCIER_LINK_STA 660 661 static inline int 662 pci_find_capability(struct pci_dev *pdev, int capid) 663 { 664 int reg; 665 666 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 667 return (0); 668 return (reg); 669 } 670 671 static inline int pci_pcie_cap(struct pci_dev *dev) 672 { 673 return pci_find_capability(dev, PCI_CAP_ID_EXP); 674 } 675 676 static inline int 677 pci_find_ext_capability(struct pci_dev *pdev, int capid) 678 { 679 int reg; 680 681 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 682 return (0); 683 return (reg); 684 } 685 686 #define PCIM_PCAP_PME_SHIFT 11 687 static __inline bool 688 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 689 { 690 struct pci_devinfo *dinfo; 691 pcicfgregs *cfg; 692 693 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 694 return (false); 695 696 dinfo = device_get_ivars(pdev->dev.bsddev); 697 cfg = &dinfo->cfg; 698 699 if (cfg->pp.pp_cap == 0) 700 return (false); 701 702 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 703 return (true); 704 705 return (false); 706 } 707 708 static inline int 709 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 710 { 711 712 if (!pci_enable_aspm) 713 return (-EPERM); 714 715 return (-ENXIO); 716 } 717 718 static inline int 719 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 720 { 721 722 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 723 return (0); 724 } 725 726 static inline int 727 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 728 { 729 730 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 731 return (0); 732 } 733 734 static inline int 735 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 736 { 737 738 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 739 return (0); 740 } 741 742 static inline int 743 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 744 { 745 746 pci_write_config(pdev->dev.bsddev, where, val, 1); 747 return (0); 748 } 749 750 static inline int 751 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 752 { 753 754 pci_write_config(pdev->dev.bsddev, where, val, 2); 755 return (0); 756 } 757 758 static inline int 759 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 760 { 761 762 pci_write_config(pdev->dev.bsddev, where, val, 4); 763 return (0); 764 } 765 766 int linux_pci_register_driver(struct pci_driver *pdrv); 767 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 768 void linux_pci_unregister_driver(struct pci_driver *pdrv); 769 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 770 771 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 772 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 773 774 struct msix_entry { 775 int entry; 776 int vector; 777 }; 778 779 /* 780 * Enable msix, positive errors indicate actual number of available 781 * vectors. Negative errors are failures. 782 * 783 * NB: define added to prevent this definition of pci_enable_msix from 784 * clashing with the native FreeBSD version. 785 */ 786 #define pci_enable_msix(...) \ 787 linux_pci_enable_msix(__VA_ARGS__) 788 789 static inline int 790 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 791 { 792 struct resource_list_entry *rle; 793 int error; 794 int avail; 795 int i; 796 797 avail = pci_msix_count(pdev->dev.bsddev); 798 if (avail < nreq) { 799 if (avail == 0) 800 return -EINVAL; 801 return avail; 802 } 803 avail = nreq; 804 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 805 return error; 806 /* 807 * Handle case where "pci_alloc_msix()" may allocate less 808 * interrupts than available and return with no error: 809 */ 810 if (avail < nreq) { 811 pci_release_msi(pdev->dev.bsddev); 812 return avail; 813 } 814 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 815 pdev->dev.irq_start = rle->start; 816 pdev->dev.irq_end = rle->start + avail; 817 for (i = 0; i < nreq; i++) 818 entries[i].vector = pdev->dev.irq_start + i; 819 pdev->msix_enabled = true; 820 return (0); 821 } 822 823 #define pci_enable_msix_range(...) \ 824 linux_pci_enable_msix_range(__VA_ARGS__) 825 826 static inline int 827 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 828 int minvec, int maxvec) 829 { 830 int nvec = maxvec; 831 int rc; 832 833 if (maxvec < minvec) 834 return (-ERANGE); 835 836 do { 837 rc = pci_enable_msix(dev, entries, nvec); 838 if (rc < 0) { 839 return (rc); 840 } else if (rc > 0) { 841 if (rc < minvec) 842 return (-ENOSPC); 843 nvec = rc; 844 } 845 } while (rc); 846 return (nvec); 847 } 848 849 #define pci_enable_msi(pdev) \ 850 linux_pci_enable_msi(pdev) 851 852 static inline int 853 pci_enable_msi(struct pci_dev *pdev) 854 { 855 struct resource_list_entry *rle; 856 int error; 857 int avail; 858 859 avail = pci_msi_count(pdev->dev.bsddev); 860 if (avail < 1) 861 return -EINVAL; 862 863 avail = 1; /* this function only enable one MSI IRQ */ 864 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 865 return error; 866 867 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 868 pdev->dev.irq_start = rle->start; 869 pdev->dev.irq_end = rle->start + avail; 870 pdev->irq = rle->start; 871 pdev->msi_enabled = true; 872 return (0); 873 } 874 875 static inline int 876 pci_channel_offline(struct pci_dev *pdev) 877 { 878 879 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 880 } 881 882 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 883 { 884 return -ENODEV; 885 } 886 887 static inline void pci_disable_sriov(struct pci_dev *dev) 888 { 889 } 890 891 static inline void * 892 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 893 { 894 struct resource *res; 895 896 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 897 if (res == NULL) 898 return (NULL); 899 /* This is a FreeBSD extension so we can use bus_*(). */ 900 if (pdev->want_iomap_res) 901 return (res); 902 return ((void *)rman_get_bushandle(res)); 903 } 904 905 static inline void 906 pci_iounmap(struct pci_dev *pdev, void *res) 907 { 908 struct pci_mmio_region *mmio, *p; 909 910 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 911 if (res != (void *)rman_get_bushandle(mmio->res)) 912 continue; 913 bus_release_resource(pdev->dev.bsddev, 914 mmio->type, mmio->rid, mmio->res); 915 TAILQ_REMOVE(&pdev->mmio, mmio, next); 916 free(mmio, M_DEVBUF); 917 return; 918 } 919 } 920 921 static inline void 922 lkpi_pci_save_state(struct pci_dev *pdev) 923 { 924 925 pci_save_state(pdev->dev.bsddev); 926 } 927 928 static inline void 929 lkpi_pci_restore_state(struct pci_dev *pdev) 930 { 931 932 pci_restore_state(pdev->dev.bsddev); 933 } 934 935 #define pci_save_state(dev) lkpi_pci_save_state(dev) 936 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 937 938 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 939 const struct pci_device_id _table[] __devinitdata 940 941 /* XXX This should not be necessary. */ 942 #define pcix_set_mmrbc(d, v) 0 943 #define pcix_get_max_mmrbc(d) 0 944 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 945 946 #define PCI_DMA_BIDIRECTIONAL 0 947 #define PCI_DMA_TODEVICE 1 948 #define PCI_DMA_FROMDEVICE 2 949 #define PCI_DMA_NONE 3 950 951 #define pci_pool dma_pool 952 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 953 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 954 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 955 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 956 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 957 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 958 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 959 _size, _vaddr, _dma_handle) 960 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 961 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 962 _sg, _nents, (enum dma_data_direction)_dir) 963 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 964 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 965 (_ptr), (_size), (enum dma_data_direction)_dir) 966 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 967 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 968 _addr, _size, (enum dma_data_direction)_dir) 969 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 970 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 971 _sg, _nents, (enum dma_data_direction)_dir) 972 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 973 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 974 _offset, _size, (enum dma_data_direction)_dir) 975 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 976 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 977 _dma_address, _size, (enum dma_data_direction)_dir) 978 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 979 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 980 dma_mapping_error(&(_pdev)->dev, _dma_addr) 981 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 982 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 983 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 984 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 985 #define pci_unmap_addr dma_unmap_addr 986 #define pci_unmap_addr_set dma_unmap_addr_set 987 #define pci_unmap_len dma_unmap_len 988 #define pci_unmap_len_set dma_unmap_len_set 989 990 typedef unsigned int __bitwise pci_channel_state_t; 991 typedef unsigned int __bitwise pci_ers_result_t; 992 993 enum pci_channel_state { 994 pci_channel_io_normal = 1, 995 pci_channel_io_frozen = 2, 996 pci_channel_io_perm_failure = 3, 997 }; 998 999 enum pci_ers_result { 1000 PCI_ERS_RESULT_NONE = 1, 1001 PCI_ERS_RESULT_CAN_RECOVER = 2, 1002 PCI_ERS_RESULT_NEED_RESET = 3, 1003 PCI_ERS_RESULT_DISCONNECT = 4, 1004 PCI_ERS_RESULT_RECOVERED = 5, 1005 }; 1006 1007 /* PCI bus error event callbacks */ 1008 struct pci_error_handlers { 1009 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1010 enum pci_channel_state error); 1011 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1012 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1013 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1014 void (*resume)(struct pci_dev *dev); 1015 }; 1016 1017 /* FreeBSD does not support SRIOV - yet */ 1018 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1019 { 1020 return dev; 1021 } 1022 1023 static inline bool pci_is_pcie(struct pci_dev *dev) 1024 { 1025 return !!pci_pcie_cap(dev); 1026 } 1027 1028 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1029 { 1030 int pos; 1031 u16 reg16; 1032 1033 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1034 if (!pos) 1035 return 0; 1036 1037 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1038 1039 return reg16; 1040 } 1041 1042 static inline int pci_pcie_type(struct pci_dev *dev) 1043 { 1044 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1045 } 1046 1047 static inline int pcie_cap_version(struct pci_dev *dev) 1048 { 1049 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1050 } 1051 1052 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1053 { 1054 int type = pci_pcie_type(dev); 1055 1056 return pcie_cap_version(dev) > 1 || 1057 type == PCI_EXP_TYPE_ROOT_PORT || 1058 type == PCI_EXP_TYPE_ENDPOINT || 1059 type == PCI_EXP_TYPE_LEG_END; 1060 } 1061 1062 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1063 { 1064 return true; 1065 } 1066 1067 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1068 { 1069 int type = pci_pcie_type(dev); 1070 1071 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1072 (type == PCI_EXP_TYPE_DOWNSTREAM && 1073 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1074 } 1075 1076 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1077 { 1078 int type = pci_pcie_type(dev); 1079 1080 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1081 type == PCI_EXP_TYPE_RC_EC; 1082 } 1083 1084 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1085 { 1086 if (!pci_is_pcie(dev)) 1087 return false; 1088 1089 switch (pos) { 1090 case PCI_EXP_FLAGS_TYPE: 1091 return true; 1092 case PCI_EXP_DEVCAP: 1093 case PCI_EXP_DEVCTL: 1094 case PCI_EXP_DEVSTA: 1095 return pcie_cap_has_devctl(dev); 1096 case PCI_EXP_LNKCAP: 1097 case PCI_EXP_LNKCTL: 1098 case PCI_EXP_LNKSTA: 1099 return pcie_cap_has_lnkctl(dev); 1100 case PCI_EXP_SLTCAP: 1101 case PCI_EXP_SLTCTL: 1102 case PCI_EXP_SLTSTA: 1103 return pcie_cap_has_sltctl(dev); 1104 case PCI_EXP_RTCTL: 1105 case PCI_EXP_RTCAP: 1106 case PCI_EXP_RTSTA: 1107 return pcie_cap_has_rtctl(dev); 1108 case PCI_EXP_DEVCAP2: 1109 case PCI_EXP_DEVCTL2: 1110 case PCI_EXP_LNKCAP2: 1111 case PCI_EXP_LNKCTL2: 1112 case PCI_EXP_LNKSTA2: 1113 return pcie_cap_version(dev) > 1; 1114 default: 1115 return false; 1116 } 1117 } 1118 1119 static inline int 1120 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1121 { 1122 if (pos & 3) 1123 return -EINVAL; 1124 1125 if (!pcie_capability_reg_implemented(dev, pos)) 1126 return -EINVAL; 1127 1128 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1129 } 1130 1131 static inline int 1132 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1133 { 1134 if (pos & 3) 1135 return -EINVAL; 1136 1137 if (!pcie_capability_reg_implemented(dev, pos)) 1138 return -EINVAL; 1139 1140 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1141 } 1142 1143 static inline int 1144 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1145 { 1146 if (pos & 1) 1147 return -EINVAL; 1148 1149 if (!pcie_capability_reg_implemented(dev, pos)) 1150 return 0; 1151 1152 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1153 } 1154 1155 static inline int 1156 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1157 { 1158 int error; 1159 uint16_t v; 1160 1161 error = pcie_capability_read_word(dev, pos, &v); 1162 if (error != 0) 1163 return (error); 1164 1165 v |= val; 1166 1167 error = pcie_capability_write_word(dev, pos, v); 1168 return (error); 1169 } 1170 1171 static inline int 1172 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1173 { 1174 int error; 1175 uint16_t v; 1176 1177 error = pcie_capability_read_word(dev, pos, &v); 1178 if (error != 0) 1179 return (error); 1180 1181 v &= ~val; 1182 1183 error = pcie_capability_write_word(dev, pos, v); 1184 return (error); 1185 } 1186 1187 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1188 enum pci_bus_speed *speed, enum pcie_link_width *width) 1189 { 1190 *speed = PCI_SPEED_UNKNOWN; 1191 *width = PCIE_LNK_WIDTH_UNKNOWN; 1192 return (0); 1193 } 1194 1195 static inline int 1196 pci_num_vf(struct pci_dev *dev) 1197 { 1198 return (0); 1199 } 1200 1201 static inline enum pci_bus_speed 1202 pcie_get_speed_cap(struct pci_dev *dev) 1203 { 1204 device_t root; 1205 uint32_t lnkcap, lnkcap2; 1206 int error, pos; 1207 1208 root = device_get_parent(dev->dev.bsddev); 1209 if (root == NULL) 1210 return (PCI_SPEED_UNKNOWN); 1211 root = device_get_parent(root); 1212 if (root == NULL) 1213 return (PCI_SPEED_UNKNOWN); 1214 root = device_get_parent(root); 1215 if (root == NULL) 1216 return (PCI_SPEED_UNKNOWN); 1217 1218 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1219 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1220 return (PCI_SPEED_UNKNOWN); 1221 1222 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1223 return (PCI_SPEED_UNKNOWN); 1224 1225 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1226 1227 if (lnkcap2) { /* PCIe r3.0-compliant */ 1228 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1229 return (PCIE_SPEED_2_5GT); 1230 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1231 return (PCIE_SPEED_5_0GT); 1232 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1233 return (PCIE_SPEED_8_0GT); 1234 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1235 return (PCIE_SPEED_16_0GT); 1236 } else { /* pre-r3.0 */ 1237 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1238 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1239 return (PCIE_SPEED_2_5GT); 1240 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1241 return (PCIE_SPEED_5_0GT); 1242 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1243 return (PCIE_SPEED_8_0GT); 1244 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1245 return (PCIE_SPEED_16_0GT); 1246 } 1247 return (PCI_SPEED_UNKNOWN); 1248 } 1249 1250 static inline enum pcie_link_width 1251 pcie_get_width_cap(struct pci_dev *dev) 1252 { 1253 uint32_t lnkcap; 1254 1255 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1256 if (lnkcap) 1257 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1258 1259 return (PCIE_LNK_WIDTH_UNKNOWN); 1260 } 1261 1262 static inline int 1263 pcie_get_mps(struct pci_dev *dev) 1264 { 1265 return (pci_get_max_payload(dev->dev.bsddev)); 1266 } 1267 1268 static inline uint32_t 1269 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1270 { 1271 1272 switch(spd) { 1273 case PCIE_SPEED_16_0GT: 1274 return (16000 * 128 / 130); 1275 case PCIE_SPEED_8_0GT: 1276 return (8000 * 128 / 130); 1277 case PCIE_SPEED_5_0GT: 1278 return (5000 * 8 / 10); 1279 case PCIE_SPEED_2_5GT: 1280 return (2500 * 8 / 10); 1281 default: 1282 return (0); 1283 } 1284 } 1285 1286 static inline uint32_t 1287 pcie_bandwidth_available(struct pci_dev *pdev, 1288 struct pci_dev **limiting, 1289 enum pci_bus_speed *speed, 1290 enum pcie_link_width *width) 1291 { 1292 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1293 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1294 1295 if (speed) 1296 *speed = nspeed; 1297 if (width) 1298 *width = nwidth; 1299 1300 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1301 } 1302 1303 static inline struct pci_dev * 1304 pcie_find_root_port(struct pci_dev *pdev) 1305 { 1306 device_t root; 1307 1308 if (pdev->root != NULL) 1309 return (pdev->root); 1310 1311 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1312 if (root == NULL) 1313 return (NULL); 1314 1315 pdev->root = lkpinew_pci_dev(root); 1316 return (pdev->root); 1317 } 1318 1319 /* This is needed when people rip out the device "HotPlug". */ 1320 static inline void 1321 pci_lock_rescan_remove(void) 1322 { 1323 } 1324 1325 static inline void 1326 pci_unlock_rescan_remove(void) 1327 { 1328 } 1329 1330 static __inline void 1331 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1332 { 1333 } 1334 1335 /* 1336 * The following functions can be used to attach/detach the LinuxKPI's 1337 * PCI device runtime. The pci_driver and pci_device_id pointer is 1338 * allowed to be NULL. Other pointers must be all valid. 1339 * The pci_dev structure should be zero-initialized before passed 1340 * to the linux_pci_attach_device function. 1341 */ 1342 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1343 const struct pci_device_id *, struct pci_dev *); 1344 extern int linux_pci_detach_device(struct pci_dev *); 1345 1346 static inline int 1347 pci_dev_present(const struct pci_device_id *cur) 1348 { 1349 while (cur != NULL && (cur->vendor || cur->device)) { 1350 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1351 return (1); 1352 } 1353 cur++; 1354 } 1355 return (0); 1356 } 1357 1358 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1359 unsigned int bus, unsigned int devfn); 1360 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1361 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1362 1363 static inline int 1364 pci_domain_nr(struct pci_bus *pbus) 1365 { 1366 1367 return (pbus->domain); 1368 } 1369 1370 static inline int 1371 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1372 int pos, uint32_t *val, int len) 1373 { 1374 1375 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1376 return (0); 1377 } 1378 1379 static inline int 1380 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1381 { 1382 uint32_t tmp; 1383 int ret; 1384 1385 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1386 *val = (u16)tmp; 1387 return (ret); 1388 } 1389 1390 static inline int 1391 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1392 { 1393 uint32_t tmp; 1394 int ret; 1395 1396 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1397 *val = (u8)tmp; 1398 return (ret); 1399 } 1400 1401 static inline int 1402 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1403 uint32_t val, int size) 1404 { 1405 1406 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1407 return (0); 1408 } 1409 1410 static inline int 1411 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1412 uint8_t val) 1413 { 1414 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1415 } 1416 1417 static inline int 1418 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1419 uint16_t val) 1420 { 1421 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1422 } 1423 1424 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1425 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1426 1427 /* -------------------------------------------------------------------------- */ 1428 1429 static inline int 1430 pcim_enable_device(struct pci_dev *pdev) 1431 { 1432 struct pci_devres *dr; 1433 int error; 1434 1435 /* Here we cannot run through the pdev->managed check. */ 1436 dr = lkpi_pci_devres_get_alloc(pdev); 1437 if (dr == NULL) 1438 return (-ENOMEM); 1439 1440 /* If resources were enabled before do not do it again. */ 1441 if (dr->enable_io) 1442 return (0); 1443 1444 error = pci_enable_device(pdev); 1445 if (error == 0) 1446 dr->enable_io = true; 1447 1448 /* This device is not managed. */ 1449 pdev->managed = true; 1450 1451 return (error); 1452 } 1453 1454 static inline void __iomem ** 1455 pcim_iomap_table(struct pci_dev *pdev) 1456 { 1457 struct pcim_iomap_devres *dr; 1458 1459 dr = lkpi_pcim_iomap_devres_find(pdev); 1460 if (dr == NULL) 1461 return (NULL); 1462 1463 /* 1464 * If the driver has manually set a flag to be able to request the 1465 * resource to use bus_read/write_<n>, return the shadow table. 1466 */ 1467 if (pdev->want_iomap_res) 1468 return ((void **)dr->res_table); 1469 1470 /* This is the Linux default. */ 1471 return (dr->mmio_table); 1472 } 1473 1474 static inline int 1475 pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, const char *name) 1476 { 1477 struct pcim_iomap_devres *dr; 1478 void *res; 1479 uint32_t mappings; 1480 int bar; 1481 1482 dr = lkpi_pcim_iomap_devres_find(pdev); 1483 if (dr == NULL) 1484 return (-ENOMEM); 1485 1486 /* Now iomap all the requested (by "mask") ones. */ 1487 for (bar = mappings = 0; mappings != mask; bar++) { 1488 if ((mask & (1 << bar)) == 0) 1489 continue; 1490 1491 /* Request double is not allowed. */ 1492 if (dr->mmio_table[bar] != NULL) { 1493 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1494 __func__, bar, dr->mmio_table[bar]); 1495 goto err; 1496 } 1497 1498 res = _lkpi_pci_iomap(pdev, bar, 0); 1499 if (res == NULL) 1500 goto err; 1501 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1502 dr->res_table[bar] = res; 1503 1504 mappings |= (1 << bar); 1505 } 1506 1507 return (0); 1508 err: 1509 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1510 if ((mappings & (1 << bar)) != 0) { 1511 res = dr->mmio_table[bar]; 1512 if (res == NULL) 1513 continue; 1514 pci_iounmap(pdev, res); 1515 } 1516 } 1517 1518 return (-EINVAL); 1519 } 1520 1521 static inline int 1522 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1523 { 1524 uint32_t requests, req_mask; 1525 int bar, error; 1526 1527 /* Request all the BARs ("regions") we do not iomap. */ 1528 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1529 for (bar = requests = 0; requests != req_mask; bar++) { 1530 if ((req_mask & (1 << bar)) == 0) 1531 continue; 1532 error = pci_request_region(pdev, bar, name); 1533 if (error != 0 && error != -ENODEV) 1534 goto err; 1535 requests |= (1 << bar); 1536 } 1537 1538 error = pcim_iomap_regions(pdev, mask, name); 1539 if (error != 0) 1540 goto err; 1541 1542 return (0); 1543 1544 err: 1545 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1546 if ((requests & (1 << bar)) != 0) 1547 pci_release_region(pdev, bar); 1548 } 1549 1550 return (-EINVAL); 1551 } 1552 1553 /* This is a FreeBSD extension so we can use bus_*(). */ 1554 static inline void 1555 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1556 { 1557 pdev->want_iomap_res = true; 1558 } 1559 1560 static inline bool 1561 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1562 { 1563 1564 return (false); 1565 } 1566 1567 static inline void * 1568 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1569 { 1570 1571 return (NULL); 1572 } 1573 1574 static inline void 1575 pci_ignore_hotplug(struct pci_dev *pdev) 1576 { 1577 } 1578 1579 static inline int 1580 pcie_get_readrq(struct pci_dev *dev) 1581 { 1582 u16 ctl; 1583 1584 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1585 return (-EINVAL); 1586 1587 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1588 } 1589 1590 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1591