1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 #include <linux/device/driver.h> 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_private.h> 49 50 #include <machine/resource.h> 51 52 #include <linux/list.h> 53 #include <linux/dmapool.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/compiler.h> 56 #include <linux/errno.h> 57 #include <asm/atomic.h> 58 #include <asm/memtype.h> 59 #include <linux/device.h> 60 #include <linux/pci_ids.h> 61 #include <linux/pm.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 74 #define MODULE_DEVICE_TABLE(_bus, _table) \ 75 \ 76 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 77 DEVMETHOD_END \ 78 }; \ 79 \ 80 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 81 "lkpi_" #_bus #_table, \ 82 _ ## _bus ## _ ## _table ## _methods, \ 83 0 \ 84 }; \ 85 \ 86 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 87 0, 0); \ 88 \ 89 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 90 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 91 92 #define PCI_ANY_ID -1U 93 94 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 95 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 96 #define PCI_FUNC(devfn) ((devfn) & 0x07) 97 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 98 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 99 100 #define PCI_VDEVICE(_vendor, _device) \ 101 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 102 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 103 #define PCI_DEVICE(_vendor, _device) \ 104 .vendor = (_vendor), .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 107 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 108 109 #define PCI_STD_NUM_BARS 6 110 #define PCI_BASE_ADDRESS_0 PCIR_BARS 111 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 112 #define PCI_VENDOR_ID PCIR_VENDOR 113 #define PCI_DEVICE_ID PCIR_DEVICE 114 #define PCI_COMMAND PCIR_COMMAND 115 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 116 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 117 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 118 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 119 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 120 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 121 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 122 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 123 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 124 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 125 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 126 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 127 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 128 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 129 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 130 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 131 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 132 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 133 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 134 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 135 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 136 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 137 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 138 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 139 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 140 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 141 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 142 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 143 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 144 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 145 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 146 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 147 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 148 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 149 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 150 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 151 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 152 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 153 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 154 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 155 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 156 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 157 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 158 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 159 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 160 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 161 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 162 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 163 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 164 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 165 #define PCI_EXP_LNKCTL2_TLS 0x000f 166 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 167 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 168 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 169 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 170 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 171 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 172 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 173 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 174 175 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 176 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 177 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 178 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 179 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 180 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 181 182 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 183 #define PCI_EXP_DEVSTA_TRPND 0x0020 184 185 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 186 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 187 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 188 189 enum pci_bus_speed { 190 PCI_SPEED_UNKNOWN = -1, 191 PCIE_SPEED_2_5GT, 192 PCIE_SPEED_5_0GT, 193 PCIE_SPEED_8_0GT, 194 PCIE_SPEED_16_0GT, 195 PCIE_SPEED_32_0GT, 196 PCIE_SPEED_64_0GT, 197 }; 198 199 enum pcie_link_width { 200 PCIE_LNK_WIDTH_RESRV = 0x00, 201 PCIE_LNK_X1 = 0x01, 202 PCIE_LNK_X2 = 0x02, 203 PCIE_LNK_X4 = 0x04, 204 PCIE_LNK_X8 = 0x08, 205 PCIE_LNK_X12 = 0x0c, 206 PCIE_LNK_X16 = 0x10, 207 PCIE_LNK_X32 = 0x20, 208 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 209 }; 210 211 #define PCIE_LINK_STATE_L0S 0x00000001 212 #define PCIE_LINK_STATE_L1 0x00000002 213 #define PCIE_LINK_STATE_CLKPM 0x00000004 214 215 typedef int pci_power_t; 216 217 #define PCI_D0 PCI_POWERSTATE_D0 218 #define PCI_D1 PCI_POWERSTATE_D1 219 #define PCI_D2 PCI_POWERSTATE_D2 220 #define PCI_D3hot PCI_POWERSTATE_D3 221 #define PCI_D3cold 4 222 223 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 224 225 extern const char *pci_power_names[6]; 226 227 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 228 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 229 230 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 231 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 232 233 #define PCI_L1SS_CTL1 0x8 234 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 235 236 #define PCI_IRQ_LEGACY 0x01 237 #define PCI_IRQ_MSI 0x02 238 #define PCI_IRQ_MSIX 0x04 239 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 240 241 struct pci_dev; 242 243 struct pci_driver { 244 struct list_head node; 245 char *name; 246 const struct pci_device_id *id_table; 247 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 248 void (*remove)(struct pci_dev *dev); 249 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 250 int (*resume) (struct pci_dev *dev); /* Device woken up */ 251 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 252 driver_t bsddriver; 253 devclass_t bsdclass; 254 struct device_driver driver; 255 const struct pci_error_handlers *err_handler; 256 bool isdrm; 257 int bsd_probe_return; 258 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 259 const nvlist_t *pf_config); 260 void (*bsd_iov_uninit)(device_t dev); 261 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 262 const nvlist_t *vf_config); 263 }; 264 265 struct pci_bus { 266 struct pci_dev *self; 267 /* struct pci_bus *parent */ 268 int domain; 269 int number; 270 }; 271 272 extern struct list_head pci_drivers; 273 extern struct list_head pci_devices; 274 extern spinlock_t pci_lock; 275 276 #define __devexit_p(x) x 277 278 #define module_pci_driver(_drv) \ 279 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver) 280 281 struct msi_msg { 282 uint32_t data; 283 }; 284 285 struct pci_msi_desc { 286 struct { 287 bool is_64; 288 } msi_attrib; 289 }; 290 291 struct msi_desc { 292 struct msi_msg msg; 293 struct pci_msi_desc pci; 294 }; 295 296 struct msix_entry { 297 int entry; 298 int vector; 299 }; 300 301 /* 302 * If we find drivers accessing this from multiple KPIs we may have to 303 * refcount objects of this structure. 304 */ 305 struct resource; 306 struct pci_mmio_region { 307 TAILQ_ENTRY(pci_mmio_region) next; 308 struct resource *res; 309 int rid; 310 int type; 311 }; 312 313 struct pci_dev { 314 struct device dev; 315 struct list_head links; 316 struct pci_driver *pdrv; 317 struct pci_bus *bus; 318 struct pci_dev *root; 319 pci_power_t current_state; 320 uint16_t device; 321 uint16_t vendor; 322 uint16_t subsystem_vendor; 323 uint16_t subsystem_device; 324 unsigned int irq; 325 unsigned int devfn; 326 uint32_t class; 327 uint8_t revision; 328 uint8_t msi_cap; 329 uint8_t msix_cap; 330 bool managed; /* devres "pcim_*(). */ 331 bool want_iomap_res; 332 bool msi_enabled; 333 bool msix_enabled; 334 phys_addr_t rom; 335 size_t romlen; 336 struct msi_desc **msi_desc; 337 char *path_name; 338 spinlock_t pcie_cap_lock; 339 340 TAILQ_HEAD(, pci_mmio_region) mmio; 341 }; 342 343 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 344 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 345 unsigned int flags); 346 bool pci_device_is_present(struct pci_dev *pdev); 347 348 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 349 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 350 void *linuxkpi_pci_iomap_range(struct pci_dev *pdev, int mmio_bar, 351 unsigned long mmio_off, unsigned long mmio_size); 352 void *linuxkpi_pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size); 353 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 354 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 355 const char *name); 356 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 357 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 358 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 359 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 360 int nreq); 361 362 /* Internal helper function(s). */ 363 struct pci_dev *lkpinew_pci_dev(device_t); 364 void lkpi_pci_devres_release(struct device *, void *); 365 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 366 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 367 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 368 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 369 370 #define pci_err(pdev, fmt, ...) \ 371 dev_err(&(pdev)->dev, fmt, __VA_ARGS__) 372 373 static inline bool 374 dev_is_pci(struct device *dev) 375 { 376 377 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 378 } 379 380 static inline uint16_t 381 pci_dev_id(struct pci_dev *pdev) 382 { 383 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 384 } 385 386 static inline int 387 pci_resource_type(struct pci_dev *pdev, int bar) 388 { 389 struct pci_map *pm; 390 391 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 392 if (!pm) 393 return (-1); 394 395 if (PCI_BAR_IO(pm->pm_value)) 396 return (SYS_RES_IOPORT); 397 else 398 return (SYS_RES_MEMORY); 399 } 400 401 /* 402 * All drivers just seem to want to inspect the type not flags. 403 */ 404 static inline int 405 pci_resource_flags(struct pci_dev *pdev, int bar) 406 { 407 int type; 408 409 type = pci_resource_type(pdev, bar); 410 if (type < 0) 411 return (0); 412 return (1 << type); 413 } 414 415 static inline const char * 416 pci_name(struct pci_dev *d) 417 { 418 return d->path_name; 419 } 420 421 static inline void * 422 pci_get_drvdata(struct pci_dev *pdev) 423 { 424 425 return dev_get_drvdata(&pdev->dev); 426 } 427 428 static inline void 429 pci_set_drvdata(struct pci_dev *pdev, void *data) 430 { 431 432 dev_set_drvdata(&pdev->dev, data); 433 } 434 435 static inline struct pci_dev * 436 pci_dev_get(struct pci_dev *pdev) 437 { 438 439 if (pdev != NULL) 440 get_device(&pdev->dev); 441 return (pdev); 442 } 443 444 static __inline void 445 pci_dev_put(struct pci_dev *pdev) 446 { 447 448 if (pdev != NULL) 449 put_device(&pdev->dev); 450 } 451 452 static inline int 453 pci_enable_device(struct pci_dev *pdev) 454 { 455 456 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 457 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 458 return (0); 459 } 460 461 static inline void 462 pci_disable_device(struct pci_dev *pdev) 463 { 464 465 pci_disable_busmaster(pdev->dev.bsddev); 466 } 467 468 static inline int 469 pci_set_master(struct pci_dev *pdev) 470 { 471 472 pci_enable_busmaster(pdev->dev.bsddev); 473 return (0); 474 } 475 476 static inline int 477 pci_set_power_state(struct pci_dev *pdev, int state) 478 { 479 480 pci_set_powerstate(pdev->dev.bsddev, state); 481 return (0); 482 } 483 484 static inline int 485 pci_clear_master(struct pci_dev *pdev) 486 { 487 488 pci_disable_busmaster(pdev->dev.bsddev); 489 return (0); 490 } 491 492 static inline bool 493 pci_is_root_bus(struct pci_bus *pbus) 494 { 495 496 return (pbus->self == NULL); 497 } 498 499 static inline struct pci_dev * 500 pci_upstream_bridge(struct pci_dev *pdev) 501 { 502 503 if (pci_is_root_bus(pdev->bus)) 504 return (NULL); 505 506 /* 507 * If we do not have a (proper) "upstream bridge" set, e.g., we point 508 * to ourselves, try to handle this case on the fly like we do 509 * for pcie_find_root_port(). 510 */ 511 if (pdev == pdev->bus->self) { 512 device_t bridge; 513 514 bridge = device_get_parent(pdev->dev.bsddev); 515 if (bridge == NULL) 516 goto done; 517 bridge = device_get_parent(bridge); 518 if (bridge == NULL) 519 goto done; 520 if (device_get_devclass(device_get_parent(bridge)) != 521 devclass_find("pci")) 522 goto done; 523 524 /* 525 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 526 * for it so it can be returned. 527 */ 528 pdev->bus->self = lkpinew_pci_dev(bridge); 529 } 530 done: 531 return (pdev->bus->self); 532 } 533 534 #define pci_release_region(pdev, bar) linuxkpi_pci_release_region(pdev, bar) 535 #define pci_release_regions(pdev) linuxkpi_pci_release_regions(pdev) 536 #define pci_request_regions(pdev, res_name) \ 537 linuxkpi_pci_request_regions(pdev, res_name) 538 539 static inline void 540 lkpi_pci_disable_msix(struct pci_dev *pdev) 541 { 542 543 pci_release_msi(pdev->dev.bsddev); 544 545 /* 546 * The MSIX IRQ numbers associated with this PCI device are no 547 * longer valid and might be re-assigned. Make sure 548 * lkpi_pci_find_irq_dev() does no longer see them by 549 * resetting their references to zero: 550 */ 551 pdev->dev.irq_start = 0; 552 pdev->dev.irq_end = 0; 553 pdev->msix_enabled = false; 554 } 555 /* Only for consistency. No conflict on that one. */ 556 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 557 558 static inline void 559 lkpi_pci_disable_msi(struct pci_dev *pdev) 560 { 561 562 pci_release_msi(pdev->dev.bsddev); 563 564 pdev->dev.irq_start = 0; 565 pdev->dev.irq_end = 0; 566 pdev->irq = pdev->dev.irq; 567 pdev->msi_enabled = false; 568 } 569 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 570 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 571 572 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 573 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 574 575 static inline bus_addr_t 576 pci_bus_address(struct pci_dev *pdev, int bar) 577 { 578 579 return (pci_resource_start(pdev, bar)); 580 } 581 582 #define PCI_CAP_ID_EXP PCIY_EXPRESS 583 #define PCI_CAP_ID_PCIX PCIY_PCIX 584 #define PCI_CAP_ID_AGP PCIY_AGP 585 #define PCI_CAP_ID_PM PCIY_PMG 586 587 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 588 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 589 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 590 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 591 #define PCI_EXP_LNKSTA PCIER_LINK_STA 592 593 static inline int 594 pci_find_capability(struct pci_dev *pdev, int capid) 595 { 596 int reg; 597 598 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 599 return (0); 600 return (reg); 601 } 602 603 static inline int pci_pcie_cap(struct pci_dev *dev) 604 { 605 return pci_find_capability(dev, PCI_CAP_ID_EXP); 606 } 607 608 static inline int 609 pci_find_ext_capability(struct pci_dev *pdev, int capid) 610 { 611 int reg; 612 613 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 614 return (0); 615 return (reg); 616 } 617 618 #define PCIM_PCAP_PME_SHIFT 11 619 static __inline bool 620 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 621 { 622 struct pci_devinfo *dinfo; 623 pcicfgregs *cfg; 624 625 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 626 return (false); 627 628 dinfo = device_get_ivars(pdev->dev.bsddev); 629 cfg = &dinfo->cfg; 630 631 if (cfg->pp.pp_cap == 0) 632 return (false); 633 634 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 635 return (true); 636 637 return (false); 638 } 639 640 static inline int 641 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 642 { 643 644 if (!pci_enable_aspm) 645 return (-EPERM); 646 647 return (-ENXIO); 648 } 649 650 static inline int 651 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 652 { 653 654 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 655 return (0); 656 } 657 658 static inline int 659 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 660 { 661 662 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 663 return (0); 664 } 665 666 static inline int 667 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 668 { 669 670 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 671 return (0); 672 } 673 674 static inline int 675 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 676 { 677 678 pci_write_config(pdev->dev.bsddev, where, val, 1); 679 return (0); 680 } 681 682 static inline int 683 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 684 { 685 686 pci_write_config(pdev->dev.bsddev, where, val, 2); 687 return (0); 688 } 689 690 static inline int 691 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 692 { 693 694 pci_write_config(pdev->dev.bsddev, where, val, 4); 695 return (0); 696 } 697 698 int linux_pci_register_driver(struct pci_driver *pdrv); 699 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 700 void linux_pci_unregister_driver(struct pci_driver *pdrv); 701 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 702 703 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 704 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 705 706 /* 707 * Enable msix, positive errors indicate actual number of available 708 * vectors. Negative errors are failures. 709 * 710 * NB: define added to prevent this definition of pci_enable_msix from 711 * clashing with the native FreeBSD version. 712 */ 713 #define pci_enable_msix(...) linuxkpi_pci_enable_msix(__VA_ARGS__) 714 715 #define pci_enable_msix_range(...) \ 716 linux_pci_enable_msix_range(__VA_ARGS__) 717 718 static inline int 719 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 720 int minvec, int maxvec) 721 { 722 int nvec = maxvec; 723 int rc; 724 725 if (maxvec < minvec) 726 return (-ERANGE); 727 728 do { 729 rc = pci_enable_msix(dev, entries, nvec); 730 if (rc < 0) { 731 return (rc); 732 } else if (rc > 0) { 733 if (rc < minvec) 734 return (-ENOSPC); 735 nvec = rc; 736 } 737 } while (rc); 738 return (nvec); 739 } 740 741 #define pci_enable_msi(pdev) \ 742 linux_pci_enable_msi(pdev) 743 744 static inline int 745 pci_enable_msi(struct pci_dev *pdev) 746 { 747 748 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 749 } 750 751 static inline int 752 pci_channel_offline(struct pci_dev *pdev) 753 { 754 755 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 756 } 757 758 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 759 { 760 return -ENODEV; 761 } 762 763 static inline void pci_disable_sriov(struct pci_dev *dev) 764 { 765 } 766 767 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \ 768 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) 769 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 770 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 771 #define pci_iounmap(pdev, res) linuxkpi_pci_iounmap(pdev, res) 772 773 static inline void 774 lkpi_pci_save_state(struct pci_dev *pdev) 775 { 776 777 pci_save_state(pdev->dev.bsddev); 778 } 779 780 static inline void 781 lkpi_pci_restore_state(struct pci_dev *pdev) 782 { 783 784 pci_restore_state(pdev->dev.bsddev); 785 } 786 787 #define pci_save_state(dev) lkpi_pci_save_state(dev) 788 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 789 790 static inline int 791 pci_reset_function(struct pci_dev *pdev) 792 { 793 794 return (-ENOSYS); 795 } 796 797 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 798 const struct pci_device_id _table[] __devinitdata 799 800 /* XXX This should not be necessary. */ 801 #define pcix_set_mmrbc(d, v) 0 802 #define pcix_get_max_mmrbc(d) 0 803 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 804 805 #define PCI_DMA_BIDIRECTIONAL 0 806 #define PCI_DMA_TODEVICE 1 807 #define PCI_DMA_FROMDEVICE 2 808 #define PCI_DMA_NONE 3 809 810 #define pci_pool dma_pool 811 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 812 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 813 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 814 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 815 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 816 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 817 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 818 _size, _vaddr, _dma_handle) 819 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 820 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 821 _sg, _nents, (enum dma_data_direction)_dir) 822 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 823 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 824 (_ptr), (_size), (enum dma_data_direction)_dir) 825 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 826 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 827 _addr, _size, (enum dma_data_direction)_dir) 828 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 829 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 830 _sg, _nents, (enum dma_data_direction)_dir) 831 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 832 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 833 _offset, _size, (enum dma_data_direction)_dir) 834 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 835 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 836 _dma_address, _size, (enum dma_data_direction)_dir) 837 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 838 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 839 dma_mapping_error(&(_pdev)->dev, _dma_addr) 840 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 841 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 842 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 843 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 844 #define pci_unmap_addr dma_unmap_addr 845 #define pci_unmap_addr_set dma_unmap_addr_set 846 #define pci_unmap_len dma_unmap_len 847 #define pci_unmap_len_set dma_unmap_len_set 848 849 typedef unsigned int __bitwise pci_channel_state_t; 850 typedef unsigned int __bitwise pci_ers_result_t; 851 852 enum pci_channel_state { 853 pci_channel_io_normal = 1, 854 pci_channel_io_frozen = 2, 855 pci_channel_io_perm_failure = 3, 856 }; 857 858 enum pci_ers_result { 859 PCI_ERS_RESULT_NONE = 1, 860 PCI_ERS_RESULT_CAN_RECOVER = 2, 861 PCI_ERS_RESULT_NEED_RESET = 3, 862 PCI_ERS_RESULT_DISCONNECT = 4, 863 PCI_ERS_RESULT_RECOVERED = 5, 864 }; 865 866 /* PCI bus error event callbacks */ 867 struct pci_error_handlers { 868 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 869 enum pci_channel_state error); 870 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 871 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 872 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 873 void (*resume)(struct pci_dev *dev); 874 }; 875 876 /* FreeBSD does not support SRIOV - yet */ 877 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 878 { 879 return dev; 880 } 881 882 static inline bool pci_is_pcie(struct pci_dev *dev) 883 { 884 return !!pci_pcie_cap(dev); 885 } 886 887 static inline u16 pcie_flags_reg(struct pci_dev *dev) 888 { 889 int pos; 890 u16 reg16; 891 892 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 893 if (!pos) 894 return 0; 895 896 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 897 898 return reg16; 899 } 900 901 static inline int pci_pcie_type(struct pci_dev *dev) 902 { 903 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 904 } 905 906 static inline int pcie_cap_version(struct pci_dev *dev) 907 { 908 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 909 } 910 911 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 912 { 913 int type = pci_pcie_type(dev); 914 915 return pcie_cap_version(dev) > 1 || 916 type == PCI_EXP_TYPE_ROOT_PORT || 917 type == PCI_EXP_TYPE_ENDPOINT || 918 type == PCI_EXP_TYPE_LEG_END; 919 } 920 921 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 922 { 923 return true; 924 } 925 926 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 927 { 928 int type = pci_pcie_type(dev); 929 930 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 931 (type == PCI_EXP_TYPE_DOWNSTREAM && 932 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 933 } 934 935 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 936 { 937 int type = pci_pcie_type(dev); 938 939 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 940 type == PCI_EXP_TYPE_RC_EC; 941 } 942 943 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 944 { 945 if (!pci_is_pcie(dev)) 946 return false; 947 948 switch (pos) { 949 case PCI_EXP_FLAGS_TYPE: 950 return true; 951 case PCI_EXP_DEVCAP: 952 case PCI_EXP_DEVCTL: 953 case PCI_EXP_DEVSTA: 954 return pcie_cap_has_devctl(dev); 955 case PCI_EXP_LNKCAP: 956 case PCI_EXP_LNKCTL: 957 case PCI_EXP_LNKSTA: 958 return pcie_cap_has_lnkctl(dev); 959 case PCI_EXP_SLTCAP: 960 case PCI_EXP_SLTCTL: 961 case PCI_EXP_SLTSTA: 962 return pcie_cap_has_sltctl(dev); 963 case PCI_EXP_RTCTL: 964 case PCI_EXP_RTCAP: 965 case PCI_EXP_RTSTA: 966 return pcie_cap_has_rtctl(dev); 967 case PCI_EXP_DEVCAP2: 968 case PCI_EXP_DEVCTL2: 969 case PCI_EXP_LNKCAP2: 970 case PCI_EXP_LNKCTL2: 971 case PCI_EXP_LNKSTA2: 972 return pcie_cap_version(dev) > 1; 973 default: 974 return false; 975 } 976 } 977 978 static inline int 979 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 980 { 981 *dst = 0; 982 if (pos & 3) 983 return -EINVAL; 984 985 if (!pcie_capability_reg_implemented(dev, pos)) 986 return -EINVAL; 987 988 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 989 } 990 991 static inline int 992 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 993 { 994 *dst = 0; 995 if (pos & 3) 996 return -EINVAL; 997 998 if (!pcie_capability_reg_implemented(dev, pos)) 999 return -EINVAL; 1000 1001 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1002 } 1003 1004 static inline int 1005 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1006 { 1007 if (pos & 1) 1008 return -EINVAL; 1009 1010 if (!pcie_capability_reg_implemented(dev, pos)) 1011 return 0; 1012 1013 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1014 } 1015 1016 static inline int 1017 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1018 uint16_t clear, uint16_t set) 1019 { 1020 int error; 1021 uint16_t v; 1022 1023 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1024 spin_lock(&dev->pcie_cap_lock); 1025 1026 error = pcie_capability_read_word(dev, pos, &v); 1027 if (error == 0) { 1028 v &= ~clear; 1029 v |= set; 1030 error = pcie_capability_write_word(dev, pos, v); 1031 } 1032 1033 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1034 spin_unlock(&dev->pcie_cap_lock); 1035 1036 return (error); 1037 } 1038 1039 static inline int 1040 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1041 { 1042 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1043 } 1044 1045 static inline int 1046 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1047 { 1048 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1049 } 1050 1051 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1052 enum pci_bus_speed *speed, enum pcie_link_width *width) 1053 { 1054 *speed = PCI_SPEED_UNKNOWN; 1055 *width = PCIE_LNK_WIDTH_UNKNOWN; 1056 return (0); 1057 } 1058 1059 static inline int 1060 pci_num_vf(struct pci_dev *dev) 1061 { 1062 return (0); 1063 } 1064 1065 static inline enum pci_bus_speed 1066 pcie_get_speed_cap(struct pci_dev *dev) 1067 { 1068 device_t root; 1069 uint32_t lnkcap, lnkcap2; 1070 int error, pos; 1071 1072 root = device_get_parent(dev->dev.bsddev); 1073 if (root == NULL) 1074 return (PCI_SPEED_UNKNOWN); 1075 root = device_get_parent(root); 1076 if (root == NULL) 1077 return (PCI_SPEED_UNKNOWN); 1078 root = device_get_parent(root); 1079 if (root == NULL) 1080 return (PCI_SPEED_UNKNOWN); 1081 1082 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1083 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1084 return (PCI_SPEED_UNKNOWN); 1085 1086 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1087 return (PCI_SPEED_UNKNOWN); 1088 1089 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1090 1091 if (lnkcap2) { /* PCIe r3.0-compliant */ 1092 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1093 return (PCIE_SPEED_2_5GT); 1094 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1095 return (PCIE_SPEED_5_0GT); 1096 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1097 return (PCIE_SPEED_8_0GT); 1098 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1099 return (PCIE_SPEED_16_0GT); 1100 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1101 return (PCIE_SPEED_32_0GT); 1102 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1103 return (PCIE_SPEED_64_0GT); 1104 } else { /* pre-r3.0 */ 1105 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1106 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1107 return (PCIE_SPEED_2_5GT); 1108 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1109 return (PCIE_SPEED_5_0GT); 1110 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1111 return (PCIE_SPEED_8_0GT); 1112 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1113 return (PCIE_SPEED_16_0GT); 1114 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1115 return (PCIE_SPEED_32_0GT); 1116 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1117 return (PCIE_SPEED_64_0GT); 1118 } 1119 return (PCI_SPEED_UNKNOWN); 1120 } 1121 1122 static inline enum pcie_link_width 1123 pcie_get_width_cap(struct pci_dev *dev) 1124 { 1125 uint32_t lnkcap; 1126 1127 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1128 if (lnkcap) 1129 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1130 1131 return (PCIE_LNK_WIDTH_UNKNOWN); 1132 } 1133 1134 static inline int 1135 pcie_get_mps(struct pci_dev *dev) 1136 { 1137 return (pci_get_max_payload(dev->dev.bsddev)); 1138 } 1139 1140 static inline uint32_t 1141 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1142 { 1143 1144 switch(spd) { 1145 case PCIE_SPEED_64_0GT: 1146 return (64000 * 128 / 130); 1147 case PCIE_SPEED_32_0GT: 1148 return (32000 * 128 / 130); 1149 case PCIE_SPEED_16_0GT: 1150 return (16000 * 128 / 130); 1151 case PCIE_SPEED_8_0GT: 1152 return (8000 * 128 / 130); 1153 case PCIE_SPEED_5_0GT: 1154 return (5000 * 8 / 10); 1155 case PCIE_SPEED_2_5GT: 1156 return (2500 * 8 / 10); 1157 default: 1158 return (0); 1159 } 1160 } 1161 1162 static inline uint32_t 1163 pcie_bandwidth_available(struct pci_dev *pdev, 1164 struct pci_dev **limiting, 1165 enum pci_bus_speed *speed, 1166 enum pcie_link_width *width) 1167 { 1168 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1169 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1170 1171 if (speed) 1172 *speed = nspeed; 1173 if (width) 1174 *width = nwidth; 1175 1176 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1177 } 1178 1179 static inline bool 1180 pcie_aspm_enabled(struct pci_dev *pdev) 1181 { 1182 return (false); 1183 } 1184 1185 static inline struct pci_dev * 1186 pcie_find_root_port(struct pci_dev *pdev) 1187 { 1188 device_t root; 1189 1190 if (pdev->root != NULL) 1191 return (pdev->root); 1192 1193 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1194 if (root == NULL) 1195 return (NULL); 1196 1197 pdev->root = lkpinew_pci_dev(root); 1198 return (pdev->root); 1199 } 1200 1201 /* This is needed when people rip out the device "HotPlug". */ 1202 static inline void 1203 pci_lock_rescan_remove(void) 1204 { 1205 } 1206 1207 static inline void 1208 pci_unlock_rescan_remove(void) 1209 { 1210 } 1211 1212 static __inline void 1213 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1214 { 1215 } 1216 1217 static inline int 1218 pci_rescan_bus(struct pci_bus *pbus) 1219 { 1220 device_t *devlist, parent; 1221 int devcount, error; 1222 1223 if (!device_is_attached(pbus->self->dev.bsddev)) 1224 return (0); 1225 /* pci_rescan_method() will work on the pcib (parent). */ 1226 error = BUS_RESCAN(pbus->self->dev.bsddev); 1227 if (error != 0) 1228 return (0); 1229 1230 parent = device_get_parent(pbus->self->dev.bsddev); 1231 error = device_get_children(parent, &devlist, &devcount); 1232 if (error != 0) 1233 return (0); 1234 if (devcount != 0) 1235 free(devlist, M_TEMP); 1236 1237 return (devcount); 1238 } 1239 1240 /* 1241 * The following functions can be used to attach/detach the LinuxKPI's 1242 * PCI device runtime. The pci_driver and pci_device_id pointer is 1243 * allowed to be NULL. Other pointers must be all valid. 1244 * The pci_dev structure should be zero-initialized before passed 1245 * to the linux_pci_attach_device function. 1246 */ 1247 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1248 const struct pci_device_id *, struct pci_dev *); 1249 extern int linux_pci_detach_device(struct pci_dev *); 1250 1251 static inline int 1252 pci_dev_present(const struct pci_device_id *cur) 1253 { 1254 while (cur != NULL && (cur->vendor || cur->device)) { 1255 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1256 return (1); 1257 } 1258 cur++; 1259 } 1260 return (0); 1261 } 1262 1263 static inline const struct pci_device_id * 1264 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 1265 { 1266 if (ids == NULL) 1267 return (NULL); 1268 1269 for (; 1270 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0; 1271 ids++) 1272 if ((ids->vendor == PCI_ANY_ID || 1273 ids->vendor == pdev->vendor) && 1274 (ids->device == PCI_ANY_ID || 1275 ids->device == pdev->device) && 1276 (ids->subvendor == PCI_ANY_ID || 1277 ids->subvendor == pdev->subsystem_vendor) && 1278 (ids->subdevice == PCI_ANY_ID || 1279 ids->subdevice == pdev->subsystem_device) && 1280 ((ids->class ^ pdev->class) & ids->class_mask) == 0) 1281 return (ids); 1282 1283 return (NULL); 1284 } 1285 1286 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1287 unsigned int bus, unsigned int devfn); 1288 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1289 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1290 1291 static inline int 1292 pci_domain_nr(struct pci_bus *pbus) 1293 { 1294 1295 return (pbus->domain); 1296 } 1297 1298 static inline int 1299 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1300 int pos, uint32_t *val, int len) 1301 { 1302 1303 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1304 return (0); 1305 } 1306 1307 static inline int 1308 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1309 { 1310 uint32_t tmp; 1311 int ret; 1312 1313 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1314 *val = (u16)tmp; 1315 return (ret); 1316 } 1317 1318 static inline int 1319 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1320 { 1321 uint32_t tmp; 1322 int ret; 1323 1324 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1325 *val = (u8)tmp; 1326 return (ret); 1327 } 1328 1329 static inline int 1330 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1331 uint32_t val, int size) 1332 { 1333 1334 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1335 return (0); 1336 } 1337 1338 static inline int 1339 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1340 uint8_t val) 1341 { 1342 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1343 } 1344 1345 static inline int 1346 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1347 uint16_t val) 1348 { 1349 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1350 } 1351 1352 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1353 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1354 1355 /* -------------------------------------------------------------------------- */ 1356 1357 #define pcim_enable_device(pdev) linuxkpi_pcim_enable_device(pdev) 1358 #define pcim_iomap_table(pdev) linuxkpi_pcim_iomap_table(pdev) 1359 #define pcim_iomap_regions(pdev, mask, name) \ 1360 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1361 1362 static inline int 1363 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1364 { 1365 uint32_t requests, req_mask; 1366 int bar, error; 1367 1368 /* Request all the BARs ("regions") we do not iomap. */ 1369 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1370 for (bar = requests = 0; requests != req_mask; bar++) { 1371 if ((req_mask & (1 << bar)) == 0) 1372 continue; 1373 error = pci_request_region(pdev, bar, name); 1374 if (error != 0 && error != -ENODEV) 1375 goto err; 1376 requests |= (1 << bar); 1377 } 1378 1379 error = pcim_iomap_regions(pdev, mask, name); 1380 if (error != 0) 1381 goto err; 1382 1383 return (0); 1384 1385 err: 1386 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1387 if ((requests & (1 << bar)) != 0) 1388 pci_release_region(pdev, bar); 1389 } 1390 1391 return (-EINVAL); 1392 } 1393 1394 /* 1395 * We cannot simply re-define pci_get_device() as we would normally do 1396 * and then hide it in linux_pci.c as too many semi-native drivers still 1397 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1398 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1399 */ 1400 static inline struct pci_dev * 1401 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1402 { 1403 1404 return (lkpi_pci_get_device(vendor, device, odev)); 1405 } 1406 1407 /* This is a FreeBSD extension so we can use bus_*(). */ 1408 static inline void 1409 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1410 { 1411 pdev->want_iomap_res = true; 1412 } 1413 1414 static inline bool 1415 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1416 { 1417 1418 return (false); 1419 } 1420 1421 static inline void * 1422 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1423 { 1424 1425 return (NULL); 1426 } 1427 1428 static inline void 1429 pci_ignore_hotplug(struct pci_dev *pdev) 1430 { 1431 } 1432 1433 static inline const char * 1434 pci_power_name(pci_power_t state) 1435 { 1436 int pstate = state + 1; 1437 1438 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1439 return (pci_power_names[pstate]); 1440 else 1441 return (pci_power_names[0]); 1442 } 1443 1444 static inline int 1445 pcie_get_readrq(struct pci_dev *dev) 1446 { 1447 u16 ctl; 1448 1449 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1450 return (-EINVAL); 1451 1452 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1453 } 1454 1455 static inline bool 1456 pci_is_enabled(struct pci_dev *pdev) 1457 { 1458 1459 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1460 PCIM_CMD_BUSMASTEREN) != 0); 1461 } 1462 1463 static inline int 1464 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1465 { 1466 1467 return (0); 1468 } 1469 1470 static inline int 1471 pci_assign_resource(struct pci_dev *pdev, int bar) 1472 { 1473 1474 return (0); 1475 } 1476 1477 static inline int 1478 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1479 { 1480 1481 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1482 if (vector != 0) 1483 return (-EINVAL); 1484 return (pdev->irq); 1485 } 1486 1487 if (pdev->msix_enabled || pdev->msi_enabled) { 1488 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1489 return (-EINVAL); 1490 return (pdev->dev.irq_start + vector); 1491 } 1492 1493 return (-ENXIO); 1494 } 1495 1496 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1497