1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/pciio.h> 41 #include <sys/rman.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pci_private.h> 45 46 #include <machine/resource.h> 47 48 #include <linux/list.h> 49 #include <linux/dmapool.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/compiler.h> 52 #include <linux/errno.h> 53 #include <asm/atomic.h> 54 #include <linux/device.h> 55 56 struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class; 62 uint32_t class_mask; 63 uintptr_t driver_data; 64 }; 65 66 #define MODULE_DEVICE_TABLE(bus, table) 67 68 #define PCI_BASE_CLASS_DISPLAY 0x03 69 #define PCI_CLASS_DISPLAY_VGA 0x0300 70 #define PCI_CLASS_DISPLAY_OTHER 0x0380 71 #define PCI_BASE_CLASS_BRIDGE 0x06 72 #define PCI_CLASS_BRIDGE_ISA 0x0601 73 74 #define PCI_ANY_ID -1U 75 #define PCI_VENDOR_ID_APPLE 0x106b 76 #define PCI_VENDOR_ID_ASUSTEK 0x1043 77 #define PCI_VENDOR_ID_ATI 0x1002 78 #define PCI_VENDOR_ID_DELL 0x1028 79 #define PCI_VENDOR_ID_HP 0x103c 80 #define PCI_VENDOR_ID_IBM 0x1014 81 #define PCI_VENDOR_ID_INTEL 0x8086 82 #define PCI_VENDOR_ID_MELLANOX 0x15b3 83 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 84 #define PCI_VENDOR_ID_SERVERWORKS 0x1166 85 #define PCI_VENDOR_ID_SONY 0x104d 86 #define PCI_VENDOR_ID_TOPSPIN 0x1867 87 #define PCI_VENDOR_ID_VIA 0x1106 88 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 89 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 90 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 91 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 92 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 93 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 94 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 95 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 96 #define PCI_SUBDEVICE_ID_QEMU 0x1100 97 98 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 99 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 100 #define PCI_FUNC(devfn) ((devfn) & 0x07) 101 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 102 103 #define PCI_VDEVICE(_vendor, _device) \ 104 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 #define PCI_DEVICE(_vendor, _device) \ 107 .vendor = (_vendor), .device = (_device), \ 108 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 109 110 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 111 112 #define PCI_VENDOR_ID PCIR_DEVVENDOR 113 #define PCI_COMMAND PCIR_COMMAND 114 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 115 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 116 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 117 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 118 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 119 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 120 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 121 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 122 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 123 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 124 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 125 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 126 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 127 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 128 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 129 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 130 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 131 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 132 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 133 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 134 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 135 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 136 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 137 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 138 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 139 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 140 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 141 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 142 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 143 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 144 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 145 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 146 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 147 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 148 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 149 150 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 151 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 152 #define PCI_EXP_DEVSTA_TRPND 0x0020 153 154 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 155 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 156 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 157 158 enum pci_bus_speed { 159 PCI_SPEED_UNKNOWN = -1, 160 PCIE_SPEED_2_5GT, 161 PCIE_SPEED_5_0GT, 162 PCIE_SPEED_8_0GT, 163 PCIE_SPEED_16_0GT, 164 }; 165 166 enum pcie_link_width { 167 PCIE_LNK_WIDTH_RESRV = 0x00, 168 PCIE_LNK_X1 = 0x01, 169 PCIE_LNK_X2 = 0x02, 170 PCIE_LNK_X4 = 0x04, 171 PCIE_LNK_X8 = 0x08, 172 PCIE_LNK_X12 = 0x0c, 173 PCIE_LNK_X16 = 0x10, 174 PCIE_LNK_X32 = 0x20, 175 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 176 }; 177 178 typedef int pci_power_t; 179 180 #define PCI_D0 PCI_POWERSTATE_D0 181 #define PCI_D1 PCI_POWERSTATE_D1 182 #define PCI_D2 PCI_POWERSTATE_D2 183 #define PCI_D3hot PCI_POWERSTATE_D3 184 #define PCI_D3cold 4 185 186 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 187 188 struct pci_dev; 189 190 struct pci_driver { 191 struct list_head links; 192 char *name; 193 const struct pci_device_id *id_table; 194 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 195 void (*remove)(struct pci_dev *dev); 196 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 197 int (*resume) (struct pci_dev *dev); /* Device woken up */ 198 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 199 driver_t bsddriver; 200 devclass_t bsdclass; 201 struct device_driver driver; 202 const struct pci_error_handlers *err_handler; 203 bool isdrm; 204 }; 205 206 struct pci_bus { 207 struct pci_dev *self; 208 int number; 209 }; 210 211 extern struct list_head pci_drivers; 212 extern struct list_head pci_devices; 213 extern spinlock_t pci_lock; 214 215 #define __devexit_p(x) x 216 217 struct pci_dev { 218 struct device dev; 219 struct list_head links; 220 struct pci_driver *pdrv; 221 struct pci_bus *bus; 222 uint64_t dma_mask; 223 uint16_t device; 224 uint16_t vendor; 225 uint16_t subsystem_vendor; 226 uint16_t subsystem_device; 227 unsigned int irq; 228 unsigned int devfn; 229 uint32_t class; 230 uint8_t revision; 231 }; 232 233 static inline struct resource_list_entry * 234 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 235 { 236 struct pci_devinfo *dinfo; 237 struct resource_list *rl; 238 239 dinfo = device_get_ivars(pdev->dev.bsddev); 240 rl = &dinfo->resources; 241 return resource_list_find(rl, type, rid); 242 } 243 244 static inline struct resource_list_entry * 245 linux_pci_get_bar(struct pci_dev *pdev, int bar) 246 { 247 struct resource_list_entry *rle; 248 249 bar = PCIR_BAR(bar); 250 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 251 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 252 return (rle); 253 } 254 255 static inline struct device * 256 linux_pci_find_irq_dev(unsigned int irq) 257 { 258 struct pci_dev *pdev; 259 struct device *found; 260 261 found = NULL; 262 spin_lock(&pci_lock); 263 list_for_each_entry(pdev, &pci_devices, links) { 264 if (irq == pdev->dev.irq || 265 (irq >= pdev->dev.msix && irq < pdev->dev.msix_max)) { 266 found = &pdev->dev; 267 break; 268 } 269 } 270 spin_unlock(&pci_lock); 271 return (found); 272 } 273 274 static inline unsigned long 275 pci_resource_start(struct pci_dev *pdev, int bar) 276 { 277 struct resource_list_entry *rle; 278 279 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 280 return (0); 281 return rle->start; 282 } 283 284 static inline unsigned long 285 pci_resource_len(struct pci_dev *pdev, int bar) 286 { 287 struct resource_list_entry *rle; 288 289 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 290 return (0); 291 return rle->count; 292 } 293 294 static inline int 295 pci_resource_type(struct pci_dev *pdev, int bar) 296 { 297 struct pci_map *pm; 298 299 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 300 if (!pm) 301 return (-1); 302 303 if (PCI_BAR_IO(pm->pm_value)) 304 return (SYS_RES_IOPORT); 305 else 306 return (SYS_RES_MEMORY); 307 } 308 309 /* 310 * All drivers just seem to want to inspect the type not flags. 311 */ 312 static inline int 313 pci_resource_flags(struct pci_dev *pdev, int bar) 314 { 315 int type; 316 317 type = pci_resource_type(pdev, bar); 318 if (type < 0) 319 return (0); 320 return (1 << type); 321 } 322 323 static inline const char * 324 pci_name(struct pci_dev *d) 325 { 326 327 return device_get_desc(d->dev.bsddev); 328 } 329 330 static inline void * 331 pci_get_drvdata(struct pci_dev *pdev) 332 { 333 334 return dev_get_drvdata(&pdev->dev); 335 } 336 337 static inline void 338 pci_set_drvdata(struct pci_dev *pdev, void *data) 339 { 340 341 dev_set_drvdata(&pdev->dev, data); 342 } 343 344 static inline int 345 pci_enable_device(struct pci_dev *pdev) 346 { 347 348 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 349 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 350 return (0); 351 } 352 353 static inline void 354 pci_disable_device(struct pci_dev *pdev) 355 { 356 357 pci_disable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 358 pci_disable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 359 pci_disable_busmaster(pdev->dev.bsddev); 360 } 361 362 static inline int 363 pci_set_master(struct pci_dev *pdev) 364 { 365 366 pci_enable_busmaster(pdev->dev.bsddev); 367 return (0); 368 } 369 370 static inline int 371 pci_set_power_state(struct pci_dev *pdev, int state) 372 { 373 374 pci_set_powerstate(pdev->dev.bsddev, state); 375 return (0); 376 } 377 378 static inline int 379 pci_clear_master(struct pci_dev *pdev) 380 { 381 382 pci_disable_busmaster(pdev->dev.bsddev); 383 return (0); 384 } 385 386 static inline int 387 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 388 { 389 int rid; 390 int type; 391 392 type = pci_resource_type(pdev, bar); 393 if (type < 0) 394 return (-ENODEV); 395 rid = PCIR_BAR(bar); 396 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 397 RF_ACTIVE) == NULL) 398 return (-EINVAL); 399 return (0); 400 } 401 402 static inline void 403 pci_release_region(struct pci_dev *pdev, int bar) 404 { 405 struct resource_list_entry *rle; 406 407 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 408 return; 409 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 410 } 411 412 static inline void 413 pci_release_regions(struct pci_dev *pdev) 414 { 415 int i; 416 417 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 418 pci_release_region(pdev, i); 419 } 420 421 static inline int 422 pci_request_regions(struct pci_dev *pdev, const char *res_name) 423 { 424 int error; 425 int i; 426 427 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 428 error = pci_request_region(pdev, i, res_name); 429 if (error && error != -ENODEV) { 430 pci_release_regions(pdev); 431 return (error); 432 } 433 } 434 return (0); 435 } 436 437 static inline void 438 pci_disable_msix(struct pci_dev *pdev) 439 { 440 441 pci_release_msi(pdev->dev.bsddev); 442 443 /* 444 * The MSIX IRQ numbers associated with this PCI device are no 445 * longer valid and might be re-assigned. Make sure 446 * linux_pci_find_irq_dev() does no longer see them by 447 * resetting their references to zero: 448 */ 449 pdev->dev.msix = 0; 450 pdev->dev.msix_max = 0; 451 } 452 453 static inline bus_addr_t 454 pci_bus_address(struct pci_dev *pdev, int bar) 455 { 456 457 return (pci_resource_start(pdev, bar)); 458 } 459 460 #define PCI_CAP_ID_EXP PCIY_EXPRESS 461 #define PCI_CAP_ID_PCIX PCIY_PCIX 462 #define PCI_CAP_ID_AGP PCIY_AGP 463 #define PCI_CAP_ID_PM PCIY_PMG 464 465 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 466 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 467 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 468 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 469 #define PCI_EXP_LNKSTA PCIER_LINK_STA 470 471 static inline int 472 pci_find_capability(struct pci_dev *pdev, int capid) 473 { 474 int reg; 475 476 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 477 return (0); 478 return (reg); 479 } 480 481 static inline int pci_pcie_cap(struct pci_dev *dev) 482 { 483 return pci_find_capability(dev, PCI_CAP_ID_EXP); 484 } 485 486 487 static inline int 488 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 489 { 490 491 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 492 return (0); 493 } 494 495 static inline int 496 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 497 { 498 499 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 500 return (0); 501 } 502 503 static inline int 504 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 505 { 506 507 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 508 return (0); 509 } 510 511 static inline int 512 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 513 { 514 515 pci_write_config(pdev->dev.bsddev, where, val, 1); 516 return (0); 517 } 518 519 static inline int 520 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 521 { 522 523 pci_write_config(pdev->dev.bsddev, where, val, 2); 524 return (0); 525 } 526 527 static inline int 528 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 529 { 530 531 pci_write_config(pdev->dev.bsddev, where, val, 4); 532 return (0); 533 } 534 535 int linux_pci_register_driver(struct pci_driver *pdrv); 536 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 537 void linux_pci_unregister_driver(struct pci_driver *pdrv); 538 539 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 540 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 541 542 struct msix_entry { 543 int entry; 544 int vector; 545 }; 546 547 /* 548 * Enable msix, positive errors indicate actual number of available 549 * vectors. Negative errors are failures. 550 * 551 * NB: define added to prevent this definition of pci_enable_msix from 552 * clashing with the native FreeBSD version. 553 */ 554 #define pci_enable_msix(...) \ 555 linux_pci_enable_msix(__VA_ARGS__) 556 557 static inline int 558 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 559 { 560 struct resource_list_entry *rle; 561 int error; 562 int avail; 563 int i; 564 565 avail = pci_msix_count(pdev->dev.bsddev); 566 if (avail < nreq) { 567 if (avail == 0) 568 return -EINVAL; 569 return avail; 570 } 571 avail = nreq; 572 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 573 return error; 574 /* 575 * Handle case where "pci_alloc_msix()" may allocate less 576 * interrupts than available and return with no error: 577 */ 578 if (avail < nreq) { 579 pci_release_msi(pdev->dev.bsddev); 580 return avail; 581 } 582 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 583 pdev->dev.msix = rle->start; 584 pdev->dev.msix_max = rle->start + avail; 585 for (i = 0; i < nreq; i++) 586 entries[i].vector = pdev->dev.msix + i; 587 return (0); 588 } 589 590 #define pci_enable_msix_range(...) \ 591 linux_pci_enable_msix_range(__VA_ARGS__) 592 593 static inline int 594 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 595 int minvec, int maxvec) 596 { 597 int nvec = maxvec; 598 int rc; 599 600 if (maxvec < minvec) 601 return (-ERANGE); 602 603 do { 604 rc = pci_enable_msix(dev, entries, nvec); 605 if (rc < 0) { 606 return (rc); 607 } else if (rc > 0) { 608 if (rc < minvec) 609 return (-ENOSPC); 610 nvec = rc; 611 } 612 } while (rc); 613 return (nvec); 614 } 615 616 static inline int 617 pci_channel_offline(struct pci_dev *pdev) 618 { 619 620 return (pci_get_vendor(pdev->dev.bsddev) == 0xffff); 621 } 622 623 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 624 { 625 return -ENODEV; 626 } 627 static inline void pci_disable_sriov(struct pci_dev *dev) 628 { 629 } 630 631 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 632 const struct pci_device_id _table[] __devinitdata 633 634 635 /* XXX This should not be necessary. */ 636 #define pcix_set_mmrbc(d, v) 0 637 #define pcix_get_max_mmrbc(d) 0 638 #define pcie_set_readrq(d, v) 0 639 640 #define PCI_DMA_BIDIRECTIONAL 0 641 #define PCI_DMA_TODEVICE 1 642 #define PCI_DMA_FROMDEVICE 2 643 #define PCI_DMA_NONE 3 644 645 #define pci_pool dma_pool 646 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 647 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 648 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 649 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 650 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 651 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 652 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 653 _size, _vaddr, _dma_handle) 654 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 655 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 656 _sg, _nents, (enum dma_data_direction)_dir) 657 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 658 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 659 (_ptr), (_size), (enum dma_data_direction)_dir) 660 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 661 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 662 _addr, _size, (enum dma_data_direction)_dir) 663 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 664 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 665 _sg, _nents, (enum dma_data_direction)_dir) 666 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 667 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 668 _offset, _size, (enum dma_data_direction)_dir) 669 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 670 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 671 _dma_address, _size, (enum dma_data_direction)_dir) 672 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 673 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 674 dma_mapping_error(&(_pdev)->dev, _dma_addr) 675 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 676 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 677 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 678 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 679 #define pci_unmap_addr dma_unmap_addr 680 #define pci_unmap_addr_set dma_unmap_addr_set 681 #define pci_unmap_len dma_unmap_len 682 #define pci_unmap_len_set dma_unmap_len_set 683 684 typedef unsigned int __bitwise pci_channel_state_t; 685 typedef unsigned int __bitwise pci_ers_result_t; 686 687 enum pci_channel_state { 688 pci_channel_io_normal = 1, 689 pci_channel_io_frozen = 2, 690 pci_channel_io_perm_failure = 3, 691 }; 692 693 enum pci_ers_result { 694 PCI_ERS_RESULT_NONE = 1, 695 PCI_ERS_RESULT_CAN_RECOVER = 2, 696 PCI_ERS_RESULT_NEED_RESET = 3, 697 PCI_ERS_RESULT_DISCONNECT = 4, 698 PCI_ERS_RESULT_RECOVERED = 5, 699 }; 700 701 702 /* PCI bus error event callbacks */ 703 struct pci_error_handlers { 704 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 705 enum pci_channel_state error); 706 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 707 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 708 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 709 void (*resume)(struct pci_dev *dev); 710 }; 711 712 /* FreeBSD does not support SRIOV - yet */ 713 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 714 { 715 return dev; 716 } 717 718 static inline bool pci_is_pcie(struct pci_dev *dev) 719 { 720 return !!pci_pcie_cap(dev); 721 } 722 723 static inline u16 pcie_flags_reg(struct pci_dev *dev) 724 { 725 int pos; 726 u16 reg16; 727 728 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 729 if (!pos) 730 return 0; 731 732 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 733 734 return reg16; 735 } 736 737 738 static inline int pci_pcie_type(struct pci_dev *dev) 739 { 740 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 741 } 742 743 static inline int pcie_cap_version(struct pci_dev *dev) 744 { 745 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 746 } 747 748 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 749 { 750 int type = pci_pcie_type(dev); 751 752 return pcie_cap_version(dev) > 1 || 753 type == PCI_EXP_TYPE_ROOT_PORT || 754 type == PCI_EXP_TYPE_ENDPOINT || 755 type == PCI_EXP_TYPE_LEG_END; 756 } 757 758 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 759 { 760 return true; 761 } 762 763 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 764 { 765 int type = pci_pcie_type(dev); 766 767 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 768 (type == PCI_EXP_TYPE_DOWNSTREAM && 769 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 770 } 771 772 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 773 { 774 int type = pci_pcie_type(dev); 775 776 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 777 type == PCI_EXP_TYPE_RC_EC; 778 } 779 780 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 781 { 782 if (!pci_is_pcie(dev)) 783 return false; 784 785 switch (pos) { 786 case PCI_EXP_FLAGS_TYPE: 787 return true; 788 case PCI_EXP_DEVCAP: 789 case PCI_EXP_DEVCTL: 790 case PCI_EXP_DEVSTA: 791 return pcie_cap_has_devctl(dev); 792 case PCI_EXP_LNKCAP: 793 case PCI_EXP_LNKCTL: 794 case PCI_EXP_LNKSTA: 795 return pcie_cap_has_lnkctl(dev); 796 case PCI_EXP_SLTCAP: 797 case PCI_EXP_SLTCTL: 798 case PCI_EXP_SLTSTA: 799 return pcie_cap_has_sltctl(dev); 800 case PCI_EXP_RTCTL: 801 case PCI_EXP_RTCAP: 802 case PCI_EXP_RTSTA: 803 return pcie_cap_has_rtctl(dev); 804 case PCI_EXP_DEVCAP2: 805 case PCI_EXP_DEVCTL2: 806 case PCI_EXP_LNKCAP2: 807 case PCI_EXP_LNKCTL2: 808 case PCI_EXP_LNKSTA2: 809 return pcie_cap_version(dev) > 1; 810 default: 811 return false; 812 } 813 } 814 815 static inline int 816 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 817 { 818 if (pos & 3) 819 return -EINVAL; 820 821 if (!pcie_capability_reg_implemented(dev, pos)) 822 return -EINVAL; 823 824 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 825 } 826 827 static inline int 828 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 829 { 830 if (pos & 3) 831 return -EINVAL; 832 833 if (!pcie_capability_reg_implemented(dev, pos)) 834 return -EINVAL; 835 836 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 837 } 838 839 static inline int 840 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 841 { 842 if (pos & 1) 843 return -EINVAL; 844 845 if (!pcie_capability_reg_implemented(dev, pos)) 846 return 0; 847 848 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 849 } 850 851 static inline int pcie_get_minimum_link(struct pci_dev *dev, 852 enum pci_bus_speed *speed, enum pcie_link_width *width) 853 { 854 *speed = PCI_SPEED_UNKNOWN; 855 *width = PCIE_LNK_WIDTH_UNKNOWN; 856 return (0); 857 } 858 859 static inline int 860 pci_num_vf(struct pci_dev *dev) 861 { 862 return (0); 863 } 864 865 static inline enum pci_bus_speed 866 pcie_get_speed_cap(struct pci_dev *dev) 867 { 868 device_t root; 869 uint32_t lnkcap, lnkcap2; 870 int error, pos; 871 872 root = device_get_parent(dev->dev.bsddev); 873 if (root == NULL) 874 return (PCI_SPEED_UNKNOWN); 875 root = device_get_parent(root); 876 if (root == NULL) 877 return (PCI_SPEED_UNKNOWN); 878 root = device_get_parent(root); 879 if (root == NULL) 880 return (PCI_SPEED_UNKNOWN); 881 882 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 883 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 884 return (PCI_SPEED_UNKNOWN); 885 886 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 887 return (PCI_SPEED_UNKNOWN); 888 889 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 890 891 if (lnkcap2) { /* PCIe r3.0-compliant */ 892 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 893 return (PCIE_SPEED_2_5GT); 894 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 895 return (PCIE_SPEED_5_0GT); 896 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 897 return (PCIE_SPEED_8_0GT); 898 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 899 return (PCIE_SPEED_16_0GT); 900 } else { /* pre-r3.0 */ 901 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 902 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 903 return (PCIE_SPEED_2_5GT); 904 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 905 return (PCIE_SPEED_5_0GT); 906 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 907 return (PCIE_SPEED_8_0GT); 908 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 909 return (PCIE_SPEED_16_0GT); 910 } 911 return (PCI_SPEED_UNKNOWN); 912 } 913 914 static inline enum pcie_link_width 915 pcie_get_width_cap(struct pci_dev *dev) 916 { 917 uint32_t lnkcap; 918 919 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 920 if (lnkcap) 921 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 922 923 return (PCIE_LNK_WIDTH_UNKNOWN); 924 } 925 926 #endif /* _LINUX_PCI_H_ */ 927