1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 #include <linux/device/driver.h> 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_private.h> 49 50 #include <machine/resource.h> 51 52 #include <linux/list.h> 53 #include <linux/dmapool.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/compiler.h> 56 #include <linux/errno.h> 57 #include <asm/atomic.h> 58 #include <asm/memtype.h> 59 #include <linux/device.h> 60 #include <linux/pci_ids.h> 61 #include <linux/pm.h> 62 63 #include <linux/kernel.h> /* pr_debug */ 64 65 struct pci_device_id { 66 uint32_t vendor; 67 uint32_t device; 68 uint32_t subvendor; 69 uint32_t subdevice; 70 uint32_t class; 71 uint32_t class_mask; 72 uintptr_t driver_data; 73 }; 74 75 #define MODULE_DEVICE_TABLE_BUS_pci(_bus, _table) \ 76 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 77 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 78 79 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 80 #define MODULE_DEVICE_TABLE(_bus, _table) \ 81 \ 82 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 83 DEVMETHOD_END \ 84 }; \ 85 \ 86 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 87 "lkpi_" #_bus #_table, \ 88 _ ## _bus ## _ ## _table ## _methods, \ 89 0 \ 90 }; \ 91 \ 92 DRIVER_MODULE(lkpi_ ## _table, _bus, _ ## _bus ## _ ## _table ## _driver,\ 93 0, 0); \ 94 \ 95 MODULE_DEVICE_TABLE_BUS_ ## _bus(_bus, _table) 96 97 #define PCI_ANY_ID -1U 98 99 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 100 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 101 #define PCI_FUNC(devfn) ((devfn) & 0x07) 102 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 103 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 104 105 #define PCI_VDEVICE(_vendor, _device) \ 106 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 108 #define PCI_DEVICE(_vendor, _device) \ 109 .vendor = (_vendor), .device = (_device), \ 110 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 111 112 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 113 114 #define PCI_STD_NUM_BARS 6 115 #define PCI_BASE_ADDRESS_0 PCIR_BARS 116 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 117 #define PCI_VENDOR_ID PCIR_VENDOR 118 #define PCI_DEVICE_ID PCIR_DEVICE 119 #define PCI_COMMAND PCIR_COMMAND 120 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 121 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 122 #define PCI_PRIMARY_BUS PCIR_PRIBUS_1 123 #define PCI_SECONDARY_BUS PCIR_SECBUS_1 124 #define PCI_SUBORDINATE_BUS PCIR_SUBBUS_1 125 #define PCI_SEC_LATENCY_TIMER PCIR_SECLAT_1 126 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 127 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 128 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 129 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 130 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 131 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 132 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 133 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 134 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 135 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 136 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 137 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 138 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 139 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 140 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 141 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 142 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 143 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 144 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 145 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 146 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 147 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 148 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 149 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 150 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 151 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 152 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 153 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 154 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 155 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 156 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 157 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 158 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 159 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 160 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 161 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 162 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 163 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 164 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 165 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 166 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 167 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 168 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 169 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 170 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 171 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 172 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 173 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 174 #define PCI_EXP_LNKCTL2_TLS 0x000f 175 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 176 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 177 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 178 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 179 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 180 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 181 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 182 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 183 184 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 185 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 186 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 187 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 188 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 189 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 190 191 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 192 #define PCI_EXP_DEVSTA_TRPND 0x0020 193 194 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 195 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 196 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 197 198 enum pci_bus_speed { 199 PCI_SPEED_UNKNOWN = -1, 200 PCIE_SPEED_2_5GT, 201 PCIE_SPEED_5_0GT, 202 PCIE_SPEED_8_0GT, 203 PCIE_SPEED_16_0GT, 204 PCIE_SPEED_32_0GT, 205 PCIE_SPEED_64_0GT, 206 }; 207 208 enum pcie_link_width { 209 PCIE_LNK_WIDTH_RESRV = 0x00, 210 PCIE_LNK_X1 = 0x01, 211 PCIE_LNK_X2 = 0x02, 212 PCIE_LNK_X4 = 0x04, 213 PCIE_LNK_X8 = 0x08, 214 PCIE_LNK_X12 = 0x0c, 215 PCIE_LNK_X16 = 0x10, 216 PCIE_LNK_X32 = 0x20, 217 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 218 }; 219 220 #define PCIE_LINK_STATE_L0S 0x00000001 221 #define PCIE_LINK_STATE_L1 0x00000002 222 #define PCIE_LINK_STATE_CLKPM 0x00000004 223 224 typedef int pci_power_t; 225 226 #define PCI_D0 PCI_POWERSTATE_D0 227 #define PCI_D1 PCI_POWERSTATE_D1 228 #define PCI_D2 PCI_POWERSTATE_D2 229 #define PCI_D3hot PCI_POWERSTATE_D3 230 #define PCI_D3cold 4 231 232 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 233 234 extern const char *pci_power_names[6]; 235 236 #define PCI_ERR_UNCOR_STATUS PCIR_AER_UC_STATUS 237 #define PCI_ERR_COR_STATUS PCIR_AER_COR_STATUS 238 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 239 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 240 241 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 242 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 243 244 #define PCI_L1SS_CTL1 0x8 245 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 246 247 #define PCI_IRQ_INTX 0x01 248 #define PCI_IRQ_MSI 0x02 249 #define PCI_IRQ_MSIX 0x04 250 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_INTX) 251 252 #if defined(LINUXKPI_VERSION) && (LINUXKPI_VERSION <= 61000) 253 #define PCI_IRQ_LEGACY PCI_IRQ_INTX 254 #endif 255 256 struct pci_dev; 257 258 struct pci_driver { 259 struct list_head node; 260 char *name; 261 const struct pci_device_id *id_table; 262 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 263 void (*remove)(struct pci_dev *dev); 264 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 265 int (*resume) (struct pci_dev *dev); /* Device woken up */ 266 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 267 driver_t bsddriver; 268 devclass_t bsdclass; 269 struct device_driver driver; 270 const struct pci_error_handlers *err_handler; 271 bool isdrm; 272 int bsd_probe_return; 273 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 274 const nvlist_t *pf_config); 275 void (*bsd_iov_uninit)(device_t dev); 276 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 277 const nvlist_t *vf_config); 278 }; 279 280 struct pci_bus { 281 struct pci_dev *self; 282 /* struct pci_bus *parent */ 283 int domain; 284 int number; 285 }; 286 287 extern struct list_head pci_drivers; 288 extern struct list_head pci_devices; 289 extern spinlock_t pci_lock; 290 291 #define __devexit_p(x) x 292 293 #define module_pci_driver(_drv) \ 294 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver) 295 296 struct msi_msg { 297 uint32_t data; 298 }; 299 300 struct pci_msi_desc { 301 struct { 302 bool is_64; 303 } msi_attrib; 304 }; 305 306 struct msi_desc { 307 struct msi_msg msg; 308 struct pci_msi_desc pci; 309 }; 310 311 struct msix_entry { 312 int entry; 313 int vector; 314 }; 315 316 /* 317 * If we find drivers accessing this from multiple KPIs we may have to 318 * refcount objects of this structure. 319 */ 320 struct resource; 321 struct pci_mmio_region { 322 TAILQ_ENTRY(pci_mmio_region) next; 323 struct resource *res; 324 int rid; 325 int type; 326 }; 327 328 struct pci_dev { 329 struct device dev; 330 struct list_head links; 331 struct pci_driver *pdrv; 332 struct pci_bus *bus; 333 struct pci_dev *root; 334 pci_power_t current_state; 335 uint16_t device; 336 uint16_t vendor; 337 uint16_t subsystem_vendor; 338 uint16_t subsystem_device; 339 unsigned int irq; 340 unsigned int devfn; 341 uint32_t class; 342 uint8_t revision; 343 uint8_t msi_cap; 344 uint8_t msix_cap; 345 bool managed; /* devres "pcim_*(). */ 346 bool want_iomap_res; 347 bool msi_enabled; 348 bool msix_enabled; 349 phys_addr_t rom; 350 size_t romlen; 351 struct msi_desc **msi_desc; 352 char *path_name; 353 spinlock_t pcie_cap_lock; 354 355 TAILQ_HEAD(, pci_mmio_region) mmio; 356 }; 357 358 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 359 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 360 unsigned int flags); 361 bool pci_device_is_present(struct pci_dev *pdev); 362 363 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 364 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 365 void *linuxkpi_pci_iomap_range(struct pci_dev *pdev, int mmio_bar, 366 unsigned long mmio_off, unsigned long mmio_size); 367 void *linuxkpi_pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size); 368 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 369 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 370 const char *name); 371 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 372 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 373 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 374 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 375 int nreq); 376 377 /* Internal helper function(s). */ 378 struct pci_dev *lkpinew_pci_dev(device_t); 379 void lkpi_pci_devres_release(struct device *, void *); 380 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 381 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 382 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 383 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 384 385 #define pci_err(pdev, fmt, ...) \ 386 dev_err(&(pdev)->dev, fmt, ##__VA_ARGS__) 387 #define pci_info(pdev, fmt, ...) \ 388 dev_info(&(pdev)->dev, fmt, ##__VA_ARGS__) 389 390 static inline bool 391 dev_is_pci(struct device *dev) 392 { 393 394 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 395 } 396 397 static inline uint16_t 398 pci_dev_id(struct pci_dev *pdev) 399 { 400 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 401 } 402 403 static inline int 404 pci_resource_type(struct pci_dev *pdev, int bar) 405 { 406 struct pci_map *pm; 407 408 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 409 if (!pm) 410 return (-1); 411 412 if (PCI_BAR_IO(pm->pm_value)) 413 return (SYS_RES_IOPORT); 414 else 415 return (SYS_RES_MEMORY); 416 } 417 418 /* 419 * All drivers just seem to want to inspect the type not flags. 420 */ 421 static inline int 422 pci_resource_flags(struct pci_dev *pdev, int bar) 423 { 424 int type; 425 426 type = pci_resource_type(pdev, bar); 427 if (type < 0) 428 return (0); 429 return (1 << type); 430 } 431 432 static inline const char * 433 pci_name(struct pci_dev *d) 434 { 435 return d->path_name; 436 } 437 438 static inline void * 439 pci_get_drvdata(struct pci_dev *pdev) 440 { 441 442 return dev_get_drvdata(&pdev->dev); 443 } 444 445 static inline void 446 pci_set_drvdata(struct pci_dev *pdev, void *data) 447 { 448 449 dev_set_drvdata(&pdev->dev, data); 450 } 451 452 static inline struct pci_dev * 453 pci_dev_get(struct pci_dev *pdev) 454 { 455 456 if (pdev != NULL) 457 get_device(&pdev->dev); 458 return (pdev); 459 } 460 461 static __inline void 462 pci_dev_put(struct pci_dev *pdev) 463 { 464 465 if (pdev != NULL) 466 put_device(&pdev->dev); 467 } 468 469 static inline int 470 pci_enable_device(struct pci_dev *pdev) 471 { 472 473 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 474 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 475 return (0); 476 } 477 478 static inline void 479 pci_disable_device(struct pci_dev *pdev) 480 { 481 482 pci_disable_busmaster(pdev->dev.bsddev); 483 } 484 485 static inline int 486 pci_set_master(struct pci_dev *pdev) 487 { 488 489 pci_enable_busmaster(pdev->dev.bsddev); 490 return (0); 491 } 492 493 static inline int 494 pci_set_power_state(struct pci_dev *pdev, int state) 495 { 496 497 pci_set_powerstate(pdev->dev.bsddev, state); 498 return (0); 499 } 500 501 static inline int 502 pci_clear_master(struct pci_dev *pdev) 503 { 504 505 pci_disable_busmaster(pdev->dev.bsddev); 506 return (0); 507 } 508 509 static inline bool 510 pci_is_root_bus(struct pci_bus *pbus) 511 { 512 513 return (pbus->self == NULL); 514 } 515 516 static inline struct pci_dev * 517 pci_upstream_bridge(struct pci_dev *pdev) 518 { 519 520 if (pci_is_root_bus(pdev->bus)) 521 return (NULL); 522 523 /* 524 * If we do not have a (proper) "upstream bridge" set, e.g., we point 525 * to ourselves, try to handle this case on the fly like we do 526 * for pcie_find_root_port(). 527 */ 528 if (pdev == pdev->bus->self) { 529 device_t bridge; 530 531 /* 532 * In the case of DRM drivers, the passed device is a child of 533 * `vgapci`. We want to start the lookup from `vgapci`, so the 534 * parent of the passed `drmn`. 535 * 536 * We can use the `isdrm` flag to determine this. 537 */ 538 bridge = pdev->dev.bsddev; 539 if (pdev->pdrv != NULL && pdev->pdrv->isdrm) 540 bridge = device_get_parent(bridge); 541 if (bridge == NULL) 542 goto done; 543 544 bridge = device_get_parent(bridge); 545 if (bridge == NULL) 546 goto done; 547 bridge = device_get_parent(bridge); 548 if (bridge == NULL) 549 goto done; 550 if (device_get_devclass(device_get_parent(bridge)) != 551 devclass_find("pci")) 552 goto done; 553 554 /* 555 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 556 * for it so it can be returned. 557 */ 558 pdev->bus->self = lkpinew_pci_dev(bridge); 559 } 560 done: 561 return (pdev->bus->self); 562 } 563 564 #define pci_release_region(pdev, bar) linuxkpi_pci_release_region(pdev, bar) 565 #define pci_release_regions(pdev) linuxkpi_pci_release_regions(pdev) 566 #define pci_request_regions(pdev, res_name) \ 567 linuxkpi_pci_request_regions(pdev, res_name) 568 569 static inline void 570 lkpi_pci_disable_msix(struct pci_dev *pdev) 571 { 572 573 pci_release_msi(pdev->dev.bsddev); 574 575 /* 576 * The MSIX IRQ numbers associated with this PCI device are no 577 * longer valid and might be re-assigned. Make sure 578 * lkpi_pci_find_irq_dev() does no longer see them by 579 * resetting their references to zero: 580 */ 581 pdev->dev.irq_start = 0; 582 pdev->dev.irq_end = 0; 583 pdev->msix_enabled = false; 584 } 585 /* Only for consistency. No conflict on that one. */ 586 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 587 588 static inline void 589 lkpi_pci_disable_msi(struct pci_dev *pdev) 590 { 591 592 pci_release_msi(pdev->dev.bsddev); 593 594 pdev->dev.irq_start = 0; 595 pdev->dev.irq_end = 0; 596 pdev->irq = pdev->dev.irq; 597 pdev->msi_enabled = false; 598 } 599 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 600 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 601 602 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 603 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 604 605 static inline bus_addr_t 606 pci_bus_address(struct pci_dev *pdev, int bar) 607 { 608 609 return (pci_resource_start(pdev, bar)); 610 } 611 612 #define PCI_CAP_ID_EXP PCIY_EXPRESS 613 #define PCI_CAP_ID_PCIX PCIY_PCIX 614 #define PCI_CAP_ID_AGP PCIY_AGP 615 #define PCI_CAP_ID_PM PCIY_PMG 616 617 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 618 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 619 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 620 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 621 #define PCI_EXP_LNKSTA PCIER_LINK_STA 622 623 static inline int 624 pci_find_capability(struct pci_dev *pdev, int capid) 625 { 626 int reg; 627 628 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 629 return (0); 630 return (reg); 631 } 632 633 static inline int pci_pcie_cap(struct pci_dev *dev) 634 { 635 return pci_find_capability(dev, PCI_CAP_ID_EXP); 636 } 637 638 static inline int 639 pci_find_ext_capability(struct pci_dev *pdev, int capid) 640 { 641 int reg; 642 643 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 644 return (0); 645 return (reg); 646 } 647 648 #define PCIM_PCAP_PME_SHIFT 11 649 static __inline bool 650 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 651 { 652 struct pci_devinfo *dinfo; 653 pcicfgregs *cfg; 654 655 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 656 return (false); 657 658 dinfo = device_get_ivars(pdev->dev.bsddev); 659 cfg = &dinfo->cfg; 660 661 if (cfg->pp.pp_cap == 0) 662 return (false); 663 664 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 665 return (true); 666 667 return (false); 668 } 669 670 static inline int 671 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 672 { 673 674 if (!pci_enable_aspm) 675 return (-EPERM); 676 677 return (-ENXIO); 678 } 679 680 static inline int 681 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 682 { 683 684 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 685 return (0); 686 } 687 688 static inline int 689 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 690 { 691 692 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 693 return (0); 694 } 695 696 static inline int 697 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 698 { 699 700 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 701 return (0); 702 } 703 704 static inline int 705 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 706 { 707 708 pci_write_config(pdev->dev.bsddev, where, val, 1); 709 return (0); 710 } 711 712 static inline int 713 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 714 { 715 716 pci_write_config(pdev->dev.bsddev, where, val, 2); 717 return (0); 718 } 719 720 static inline int 721 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 722 { 723 724 pci_write_config(pdev->dev.bsddev, where, val, 4); 725 return (0); 726 } 727 728 int linux_pci_register_driver(struct pci_driver *pdrv); 729 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 730 void linux_pci_unregister_driver(struct pci_driver *pdrv); 731 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 732 733 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 734 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 735 736 /* 737 * Enable msix, positive errors indicate actual number of available 738 * vectors. Negative errors are failures. 739 * 740 * NB: define added to prevent this definition of pci_enable_msix from 741 * clashing with the native FreeBSD version. 742 */ 743 #define pci_enable_msix(...) linuxkpi_pci_enable_msix(__VA_ARGS__) 744 745 #define pci_enable_msix_range(...) \ 746 linux_pci_enable_msix_range(__VA_ARGS__) 747 748 static inline int 749 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 750 int minvec, int maxvec) 751 { 752 int nvec = maxvec; 753 int rc; 754 755 if (maxvec < minvec) 756 return (-ERANGE); 757 758 do { 759 rc = pci_enable_msix(dev, entries, nvec); 760 if (rc < 0) { 761 return (rc); 762 } else if (rc > 0) { 763 if (rc < minvec) 764 return (-ENOSPC); 765 nvec = rc; 766 } 767 } while (rc); 768 return (nvec); 769 } 770 771 #define pci_enable_msi(pdev) \ 772 linux_pci_enable_msi(pdev) 773 774 static inline int 775 pci_enable_msi(struct pci_dev *pdev) 776 { 777 778 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 779 } 780 781 static inline int 782 pci_channel_offline(struct pci_dev *pdev) 783 { 784 785 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 786 } 787 788 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 789 { 790 return -ENODEV; 791 } 792 793 static inline void pci_disable_sriov(struct pci_dev *dev) 794 { 795 } 796 797 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \ 798 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) 799 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 800 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 801 #define pci_iounmap(pdev, res) linuxkpi_pci_iounmap(pdev, res) 802 803 static inline void 804 lkpi_pci_save_state(struct pci_dev *pdev) 805 { 806 807 pci_save_state(pdev->dev.bsddev); 808 } 809 810 static inline void 811 lkpi_pci_restore_state(struct pci_dev *pdev) 812 { 813 814 pci_restore_state(pdev->dev.bsddev); 815 } 816 817 #define pci_save_state(dev) lkpi_pci_save_state(dev) 818 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 819 820 static inline int 821 pci_reset_function(struct pci_dev *pdev) 822 { 823 824 return (-ENOSYS); 825 } 826 827 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 828 const struct pci_device_id _table[] __devinitdata 829 830 /* XXX This should not be necessary. */ 831 #define pcix_set_mmrbc(d, v) 0 832 #define pcix_get_max_mmrbc(d) 0 833 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 834 835 #define PCI_DMA_BIDIRECTIONAL 0 836 #define PCI_DMA_TODEVICE 1 837 #define PCI_DMA_FROMDEVICE 2 838 #define PCI_DMA_NONE 3 839 840 #define pci_pool dma_pool 841 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 842 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 843 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 844 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 845 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 846 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 847 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 848 _size, _vaddr, _dma_handle) 849 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 850 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 851 _sg, _nents, (enum dma_data_direction)_dir) 852 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 853 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 854 (_ptr), (_size), (enum dma_data_direction)_dir) 855 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 856 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 857 _addr, _size, (enum dma_data_direction)_dir) 858 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 859 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 860 _sg, _nents, (enum dma_data_direction)_dir) 861 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 862 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 863 _offset, _size, (enum dma_data_direction)_dir) 864 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 865 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 866 _dma_address, _size, (enum dma_data_direction)_dir) 867 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 868 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 869 dma_mapping_error(&(_pdev)->dev, _dma_addr) 870 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 871 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 872 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 873 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 874 #define pci_unmap_addr dma_unmap_addr 875 #define pci_unmap_addr_set dma_unmap_addr_set 876 #define pci_unmap_len dma_unmap_len 877 #define pci_unmap_len_set dma_unmap_len_set 878 879 typedef unsigned int __bitwise pci_channel_state_t; 880 typedef unsigned int __bitwise pci_ers_result_t; 881 882 enum pci_channel_state { 883 pci_channel_io_normal = 1, 884 pci_channel_io_frozen = 2, 885 pci_channel_io_perm_failure = 3, 886 }; 887 888 enum pci_ers_result { 889 PCI_ERS_RESULT_NONE = 1, 890 PCI_ERS_RESULT_CAN_RECOVER = 2, 891 PCI_ERS_RESULT_NEED_RESET = 3, 892 PCI_ERS_RESULT_DISCONNECT = 4, 893 PCI_ERS_RESULT_RECOVERED = 5, 894 }; 895 896 /* PCI bus error event callbacks */ 897 struct pci_error_handlers { 898 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 899 enum pci_channel_state error); 900 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 901 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 902 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 903 void (*resume)(struct pci_dev *dev); 904 }; 905 906 /* FreeBSD does not support SRIOV - yet */ 907 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 908 { 909 return dev; 910 } 911 912 static inline bool pci_is_pcie(struct pci_dev *dev) 913 { 914 return !!pci_pcie_cap(dev); 915 } 916 917 static inline u16 pcie_flags_reg(struct pci_dev *dev) 918 { 919 int pos; 920 u16 reg16; 921 922 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 923 if (!pos) 924 return 0; 925 926 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 927 928 return reg16; 929 } 930 931 static inline int pci_pcie_type(struct pci_dev *dev) 932 { 933 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 934 } 935 936 static inline int pcie_cap_version(struct pci_dev *dev) 937 { 938 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 939 } 940 941 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 942 { 943 int type = pci_pcie_type(dev); 944 945 return pcie_cap_version(dev) > 1 || 946 type == PCI_EXP_TYPE_ROOT_PORT || 947 type == PCI_EXP_TYPE_ENDPOINT || 948 type == PCI_EXP_TYPE_LEG_END; 949 } 950 951 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 952 { 953 return true; 954 } 955 956 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 957 { 958 int type = pci_pcie_type(dev); 959 960 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 961 (type == PCI_EXP_TYPE_DOWNSTREAM && 962 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 963 } 964 965 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 966 { 967 int type = pci_pcie_type(dev); 968 969 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 970 type == PCI_EXP_TYPE_RC_EC; 971 } 972 973 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 974 { 975 if (!pci_is_pcie(dev)) 976 return false; 977 978 switch (pos) { 979 case PCI_EXP_FLAGS_TYPE: 980 return true; 981 case PCI_EXP_DEVCAP: 982 case PCI_EXP_DEVCTL: 983 case PCI_EXP_DEVSTA: 984 return pcie_cap_has_devctl(dev); 985 case PCI_EXP_LNKCAP: 986 case PCI_EXP_LNKCTL: 987 case PCI_EXP_LNKSTA: 988 return pcie_cap_has_lnkctl(dev); 989 case PCI_EXP_SLTCAP: 990 case PCI_EXP_SLTCTL: 991 case PCI_EXP_SLTSTA: 992 return pcie_cap_has_sltctl(dev); 993 case PCI_EXP_RTCTL: 994 case PCI_EXP_RTCAP: 995 case PCI_EXP_RTSTA: 996 return pcie_cap_has_rtctl(dev); 997 case PCI_EXP_DEVCAP2: 998 case PCI_EXP_DEVCTL2: 999 case PCI_EXP_LNKCAP2: 1000 case PCI_EXP_LNKCTL2: 1001 case PCI_EXP_LNKSTA2: 1002 return pcie_cap_version(dev) > 1; 1003 default: 1004 return false; 1005 } 1006 } 1007 1008 static inline int 1009 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1010 { 1011 *dst = 0; 1012 if (pos & 3) 1013 return -EINVAL; 1014 1015 if (!pcie_capability_reg_implemented(dev, pos)) 1016 return -EINVAL; 1017 1018 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1019 } 1020 1021 static inline int 1022 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1023 { 1024 *dst = 0; 1025 if (pos & 3) 1026 return -EINVAL; 1027 1028 if (!pcie_capability_reg_implemented(dev, pos)) 1029 return -EINVAL; 1030 1031 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1032 } 1033 1034 static inline int 1035 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1036 { 1037 if (pos & 1) 1038 return -EINVAL; 1039 1040 if (!pcie_capability_reg_implemented(dev, pos)) 1041 return 0; 1042 1043 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1044 } 1045 1046 static inline int 1047 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1048 uint16_t clear, uint16_t set) 1049 { 1050 int error; 1051 uint16_t v; 1052 1053 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1054 spin_lock(&dev->pcie_cap_lock); 1055 1056 error = pcie_capability_read_word(dev, pos, &v); 1057 if (error == 0) { 1058 v &= ~clear; 1059 v |= set; 1060 error = pcie_capability_write_word(dev, pos, v); 1061 } 1062 1063 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1064 spin_unlock(&dev->pcie_cap_lock); 1065 1066 return (error); 1067 } 1068 1069 static inline int 1070 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1071 { 1072 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1073 } 1074 1075 static inline int 1076 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1077 { 1078 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1079 } 1080 1081 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1082 enum pci_bus_speed *speed, enum pcie_link_width *width) 1083 { 1084 *speed = PCI_SPEED_UNKNOWN; 1085 *width = PCIE_LNK_WIDTH_UNKNOWN; 1086 return (0); 1087 } 1088 1089 static inline int 1090 pci_num_vf(struct pci_dev *dev) 1091 { 1092 return (0); 1093 } 1094 1095 static inline enum pci_bus_speed 1096 pcie_get_speed_cap(struct pci_dev *dev) 1097 { 1098 device_t root; 1099 uint32_t lnkcap, lnkcap2; 1100 int error, pos; 1101 1102 root = device_get_parent(dev->dev.bsddev); 1103 if (root == NULL) 1104 return (PCI_SPEED_UNKNOWN); 1105 root = device_get_parent(root); 1106 if (root == NULL) 1107 return (PCI_SPEED_UNKNOWN); 1108 root = device_get_parent(root); 1109 if (root == NULL) 1110 return (PCI_SPEED_UNKNOWN); 1111 1112 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1113 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1114 return (PCI_SPEED_UNKNOWN); 1115 1116 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1117 return (PCI_SPEED_UNKNOWN); 1118 1119 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1120 1121 if (lnkcap2) { /* PCIe r3.0-compliant */ 1122 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1123 return (PCIE_SPEED_2_5GT); 1124 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1125 return (PCIE_SPEED_5_0GT); 1126 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1127 return (PCIE_SPEED_8_0GT); 1128 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1129 return (PCIE_SPEED_16_0GT); 1130 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1131 return (PCIE_SPEED_32_0GT); 1132 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1133 return (PCIE_SPEED_64_0GT); 1134 } else { /* pre-r3.0 */ 1135 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1136 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1137 return (PCIE_SPEED_2_5GT); 1138 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1139 return (PCIE_SPEED_5_0GT); 1140 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1141 return (PCIE_SPEED_8_0GT); 1142 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1143 return (PCIE_SPEED_16_0GT); 1144 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1145 return (PCIE_SPEED_32_0GT); 1146 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1147 return (PCIE_SPEED_64_0GT); 1148 } 1149 return (PCI_SPEED_UNKNOWN); 1150 } 1151 1152 static inline enum pcie_link_width 1153 pcie_get_width_cap(struct pci_dev *dev) 1154 { 1155 uint32_t lnkcap; 1156 1157 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1158 if (lnkcap) 1159 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1160 1161 return (PCIE_LNK_WIDTH_UNKNOWN); 1162 } 1163 1164 static inline int 1165 pcie_get_mps(struct pci_dev *dev) 1166 { 1167 return (pci_get_max_payload(dev->dev.bsddev)); 1168 } 1169 1170 static inline uint32_t 1171 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1172 { 1173 1174 switch(spd) { 1175 case PCIE_SPEED_64_0GT: 1176 return (64000 * 128 / 130); 1177 case PCIE_SPEED_32_0GT: 1178 return (32000 * 128 / 130); 1179 case PCIE_SPEED_16_0GT: 1180 return (16000 * 128 / 130); 1181 case PCIE_SPEED_8_0GT: 1182 return (8000 * 128 / 130); 1183 case PCIE_SPEED_5_0GT: 1184 return (5000 * 8 / 10); 1185 case PCIE_SPEED_2_5GT: 1186 return (2500 * 8 / 10); 1187 default: 1188 return (0); 1189 } 1190 } 1191 1192 static inline uint32_t 1193 pcie_bandwidth_available(struct pci_dev *pdev, 1194 struct pci_dev **limiting, 1195 enum pci_bus_speed *speed, 1196 enum pcie_link_width *width) 1197 { 1198 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1199 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1200 1201 if (speed) 1202 *speed = nspeed; 1203 if (width) 1204 *width = nwidth; 1205 1206 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1207 } 1208 1209 static inline bool 1210 pcie_aspm_enabled(struct pci_dev *pdev) 1211 { 1212 return (false); 1213 } 1214 1215 static inline struct pci_dev * 1216 pcie_find_root_port(struct pci_dev *pdev) 1217 { 1218 device_t root; 1219 1220 if (pdev->root != NULL) 1221 return (pdev->root); 1222 1223 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1224 if (root == NULL) 1225 return (NULL); 1226 1227 pdev->root = lkpinew_pci_dev(root); 1228 return (pdev->root); 1229 } 1230 1231 /* This is needed when people rip out the device "HotPlug". */ 1232 static inline void 1233 pci_lock_rescan_remove(void) 1234 { 1235 } 1236 1237 static inline void 1238 pci_unlock_rescan_remove(void) 1239 { 1240 } 1241 1242 static __inline void 1243 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1244 { 1245 } 1246 1247 static inline int 1248 pci_rescan_bus(struct pci_bus *pbus) 1249 { 1250 device_t *devlist, parent; 1251 int devcount, error; 1252 1253 if (!device_is_attached(pbus->self->dev.bsddev)) 1254 return (0); 1255 /* pci_rescan_method() will work on the pcib (parent). */ 1256 error = BUS_RESCAN(pbus->self->dev.bsddev); 1257 if (error != 0) 1258 return (0); 1259 1260 parent = device_get_parent(pbus->self->dev.bsddev); 1261 error = device_get_children(parent, &devlist, &devcount); 1262 if (error != 0) 1263 return (0); 1264 if (devcount != 0) 1265 free(devlist, M_TEMP); 1266 1267 return (devcount); 1268 } 1269 1270 /* 1271 * The following functions can be used to attach/detach the LinuxKPI's 1272 * PCI device runtime. The pci_driver and pci_device_id pointer is 1273 * allowed to be NULL. Other pointers must be all valid. 1274 * The pci_dev structure should be zero-initialized before passed 1275 * to the linux_pci_attach_device function. 1276 */ 1277 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1278 const struct pci_device_id *, struct pci_dev *); 1279 extern int linux_pci_detach_device(struct pci_dev *); 1280 1281 static inline int 1282 pci_dev_present(const struct pci_device_id *cur) 1283 { 1284 while (cur != NULL && (cur->vendor || cur->device)) { 1285 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1286 return (1); 1287 } 1288 cur++; 1289 } 1290 return (0); 1291 } 1292 1293 static inline const struct pci_device_id * 1294 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 1295 { 1296 if (ids == NULL) 1297 return (NULL); 1298 1299 for (; 1300 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0; 1301 ids++) 1302 if ((ids->vendor == PCI_ANY_ID || 1303 ids->vendor == pdev->vendor) && 1304 (ids->device == PCI_ANY_ID || 1305 ids->device == pdev->device) && 1306 (ids->subvendor == PCI_ANY_ID || 1307 ids->subvendor == pdev->subsystem_vendor) && 1308 (ids->subdevice == PCI_ANY_ID || 1309 ids->subdevice == pdev->subsystem_device) && 1310 ((ids->class ^ pdev->class) & ids->class_mask) == 0) 1311 return (ids); 1312 1313 return (NULL); 1314 } 1315 1316 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1317 unsigned int bus, unsigned int devfn); 1318 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1319 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1320 1321 static inline int 1322 pci_domain_nr(struct pci_bus *pbus) 1323 { 1324 1325 return (pbus->domain); 1326 } 1327 1328 static inline int 1329 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1330 int pos, uint32_t *val, int len) 1331 { 1332 1333 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1334 return (0); 1335 } 1336 1337 static inline int 1338 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1339 { 1340 uint32_t tmp; 1341 int ret; 1342 1343 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1344 *val = (u16)tmp; 1345 return (ret); 1346 } 1347 1348 static inline int 1349 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1350 { 1351 uint32_t tmp; 1352 int ret; 1353 1354 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1355 *val = (u8)tmp; 1356 return (ret); 1357 } 1358 1359 static inline int 1360 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1361 uint32_t val, int size) 1362 { 1363 1364 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1365 return (0); 1366 } 1367 1368 static inline int 1369 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1370 uint8_t val) 1371 { 1372 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1373 } 1374 1375 static inline int 1376 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1377 uint16_t val) 1378 { 1379 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1380 } 1381 1382 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1383 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1384 struct pci_dev *lkpi_pci_get_base_class(unsigned int class, 1385 struct pci_dev *from); 1386 #define pci_get_base_class(class, from) lkpi_pci_get_base_class(class, from) 1387 1388 /* -------------------------------------------------------------------------- */ 1389 1390 #define pcim_enable_device(pdev) linuxkpi_pcim_enable_device(pdev) 1391 #define pcim_iomap_table(pdev) linuxkpi_pcim_iomap_table(pdev) 1392 #define pcim_iomap_regions(pdev, mask, name) \ 1393 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1394 1395 static inline int 1396 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1397 { 1398 uint32_t requests, req_mask; 1399 int bar, error; 1400 1401 /* Request all the BARs ("regions") we do not iomap. */ 1402 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1403 for (bar = requests = 0; requests != req_mask; bar++) { 1404 if ((req_mask & (1 << bar)) == 0) 1405 continue; 1406 error = pci_request_region(pdev, bar, name); 1407 if (error != 0 && error != -ENODEV) 1408 goto err; 1409 requests |= (1 << bar); 1410 } 1411 1412 error = pcim_iomap_regions(pdev, mask, name); 1413 if (error != 0) 1414 goto err; 1415 1416 return (0); 1417 1418 err: 1419 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1420 if ((requests & (1 << bar)) != 0) 1421 pci_release_region(pdev, bar); 1422 } 1423 1424 return (-EINVAL); 1425 } 1426 1427 /* 1428 * We cannot simply re-define pci_get_device() as we would normally do 1429 * and then hide it in linux_pci.c as too many semi-native drivers still 1430 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1431 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1432 */ 1433 static inline struct pci_dev * 1434 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1435 { 1436 1437 return (lkpi_pci_get_device(vendor, device, odev)); 1438 } 1439 1440 /* This is a FreeBSD extension so we can use bus_*(). */ 1441 static inline void 1442 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1443 { 1444 pdev->want_iomap_res = true; 1445 } 1446 1447 static inline bool 1448 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1449 { 1450 1451 return (false); 1452 } 1453 1454 static inline void * 1455 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1456 { 1457 1458 return (NULL); 1459 } 1460 1461 static inline void 1462 pci_ignore_hotplug(struct pci_dev *pdev) 1463 { 1464 } 1465 1466 static inline const char * 1467 pci_power_name(pci_power_t state) 1468 { 1469 int pstate = state + 1; 1470 1471 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1472 return (pci_power_names[pstate]); 1473 else 1474 return (pci_power_names[0]); 1475 } 1476 1477 static inline int 1478 pcie_get_readrq(struct pci_dev *dev) 1479 { 1480 u16 ctl; 1481 1482 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1483 return (-EINVAL); 1484 1485 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1486 } 1487 1488 static inline bool 1489 pci_is_enabled(struct pci_dev *pdev) 1490 { 1491 1492 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1493 PCIM_CMD_BUSMASTEREN) != 0); 1494 } 1495 1496 static inline int 1497 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1498 { 1499 1500 return (0); 1501 } 1502 1503 static inline int 1504 pci_assign_resource(struct pci_dev *pdev, int bar) 1505 { 1506 1507 return (0); 1508 } 1509 1510 static inline int 1511 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1512 { 1513 1514 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1515 if (vector != 0) 1516 return (-EINVAL); 1517 return (pdev->irq); 1518 } 1519 1520 if (pdev->msix_enabled || pdev->msi_enabled) { 1521 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1522 return (-EINVAL); 1523 return (pdev->dev.irq_start + vector); 1524 } 1525 1526 return (-ENXIO); 1527 } 1528 1529 static inline int 1530 pci_wake_from_d3(struct pci_dev *pdev, bool enable) 1531 { 1532 1533 pr_debug("%s: TODO\n", __func__); 1534 return (0); 1535 } 1536 1537 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1538