1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/nv.h> 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 #include <linux/pm.h> 63 64 struct pci_device_id { 65 uint32_t vendor; 66 uint32_t device; 67 uint32_t subvendor; 68 uint32_t subdevice; 69 uint32_t class; 70 uint32_t class_mask; 71 uintptr_t driver_data; 72 }; 73 74 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 75 #define MODULE_DEVICE_TABLE(_bus, _table) \ 76 \ 77 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 78 DEVMETHOD_END \ 79 }; \ 80 \ 81 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 82 "lkpi_" #_bus #_table, \ 83 _ ## _bus ## _ ## _table ## _methods, \ 84 0 \ 85 }; \ 86 \ 87 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 88 0, 0); \ 89 \ 90 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 91 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 92 93 #define PCI_ANY_ID -1U 94 95 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 96 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 97 #define PCI_FUNC(devfn) ((devfn) & 0x07) 98 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 99 100 #define PCI_VDEVICE(_vendor, _device) \ 101 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 102 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 103 #define PCI_DEVICE(_vendor, _device) \ 104 .vendor = (_vendor), .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 107 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 108 109 #define PCI_VENDOR_ID PCIR_VENDOR 110 #define PCI_DEVICE_ID PCIR_DEVICE 111 #define PCI_COMMAND PCIR_COMMAND 112 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 115 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 116 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 117 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 118 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 119 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 120 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 121 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 122 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 123 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 124 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 125 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 126 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 127 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 128 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 129 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 130 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 131 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 132 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 133 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 134 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 135 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 136 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 137 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 138 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 139 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 140 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 141 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 142 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 143 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 144 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 145 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 146 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 147 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 148 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 149 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 150 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 151 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 152 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 153 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 154 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 155 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 156 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 157 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 158 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 159 #define PCI_EXP_LNKCTL2_TLS 0x000f 160 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 161 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 162 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 163 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 164 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 165 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 166 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 167 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 168 169 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 170 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 171 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 172 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 173 174 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 175 #define PCI_EXP_DEVSTA_TRPND 0x0020 176 177 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 178 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 179 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 180 181 enum pci_bus_speed { 182 PCI_SPEED_UNKNOWN = -1, 183 PCIE_SPEED_2_5GT, 184 PCIE_SPEED_5_0GT, 185 PCIE_SPEED_8_0GT, 186 PCIE_SPEED_16_0GT, 187 PCIE_SPEED_32_0GT, 188 PCIE_SPEED_64_0GT, 189 }; 190 191 enum pcie_link_width { 192 PCIE_LNK_WIDTH_RESRV = 0x00, 193 PCIE_LNK_X1 = 0x01, 194 PCIE_LNK_X2 = 0x02, 195 PCIE_LNK_X4 = 0x04, 196 PCIE_LNK_X8 = 0x08, 197 PCIE_LNK_X12 = 0x0c, 198 PCIE_LNK_X16 = 0x10, 199 PCIE_LNK_X32 = 0x20, 200 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 201 }; 202 203 #define PCIE_LINK_STATE_L0S 0x00000001 204 #define PCIE_LINK_STATE_L1 0x00000002 205 #define PCIE_LINK_STATE_CLKPM 0x00000004 206 207 typedef int pci_power_t; 208 209 #define PCI_D0 PCI_POWERSTATE_D0 210 #define PCI_D1 PCI_POWERSTATE_D1 211 #define PCI_D2 PCI_POWERSTATE_D2 212 #define PCI_D3hot PCI_POWERSTATE_D3 213 #define PCI_D3cold 4 214 215 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 216 217 extern const char *pci_power_names[6]; 218 219 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 220 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 221 222 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 223 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 224 225 #define PCI_L1SS_CTL1 0x8 226 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 227 228 #define PCI_IRQ_LEGACY 0x01 229 #define PCI_IRQ_MSI 0x02 230 #define PCI_IRQ_MSIX 0x04 231 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 232 233 struct pci_dev; 234 235 struct pci_driver { 236 struct list_head node; 237 char *name; 238 const struct pci_device_id *id_table; 239 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 240 void (*remove)(struct pci_dev *dev); 241 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 242 int (*resume) (struct pci_dev *dev); /* Device woken up */ 243 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 244 driver_t bsddriver; 245 devclass_t bsdclass; 246 struct device_driver driver; 247 const struct pci_error_handlers *err_handler; 248 bool isdrm; 249 int bsd_probe_return; 250 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 251 const nvlist_t *pf_config); 252 void (*bsd_iov_uninit)(device_t dev); 253 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 254 const nvlist_t *vf_config); 255 }; 256 257 struct pci_bus { 258 struct pci_dev *self; 259 int domain; 260 int number; 261 }; 262 263 extern struct list_head pci_drivers; 264 extern struct list_head pci_devices; 265 extern spinlock_t pci_lock; 266 267 #define __devexit_p(x) x 268 269 #define module_pci_driver(_driver) \ 270 \ 271 static inline int \ 272 _pci_init(void) \ 273 { \ 274 \ 275 return (linux_pci_register_driver(&_driver)); \ 276 } \ 277 \ 278 static inline void \ 279 _pci_exit(void) \ 280 { \ 281 \ 282 linux_pci_unregister_driver(&_driver); \ 283 } \ 284 \ 285 module_init(_pci_init); \ 286 module_exit(_pci_exit) 287 288 /* 289 * If we find drivers accessing this from multiple KPIs we may have to 290 * refcount objects of this structure. 291 */ 292 struct pci_mmio_region { 293 TAILQ_ENTRY(pci_mmio_region) next; 294 struct resource *res; 295 int rid; 296 int type; 297 }; 298 299 struct pci_dev { 300 struct device dev; 301 struct list_head links; 302 struct pci_driver *pdrv; 303 struct pci_bus *bus; 304 struct pci_dev *root; 305 pci_power_t current_state; 306 uint16_t device; 307 uint16_t vendor; 308 uint16_t subsystem_vendor; 309 uint16_t subsystem_device; 310 unsigned int irq; 311 unsigned int devfn; 312 uint32_t class; 313 uint8_t revision; 314 bool managed; /* devres "pcim_*(). */ 315 bool want_iomap_res; 316 bool msi_enabled; 317 bool msix_enabled; 318 phys_addr_t rom; 319 size_t romlen; 320 321 TAILQ_HEAD(, pci_mmio_region) mmio; 322 }; 323 324 /* We need some meta-struct to keep track of these for devres. */ 325 struct pci_devres { 326 bool enable_io; 327 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 328 uint8_t region_mask; 329 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 330 }; 331 struct pcim_iomap_devres { 332 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 333 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 334 }; 335 336 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 337 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 338 unsigned int flags); 339 340 /* Internal helper function(s). */ 341 struct pci_dev *lkpinew_pci_dev(device_t); 342 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev); 343 void lkpi_pci_devres_release(struct device *, void *); 344 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size); 345 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev); 346 void lkpi_pcim_iomap_table_release(struct device *, void *); 347 348 static inline bool 349 dev_is_pci(struct device *dev) 350 { 351 352 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 353 } 354 355 static inline int 356 pci_resource_type(struct pci_dev *pdev, int bar) 357 { 358 struct pci_map *pm; 359 360 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 361 if (!pm) 362 return (-1); 363 364 if (PCI_BAR_IO(pm->pm_value)) 365 return (SYS_RES_IOPORT); 366 else 367 return (SYS_RES_MEMORY); 368 } 369 370 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 371 struct resource_list *rl, int type, int rid); 372 373 static inline struct resource_list_entry * 374 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 375 { 376 struct pci_devinfo *dinfo; 377 struct resource_list *rl; 378 struct resource_list_entry *rle; 379 380 dinfo = device_get_ivars(pdev->dev.bsddev); 381 rl = &dinfo->resources; 382 rle = resource_list_find(rl, type, rid); 383 /* Reserve resources for this BAR if needed. */ 384 if (rle == NULL && reserve_bar) 385 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 386 return (rle); 387 } 388 389 static inline struct resource_list_entry * 390 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 391 { 392 int type; 393 394 type = pci_resource_type(pdev, bar); 395 if (type < 0) 396 return (NULL); 397 bar = PCIR_BAR(bar); 398 return (linux_pci_get_rle(pdev, type, bar, reserve)); 399 } 400 401 static inline struct device * 402 linux_pci_find_irq_dev(unsigned int irq) 403 { 404 struct pci_dev *pdev; 405 struct device *found; 406 407 found = NULL; 408 spin_lock(&pci_lock); 409 list_for_each_entry(pdev, &pci_devices, links) { 410 if (irq == pdev->dev.irq || 411 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 412 found = &pdev->dev; 413 break; 414 } 415 } 416 spin_unlock(&pci_lock); 417 return (found); 418 } 419 420 /* 421 * All drivers just seem to want to inspect the type not flags. 422 */ 423 static inline int 424 pci_resource_flags(struct pci_dev *pdev, int bar) 425 { 426 int type; 427 428 type = pci_resource_type(pdev, bar); 429 if (type < 0) 430 return (0); 431 return (1 << type); 432 } 433 434 static inline const char * 435 pci_name(struct pci_dev *d) 436 { 437 438 return device_get_desc(d->dev.bsddev); 439 } 440 441 static inline void * 442 pci_get_drvdata(struct pci_dev *pdev) 443 { 444 445 return dev_get_drvdata(&pdev->dev); 446 } 447 448 static inline void 449 pci_set_drvdata(struct pci_dev *pdev, void *data) 450 { 451 452 dev_set_drvdata(&pdev->dev, data); 453 } 454 455 static inline struct pci_dev * 456 pci_dev_get(struct pci_dev *pdev) 457 { 458 459 if (pdev != NULL) 460 get_device(&pdev->dev); 461 return (pdev); 462 } 463 464 static __inline void 465 pci_dev_put(struct pci_dev *pdev) 466 { 467 468 if (pdev != NULL) 469 put_device(&pdev->dev); 470 } 471 472 static inline int 473 pci_enable_device(struct pci_dev *pdev) 474 { 475 476 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 477 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 478 return (0); 479 } 480 481 static inline void 482 pci_disable_device(struct pci_dev *pdev) 483 { 484 485 pci_disable_busmaster(pdev->dev.bsddev); 486 } 487 488 static inline int 489 pci_set_master(struct pci_dev *pdev) 490 { 491 492 pci_enable_busmaster(pdev->dev.bsddev); 493 return (0); 494 } 495 496 static inline int 497 pci_set_power_state(struct pci_dev *pdev, int state) 498 { 499 500 pci_set_powerstate(pdev->dev.bsddev, state); 501 return (0); 502 } 503 504 static inline int 505 pci_clear_master(struct pci_dev *pdev) 506 { 507 508 pci_disable_busmaster(pdev->dev.bsddev); 509 return (0); 510 } 511 512 static inline bool 513 pci_is_root_bus(struct pci_bus *pbus) 514 { 515 516 return (pbus->self == NULL); 517 } 518 519 static inline struct pci_dev * 520 pci_upstream_bridge(struct pci_dev *pdev) 521 { 522 523 if (pci_is_root_bus(pdev->bus)) 524 return (NULL); 525 526 /* 527 * If we do not have a (proper) "upstream bridge" set, e.g., we point 528 * to ourselves, try to handle this case on the fly like we do 529 * for pcie_find_root_port(). 530 */ 531 if (pdev == pdev->bus->self) { 532 device_t bridge; 533 534 bridge = device_get_parent(pdev->dev.bsddev); 535 if (bridge == NULL) 536 goto done; 537 bridge = device_get_parent(bridge); 538 if (bridge == NULL) 539 goto done; 540 if (device_get_devclass(device_get_parent(bridge)) != 541 devclass_find("pci")) 542 goto done; 543 544 /* 545 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 546 * for it so it can be returned. 547 */ 548 pdev->bus->self = lkpinew_pci_dev(bridge); 549 } 550 done: 551 return (pdev->bus->self); 552 } 553 554 static inline struct pci_devres * 555 lkpi_pci_devres_find(struct pci_dev *pdev) 556 { 557 558 if (!pdev->managed) 559 return (NULL); 560 561 return (lkpi_pci_devres_get_alloc(pdev)); 562 } 563 564 static inline void 565 pci_release_region(struct pci_dev *pdev, int bar) 566 { 567 struct resource_list_entry *rle; 568 struct pci_devres *dr; 569 struct pci_mmio_region *mmio, *p; 570 571 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 572 return; 573 574 /* 575 * As we implicitly track the requests we also need to clear them on 576 * release. Do clear before resource release. 577 */ 578 dr = lkpi_pci_devres_find(pdev); 579 if (dr != NULL) { 580 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 581 " region_table res %p != rel->res %p\n", __func__, pdev, 582 bar, dr->region_table[bar], rle->res)); 583 dr->region_table[bar] = NULL; 584 dr->region_mask &= ~(1 << bar); 585 } 586 587 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 588 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 589 continue; 590 TAILQ_REMOVE(&pdev->mmio, mmio, next); 591 free(mmio, M_DEVBUF); 592 } 593 594 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 595 } 596 597 static inline void 598 pci_release_regions(struct pci_dev *pdev) 599 { 600 int i; 601 602 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 603 pci_release_region(pdev, i); 604 } 605 606 static inline int 607 pci_request_regions(struct pci_dev *pdev, const char *res_name) 608 { 609 int error; 610 int i; 611 612 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 613 error = pci_request_region(pdev, i, res_name); 614 if (error && error != -ENODEV) { 615 pci_release_regions(pdev); 616 return (error); 617 } 618 } 619 return (0); 620 } 621 622 static inline void 623 lkpi_pci_disable_msix(struct pci_dev *pdev) 624 { 625 626 pci_release_msi(pdev->dev.bsddev); 627 628 /* 629 * The MSIX IRQ numbers associated with this PCI device are no 630 * longer valid and might be re-assigned. Make sure 631 * linux_pci_find_irq_dev() does no longer see them by 632 * resetting their references to zero: 633 */ 634 pdev->dev.irq_start = 0; 635 pdev->dev.irq_end = 0; 636 pdev->msix_enabled = false; 637 } 638 /* Only for consistency. No conflict on that one. */ 639 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 640 641 static inline void 642 lkpi_pci_disable_msi(struct pci_dev *pdev) 643 { 644 645 pci_release_msi(pdev->dev.bsddev); 646 647 pdev->dev.irq_start = 0; 648 pdev->dev.irq_end = 0; 649 pdev->irq = pdev->dev.irq; 650 pdev->msi_enabled = false; 651 } 652 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 653 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 654 655 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 656 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 657 658 static inline bus_addr_t 659 pci_bus_address(struct pci_dev *pdev, int bar) 660 { 661 662 return (pci_resource_start(pdev, bar)); 663 } 664 665 #define PCI_CAP_ID_EXP PCIY_EXPRESS 666 #define PCI_CAP_ID_PCIX PCIY_PCIX 667 #define PCI_CAP_ID_AGP PCIY_AGP 668 #define PCI_CAP_ID_PM PCIY_PMG 669 670 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 671 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 672 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 673 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 674 #define PCI_EXP_LNKSTA PCIER_LINK_STA 675 676 static inline int 677 pci_find_capability(struct pci_dev *pdev, int capid) 678 { 679 int reg; 680 681 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 682 return (0); 683 return (reg); 684 } 685 686 static inline int pci_pcie_cap(struct pci_dev *dev) 687 { 688 return pci_find_capability(dev, PCI_CAP_ID_EXP); 689 } 690 691 static inline int 692 pci_find_ext_capability(struct pci_dev *pdev, int capid) 693 { 694 int reg; 695 696 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 697 return (0); 698 return (reg); 699 } 700 701 #define PCIM_PCAP_PME_SHIFT 11 702 static __inline bool 703 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 704 { 705 struct pci_devinfo *dinfo; 706 pcicfgregs *cfg; 707 708 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 709 return (false); 710 711 dinfo = device_get_ivars(pdev->dev.bsddev); 712 cfg = &dinfo->cfg; 713 714 if (cfg->pp.pp_cap == 0) 715 return (false); 716 717 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 718 return (true); 719 720 return (false); 721 } 722 723 static inline int 724 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 725 { 726 727 if (!pci_enable_aspm) 728 return (-EPERM); 729 730 return (-ENXIO); 731 } 732 733 static inline int 734 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 735 { 736 737 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 738 return (0); 739 } 740 741 static inline int 742 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 743 { 744 745 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 746 return (0); 747 } 748 749 static inline int 750 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 751 { 752 753 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 754 return (0); 755 } 756 757 static inline int 758 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 759 { 760 761 pci_write_config(pdev->dev.bsddev, where, val, 1); 762 return (0); 763 } 764 765 static inline int 766 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 767 { 768 769 pci_write_config(pdev->dev.bsddev, where, val, 2); 770 return (0); 771 } 772 773 static inline int 774 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 775 { 776 777 pci_write_config(pdev->dev.bsddev, where, val, 4); 778 return (0); 779 } 780 781 int linux_pci_register_driver(struct pci_driver *pdrv); 782 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 783 void linux_pci_unregister_driver(struct pci_driver *pdrv); 784 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 785 786 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 787 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 788 789 struct msix_entry { 790 int entry; 791 int vector; 792 }; 793 794 /* 795 * Enable msix, positive errors indicate actual number of available 796 * vectors. Negative errors are failures. 797 * 798 * NB: define added to prevent this definition of pci_enable_msix from 799 * clashing with the native FreeBSD version. 800 */ 801 #define pci_enable_msix(...) \ 802 linux_pci_enable_msix(__VA_ARGS__) 803 804 static inline int 805 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 806 { 807 struct resource_list_entry *rle; 808 int error; 809 int avail; 810 int i; 811 812 avail = pci_msix_count(pdev->dev.bsddev); 813 if (avail < nreq) { 814 if (avail == 0) 815 return -EINVAL; 816 return avail; 817 } 818 avail = nreq; 819 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 820 return error; 821 /* 822 * Handle case where "pci_alloc_msix()" may allocate less 823 * interrupts than available and return with no error: 824 */ 825 if (avail < nreq) { 826 pci_release_msi(pdev->dev.bsddev); 827 return avail; 828 } 829 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 830 pdev->dev.irq_start = rle->start; 831 pdev->dev.irq_end = rle->start + avail; 832 for (i = 0; i < nreq; i++) 833 entries[i].vector = pdev->dev.irq_start + i; 834 pdev->msix_enabled = true; 835 return (0); 836 } 837 838 #define pci_enable_msix_range(...) \ 839 linux_pci_enable_msix_range(__VA_ARGS__) 840 841 static inline int 842 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 843 int minvec, int maxvec) 844 { 845 int nvec = maxvec; 846 int rc; 847 848 if (maxvec < minvec) 849 return (-ERANGE); 850 851 do { 852 rc = pci_enable_msix(dev, entries, nvec); 853 if (rc < 0) { 854 return (rc); 855 } else if (rc > 0) { 856 if (rc < minvec) 857 return (-ENOSPC); 858 nvec = rc; 859 } 860 } while (rc); 861 return (nvec); 862 } 863 864 #define pci_enable_msi(pdev) \ 865 linux_pci_enable_msi(pdev) 866 867 static inline int 868 pci_enable_msi(struct pci_dev *pdev) 869 { 870 struct resource_list_entry *rle; 871 int error; 872 int avail; 873 874 avail = pci_msi_count(pdev->dev.bsddev); 875 if (avail < 1) 876 return -EINVAL; 877 878 avail = 1; /* this function only enable one MSI IRQ */ 879 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 880 return error; 881 882 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 883 pdev->dev.irq_start = rle->start; 884 pdev->dev.irq_end = rle->start + avail; 885 pdev->irq = rle->start; 886 pdev->msi_enabled = true; 887 return (0); 888 } 889 890 static inline int 891 pci_channel_offline(struct pci_dev *pdev) 892 { 893 894 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 895 } 896 897 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 898 { 899 return -ENODEV; 900 } 901 902 static inline void pci_disable_sriov(struct pci_dev *dev) 903 { 904 } 905 906 static inline void * 907 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 908 { 909 struct resource *res; 910 911 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 912 if (res == NULL) 913 return (NULL); 914 /* This is a FreeBSD extension so we can use bus_*(). */ 915 if (pdev->want_iomap_res) 916 return (res); 917 return ((void *)rman_get_bushandle(res)); 918 } 919 920 static inline void 921 pci_iounmap(struct pci_dev *pdev, void *res) 922 { 923 struct pci_mmio_region *mmio, *p; 924 925 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 926 if (res != (void *)rman_get_bushandle(mmio->res)) 927 continue; 928 bus_release_resource(pdev->dev.bsddev, 929 mmio->type, mmio->rid, mmio->res); 930 TAILQ_REMOVE(&pdev->mmio, mmio, next); 931 free(mmio, M_DEVBUF); 932 return; 933 } 934 } 935 936 static inline void 937 lkpi_pci_save_state(struct pci_dev *pdev) 938 { 939 940 pci_save_state(pdev->dev.bsddev); 941 } 942 943 static inline void 944 lkpi_pci_restore_state(struct pci_dev *pdev) 945 { 946 947 pci_restore_state(pdev->dev.bsddev); 948 } 949 950 #define pci_save_state(dev) lkpi_pci_save_state(dev) 951 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 952 953 static inline int 954 pci_reset_function(struct pci_dev *pdev) 955 { 956 957 return (-ENOSYS); 958 } 959 960 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 961 const struct pci_device_id _table[] __devinitdata 962 963 /* XXX This should not be necessary. */ 964 #define pcix_set_mmrbc(d, v) 0 965 #define pcix_get_max_mmrbc(d) 0 966 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 967 968 #define PCI_DMA_BIDIRECTIONAL 0 969 #define PCI_DMA_TODEVICE 1 970 #define PCI_DMA_FROMDEVICE 2 971 #define PCI_DMA_NONE 3 972 973 #define pci_pool dma_pool 974 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 975 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 976 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 977 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 978 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 979 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 980 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 981 _size, _vaddr, _dma_handle) 982 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 983 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 984 _sg, _nents, (enum dma_data_direction)_dir) 985 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 986 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 987 (_ptr), (_size), (enum dma_data_direction)_dir) 988 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 989 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 990 _addr, _size, (enum dma_data_direction)_dir) 991 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 992 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 993 _sg, _nents, (enum dma_data_direction)_dir) 994 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 995 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 996 _offset, _size, (enum dma_data_direction)_dir) 997 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 998 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 999 _dma_address, _size, (enum dma_data_direction)_dir) 1000 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1001 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1002 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1003 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1004 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1005 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1006 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1007 #define pci_unmap_addr dma_unmap_addr 1008 #define pci_unmap_addr_set dma_unmap_addr_set 1009 #define pci_unmap_len dma_unmap_len 1010 #define pci_unmap_len_set dma_unmap_len_set 1011 1012 typedef unsigned int __bitwise pci_channel_state_t; 1013 typedef unsigned int __bitwise pci_ers_result_t; 1014 1015 enum pci_channel_state { 1016 pci_channel_io_normal = 1, 1017 pci_channel_io_frozen = 2, 1018 pci_channel_io_perm_failure = 3, 1019 }; 1020 1021 enum pci_ers_result { 1022 PCI_ERS_RESULT_NONE = 1, 1023 PCI_ERS_RESULT_CAN_RECOVER = 2, 1024 PCI_ERS_RESULT_NEED_RESET = 3, 1025 PCI_ERS_RESULT_DISCONNECT = 4, 1026 PCI_ERS_RESULT_RECOVERED = 5, 1027 }; 1028 1029 /* PCI bus error event callbacks */ 1030 struct pci_error_handlers { 1031 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1032 enum pci_channel_state error); 1033 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1034 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1035 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1036 void (*resume)(struct pci_dev *dev); 1037 }; 1038 1039 /* FreeBSD does not support SRIOV - yet */ 1040 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1041 { 1042 return dev; 1043 } 1044 1045 static inline bool pci_is_pcie(struct pci_dev *dev) 1046 { 1047 return !!pci_pcie_cap(dev); 1048 } 1049 1050 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1051 { 1052 int pos; 1053 u16 reg16; 1054 1055 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1056 if (!pos) 1057 return 0; 1058 1059 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1060 1061 return reg16; 1062 } 1063 1064 static inline int pci_pcie_type(struct pci_dev *dev) 1065 { 1066 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1067 } 1068 1069 static inline int pcie_cap_version(struct pci_dev *dev) 1070 { 1071 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1072 } 1073 1074 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1075 { 1076 int type = pci_pcie_type(dev); 1077 1078 return pcie_cap_version(dev) > 1 || 1079 type == PCI_EXP_TYPE_ROOT_PORT || 1080 type == PCI_EXP_TYPE_ENDPOINT || 1081 type == PCI_EXP_TYPE_LEG_END; 1082 } 1083 1084 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1085 { 1086 return true; 1087 } 1088 1089 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1090 { 1091 int type = pci_pcie_type(dev); 1092 1093 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1094 (type == PCI_EXP_TYPE_DOWNSTREAM && 1095 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1096 } 1097 1098 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1099 { 1100 int type = pci_pcie_type(dev); 1101 1102 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1103 type == PCI_EXP_TYPE_RC_EC; 1104 } 1105 1106 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1107 { 1108 if (!pci_is_pcie(dev)) 1109 return false; 1110 1111 switch (pos) { 1112 case PCI_EXP_FLAGS_TYPE: 1113 return true; 1114 case PCI_EXP_DEVCAP: 1115 case PCI_EXP_DEVCTL: 1116 case PCI_EXP_DEVSTA: 1117 return pcie_cap_has_devctl(dev); 1118 case PCI_EXP_LNKCAP: 1119 case PCI_EXP_LNKCTL: 1120 case PCI_EXP_LNKSTA: 1121 return pcie_cap_has_lnkctl(dev); 1122 case PCI_EXP_SLTCAP: 1123 case PCI_EXP_SLTCTL: 1124 case PCI_EXP_SLTSTA: 1125 return pcie_cap_has_sltctl(dev); 1126 case PCI_EXP_RTCTL: 1127 case PCI_EXP_RTCAP: 1128 case PCI_EXP_RTSTA: 1129 return pcie_cap_has_rtctl(dev); 1130 case PCI_EXP_DEVCAP2: 1131 case PCI_EXP_DEVCTL2: 1132 case PCI_EXP_LNKCAP2: 1133 case PCI_EXP_LNKCTL2: 1134 case PCI_EXP_LNKSTA2: 1135 return pcie_cap_version(dev) > 1; 1136 default: 1137 return false; 1138 } 1139 } 1140 1141 static inline int 1142 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1143 { 1144 if (pos & 3) 1145 return -EINVAL; 1146 1147 if (!pcie_capability_reg_implemented(dev, pos)) 1148 return -EINVAL; 1149 1150 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1151 } 1152 1153 static inline int 1154 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1155 { 1156 if (pos & 3) 1157 return -EINVAL; 1158 1159 if (!pcie_capability_reg_implemented(dev, pos)) 1160 return -EINVAL; 1161 1162 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1163 } 1164 1165 static inline int 1166 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1167 { 1168 if (pos & 1) 1169 return -EINVAL; 1170 1171 if (!pcie_capability_reg_implemented(dev, pos)) 1172 return 0; 1173 1174 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1175 } 1176 1177 static inline int 1178 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1179 { 1180 int error; 1181 uint16_t v; 1182 1183 error = pcie_capability_read_word(dev, pos, &v); 1184 if (error != 0) 1185 return (error); 1186 1187 v |= val; 1188 1189 error = pcie_capability_write_word(dev, pos, v); 1190 return (error); 1191 } 1192 1193 static inline int 1194 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1195 { 1196 int error; 1197 uint16_t v; 1198 1199 error = pcie_capability_read_word(dev, pos, &v); 1200 if (error != 0) 1201 return (error); 1202 1203 v &= ~val; 1204 1205 error = pcie_capability_write_word(dev, pos, v); 1206 return (error); 1207 } 1208 1209 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1210 enum pci_bus_speed *speed, enum pcie_link_width *width) 1211 { 1212 *speed = PCI_SPEED_UNKNOWN; 1213 *width = PCIE_LNK_WIDTH_UNKNOWN; 1214 return (0); 1215 } 1216 1217 static inline int 1218 pci_num_vf(struct pci_dev *dev) 1219 { 1220 return (0); 1221 } 1222 1223 static inline enum pci_bus_speed 1224 pcie_get_speed_cap(struct pci_dev *dev) 1225 { 1226 device_t root; 1227 uint32_t lnkcap, lnkcap2; 1228 int error, pos; 1229 1230 root = device_get_parent(dev->dev.bsddev); 1231 if (root == NULL) 1232 return (PCI_SPEED_UNKNOWN); 1233 root = device_get_parent(root); 1234 if (root == NULL) 1235 return (PCI_SPEED_UNKNOWN); 1236 root = device_get_parent(root); 1237 if (root == NULL) 1238 return (PCI_SPEED_UNKNOWN); 1239 1240 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1241 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1242 return (PCI_SPEED_UNKNOWN); 1243 1244 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1245 return (PCI_SPEED_UNKNOWN); 1246 1247 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1248 1249 if (lnkcap2) { /* PCIe r3.0-compliant */ 1250 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1251 return (PCIE_SPEED_2_5GT); 1252 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1253 return (PCIE_SPEED_5_0GT); 1254 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1255 return (PCIE_SPEED_8_0GT); 1256 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1257 return (PCIE_SPEED_16_0GT); 1258 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1259 return (PCIE_SPEED_32_0GT); 1260 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1261 return (PCIE_SPEED_64_0GT); 1262 } else { /* pre-r3.0 */ 1263 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1264 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1265 return (PCIE_SPEED_2_5GT); 1266 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1267 return (PCIE_SPEED_5_0GT); 1268 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1269 return (PCIE_SPEED_8_0GT); 1270 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1271 return (PCIE_SPEED_16_0GT); 1272 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1273 return (PCIE_SPEED_32_0GT); 1274 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1275 return (PCIE_SPEED_64_0GT); 1276 } 1277 return (PCI_SPEED_UNKNOWN); 1278 } 1279 1280 static inline enum pcie_link_width 1281 pcie_get_width_cap(struct pci_dev *dev) 1282 { 1283 uint32_t lnkcap; 1284 1285 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1286 if (lnkcap) 1287 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1288 1289 return (PCIE_LNK_WIDTH_UNKNOWN); 1290 } 1291 1292 static inline int 1293 pcie_get_mps(struct pci_dev *dev) 1294 { 1295 return (pci_get_max_payload(dev->dev.bsddev)); 1296 } 1297 1298 static inline uint32_t 1299 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1300 { 1301 1302 switch(spd) { 1303 case PCIE_SPEED_64_0GT: 1304 return (64000 * 128 / 130); 1305 case PCIE_SPEED_32_0GT: 1306 return (32000 * 128 / 130); 1307 case PCIE_SPEED_16_0GT: 1308 return (16000 * 128 / 130); 1309 case PCIE_SPEED_8_0GT: 1310 return (8000 * 128 / 130); 1311 case PCIE_SPEED_5_0GT: 1312 return (5000 * 8 / 10); 1313 case PCIE_SPEED_2_5GT: 1314 return (2500 * 8 / 10); 1315 default: 1316 return (0); 1317 } 1318 } 1319 1320 static inline uint32_t 1321 pcie_bandwidth_available(struct pci_dev *pdev, 1322 struct pci_dev **limiting, 1323 enum pci_bus_speed *speed, 1324 enum pcie_link_width *width) 1325 { 1326 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1327 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1328 1329 if (speed) 1330 *speed = nspeed; 1331 if (width) 1332 *width = nwidth; 1333 1334 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1335 } 1336 1337 static inline struct pci_dev * 1338 pcie_find_root_port(struct pci_dev *pdev) 1339 { 1340 device_t root; 1341 1342 if (pdev->root != NULL) 1343 return (pdev->root); 1344 1345 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1346 if (root == NULL) 1347 return (NULL); 1348 1349 pdev->root = lkpinew_pci_dev(root); 1350 return (pdev->root); 1351 } 1352 1353 /* This is needed when people rip out the device "HotPlug". */ 1354 static inline void 1355 pci_lock_rescan_remove(void) 1356 { 1357 } 1358 1359 static inline void 1360 pci_unlock_rescan_remove(void) 1361 { 1362 } 1363 1364 static __inline void 1365 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1366 { 1367 } 1368 1369 /* 1370 * The following functions can be used to attach/detach the LinuxKPI's 1371 * PCI device runtime. The pci_driver and pci_device_id pointer is 1372 * allowed to be NULL. Other pointers must be all valid. 1373 * The pci_dev structure should be zero-initialized before passed 1374 * to the linux_pci_attach_device function. 1375 */ 1376 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1377 const struct pci_device_id *, struct pci_dev *); 1378 extern int linux_pci_detach_device(struct pci_dev *); 1379 1380 static inline int 1381 pci_dev_present(const struct pci_device_id *cur) 1382 { 1383 while (cur != NULL && (cur->vendor || cur->device)) { 1384 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1385 return (1); 1386 } 1387 cur++; 1388 } 1389 return (0); 1390 } 1391 1392 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1393 unsigned int bus, unsigned int devfn); 1394 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1395 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1396 1397 static inline int 1398 pci_domain_nr(struct pci_bus *pbus) 1399 { 1400 1401 return (pbus->domain); 1402 } 1403 1404 static inline int 1405 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1406 int pos, uint32_t *val, int len) 1407 { 1408 1409 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1410 return (0); 1411 } 1412 1413 static inline int 1414 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1415 { 1416 uint32_t tmp; 1417 int ret; 1418 1419 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1420 *val = (u16)tmp; 1421 return (ret); 1422 } 1423 1424 static inline int 1425 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1426 { 1427 uint32_t tmp; 1428 int ret; 1429 1430 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1431 *val = (u8)tmp; 1432 return (ret); 1433 } 1434 1435 static inline int 1436 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1437 uint32_t val, int size) 1438 { 1439 1440 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1441 return (0); 1442 } 1443 1444 static inline int 1445 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1446 uint8_t val) 1447 { 1448 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1449 } 1450 1451 static inline int 1452 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1453 uint16_t val) 1454 { 1455 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1456 } 1457 1458 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1459 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1460 1461 /* -------------------------------------------------------------------------- */ 1462 1463 static inline int 1464 pcim_enable_device(struct pci_dev *pdev) 1465 { 1466 struct pci_devres *dr; 1467 int error; 1468 1469 /* Here we cannot run through the pdev->managed check. */ 1470 dr = lkpi_pci_devres_get_alloc(pdev); 1471 if (dr == NULL) 1472 return (-ENOMEM); 1473 1474 /* If resources were enabled before do not do it again. */ 1475 if (dr->enable_io) 1476 return (0); 1477 1478 error = pci_enable_device(pdev); 1479 if (error == 0) 1480 dr->enable_io = true; 1481 1482 /* This device is not managed. */ 1483 pdev->managed = true; 1484 1485 return (error); 1486 } 1487 1488 static inline void __iomem ** 1489 pcim_iomap_table(struct pci_dev *pdev) 1490 { 1491 struct pcim_iomap_devres *dr; 1492 1493 dr = lkpi_pcim_iomap_devres_find(pdev); 1494 if (dr == NULL) 1495 return (NULL); 1496 1497 /* 1498 * If the driver has manually set a flag to be able to request the 1499 * resource to use bus_read/write_<n>, return the shadow table. 1500 */ 1501 if (pdev->want_iomap_res) 1502 return ((void **)dr->res_table); 1503 1504 /* This is the Linux default. */ 1505 return (dr->mmio_table); 1506 } 1507 1508 static inline int 1509 pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, const char *name) 1510 { 1511 struct pcim_iomap_devres *dr; 1512 void *res; 1513 uint32_t mappings; 1514 int bar; 1515 1516 dr = lkpi_pcim_iomap_devres_find(pdev); 1517 if (dr == NULL) 1518 return (-ENOMEM); 1519 1520 /* Now iomap all the requested (by "mask") ones. */ 1521 for (bar = mappings = 0; mappings != mask; bar++) { 1522 if ((mask & (1 << bar)) == 0) 1523 continue; 1524 1525 /* Request double is not allowed. */ 1526 if (dr->mmio_table[bar] != NULL) { 1527 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1528 __func__, bar, dr->mmio_table[bar]); 1529 goto err; 1530 } 1531 1532 res = _lkpi_pci_iomap(pdev, bar, 0); 1533 if (res == NULL) 1534 goto err; 1535 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1536 dr->res_table[bar] = res; 1537 1538 mappings |= (1 << bar); 1539 } 1540 1541 return (0); 1542 err: 1543 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1544 if ((mappings & (1 << bar)) != 0) { 1545 res = dr->mmio_table[bar]; 1546 if (res == NULL) 1547 continue; 1548 pci_iounmap(pdev, res); 1549 } 1550 } 1551 1552 return (-EINVAL); 1553 } 1554 1555 static inline int 1556 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1557 { 1558 uint32_t requests, req_mask; 1559 int bar, error; 1560 1561 /* Request all the BARs ("regions") we do not iomap. */ 1562 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1563 for (bar = requests = 0; requests != req_mask; bar++) { 1564 if ((req_mask & (1 << bar)) == 0) 1565 continue; 1566 error = pci_request_region(pdev, bar, name); 1567 if (error != 0 && error != -ENODEV) 1568 goto err; 1569 requests |= (1 << bar); 1570 } 1571 1572 error = pcim_iomap_regions(pdev, mask, name); 1573 if (error != 0) 1574 goto err; 1575 1576 return (0); 1577 1578 err: 1579 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1580 if ((requests & (1 << bar)) != 0) 1581 pci_release_region(pdev, bar); 1582 } 1583 1584 return (-EINVAL); 1585 } 1586 1587 /* This is a FreeBSD extension so we can use bus_*(). */ 1588 static inline void 1589 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1590 { 1591 pdev->want_iomap_res = true; 1592 } 1593 1594 static inline bool 1595 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1596 { 1597 1598 return (false); 1599 } 1600 1601 static inline void * 1602 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1603 { 1604 1605 return (NULL); 1606 } 1607 1608 static inline void 1609 pci_ignore_hotplug(struct pci_dev *pdev) 1610 { 1611 } 1612 1613 static inline const char * 1614 pci_power_name(pci_power_t state) 1615 { 1616 int pstate = state + 1; 1617 1618 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1619 return (pci_power_names[pstate]); 1620 else 1621 return (pci_power_names[0]); 1622 } 1623 1624 static inline int 1625 pcie_get_readrq(struct pci_dev *dev) 1626 { 1627 u16 ctl; 1628 1629 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1630 return (-EINVAL); 1631 1632 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1633 } 1634 1635 static inline bool 1636 pci_is_enabled(struct pci_dev *pdev) 1637 { 1638 1639 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1640 PCIM_CMD_BUSMASTEREN) != 0); 1641 } 1642 1643 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1644