1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2025 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 #include <linux/device/driver.h> 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_private.h> 49 50 #include <machine/resource.h> 51 52 #include <linux/list.h> 53 #include <linux/dmapool.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/compiler.h> 56 #include <linux/errno.h> 57 #include <asm/atomic.h> 58 #include <asm/memtype.h> 59 #include <linux/device.h> 60 #include <linux/pci_ids.h> 61 #include <linux/pm.h> 62 #include <linux/interrupt.h> 63 64 /* 65 * <linux/ioport.h> should be included here, like Linux, but we can't have that 66 * because Linux `struct resource` definition would conflict with FreeBSD 67 * native definition. 68 * 69 * At least the amdgpu DRM driver (amdgpu_isp.c at the time of this writing) 70 * relies on this indirect include to get the definition of Linux `struct 71 * resource`. As a workaround, we include <linux/ioport.h> from 72 * <linux/mfd/core.h>. 73 */ 74 75 #include <linux/kernel.h> /* pr_debug */ 76 77 struct pci_device_id { 78 uint32_t vendor; 79 uint32_t device; 80 uint32_t subvendor; 81 uint32_t subdevice; 82 uint32_t class; 83 uint32_t class_mask; 84 uintptr_t driver_data; 85 }; 86 87 #define MODULE_DEVICE_TABLE_BUS_pci(_bus, _table) \ 88 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 89 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 90 91 #define PCI_ANY_ID -1U 92 93 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 94 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 95 #define PCI_FUNC(devfn) ((devfn) & 0x07) 96 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 97 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 98 99 #define PCI_VDEVICE(_vendor, _device) \ 100 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 101 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 102 .class = 0, .class_mask = 0 103 #define PCI_DEVICE(_vendor, _device) \ 104 .vendor = (_vendor), .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 107 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 108 109 #define PCI_STD_NUM_BARS 6 110 #define PCI_BASE_ADDRESS_0 PCIR_BARS 111 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 112 #define PCI_VENDOR_ID PCIR_VENDOR 113 #define PCI_DEVICE_ID PCIR_DEVICE 114 #define PCI_COMMAND PCIR_COMMAND 115 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 116 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 117 #define PCI_PRIMARY_BUS PCIR_PRIBUS_1 118 #define PCI_SECONDARY_BUS PCIR_SECBUS_1 119 #define PCI_SUBORDINATE_BUS PCIR_SUBBUS_1 120 #define PCI_SEC_LATENCY_TIMER PCIR_SECLAT_1 121 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 122 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 123 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 124 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 125 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 126 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 127 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 128 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 129 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 130 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 131 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 132 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 133 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 134 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 135 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 136 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 137 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 138 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 139 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 140 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 141 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 142 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 143 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 144 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 145 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 146 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 147 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 148 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 149 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 150 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 151 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 152 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 153 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 154 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 155 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 156 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 157 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 158 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 159 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 160 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 161 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 162 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 163 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 164 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 165 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 166 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 167 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 168 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 169 #define PCI_EXP_LNKCTL2_TLS 0x000f 170 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 171 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 172 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 173 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 174 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 175 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 176 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 177 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 178 179 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 180 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 181 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 182 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 183 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 184 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 185 186 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 187 #define PCI_EXP_DEVSTA_TRPND 0x0020 188 189 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 190 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 191 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 192 193 enum pci_bus_speed { 194 PCI_SPEED_UNKNOWN = -1, 195 PCIE_SPEED_2_5GT, 196 PCIE_SPEED_5_0GT, 197 PCIE_SPEED_8_0GT, 198 PCIE_SPEED_16_0GT, 199 PCIE_SPEED_32_0GT, 200 PCIE_SPEED_64_0GT, 201 }; 202 203 enum pcie_link_width { 204 PCIE_LNK_WIDTH_RESRV = 0x00, 205 PCIE_LNK_X1 = 0x01, 206 PCIE_LNK_X2 = 0x02, 207 PCIE_LNK_X4 = 0x04, 208 PCIE_LNK_X8 = 0x08, 209 PCIE_LNK_X12 = 0x0c, 210 PCIE_LNK_X16 = 0x10, 211 PCIE_LNK_X32 = 0x20, 212 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 213 }; 214 215 #define PCIE_LINK_STATE_L0S 0x00000001 216 #define PCIE_LINK_STATE_L1 0x00000002 217 #define PCIE_LINK_STATE_CLKPM 0x00000004 218 219 typedef int pci_power_t; 220 221 #define PCI_D0 PCI_POWERSTATE_D0 222 #define PCI_D1 PCI_POWERSTATE_D1 223 #define PCI_D2 PCI_POWERSTATE_D2 224 #define PCI_D3hot PCI_POWERSTATE_D3_HOT 225 #define PCI_D3cold PCI_POWERSTATE_D3_COLD 226 227 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 228 229 extern const char *pci_power_names[6]; 230 231 #define PCI_ERR_UNCOR_STATUS PCIR_AER_UC_STATUS 232 #define PCI_ERR_COR_STATUS PCIR_AER_COR_STATUS 233 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 234 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 235 236 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 237 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 238 239 #define PCI_L1SS_CTL1 0x8 240 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 241 242 #define PCI_IRQ_INTX 0x01 243 #define PCI_IRQ_MSI 0x02 244 #define PCI_IRQ_MSIX 0x04 245 #define PCI_IRQ_AFFINITY 0x08 246 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_INTX) 247 248 #if defined(LINUXKPI_VERSION) && (LINUXKPI_VERSION <= 61000) 249 #define PCI_IRQ_LEGACY PCI_IRQ_INTX 250 #endif 251 252 /* 253 * Linux PCI code uses `PCI_SET_ERROR_RESPONSE()` to indicate to the caller of 254 * a `pci_read_*()` function that the read failed. An example of failure is 255 * whether the device was disconnected. It is a bit weird because Linux 256 * `pci_read_*()` can return an error value, as the read value is stored in a 257 * integer passed by pointer. 258 * 259 * We don't set PCI_ERROR_RESPONSE anywhere as of this commit, but the DRM 260 * drivers started to use `PCI_POSSIBLE_ERROR()`. 261 */ 262 #define PCI_ERROR_RESPONSE (~0ULL) 263 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 264 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 265 266 struct pci_dev; 267 268 struct pci_driver { 269 struct list_head node; 270 char *name; 271 const struct pci_device_id *id_table; 272 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 273 void (*remove)(struct pci_dev *dev); 274 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 275 int (*resume) (struct pci_dev *dev); /* Device woken up */ 276 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 277 driver_t bsddriver; 278 devclass_t bsdclass; 279 struct device_driver driver; 280 const struct pci_error_handlers *err_handler; 281 bool isdrm; 282 int bsd_probe_return; 283 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 284 const nvlist_t *pf_config); 285 void (*bsd_iov_uninit)(device_t dev); 286 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 287 const nvlist_t *vf_config); 288 }; 289 290 struct pci_bus { 291 struct pci_dev *self; 292 /* struct pci_bus *parent */ 293 int domain; 294 int number; 295 }; 296 297 extern struct list_head pci_drivers; 298 extern struct list_head pci_devices; 299 extern spinlock_t pci_lock; 300 301 #define __devexit_p(x) x 302 303 #define module_pci_driver(_drv) \ 304 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver) 305 306 struct msi_msg { 307 uint32_t data; 308 }; 309 310 struct pci_msi_desc { 311 struct { 312 bool is_64; 313 } msi_attrib; 314 }; 315 316 struct msi_desc { 317 struct msi_msg msg; 318 struct pci_msi_desc pci; 319 }; 320 321 struct msix_entry { 322 int entry; 323 int vector; 324 }; 325 326 /* 327 * If we find drivers accessing this from multiple KPIs we may have to 328 * refcount objects of this structure. 329 */ 330 struct resource; 331 struct pci_mmio_region { 332 TAILQ_ENTRY(pci_mmio_region) next; 333 struct resource *res; 334 int rid; 335 int type; 336 }; 337 338 struct pci_dev { 339 struct device dev; 340 struct list_head links; 341 struct pci_driver *pdrv; 342 struct pci_bus *bus; 343 struct pci_dev *root; 344 pci_power_t current_state; 345 uint16_t device; 346 uint16_t vendor; 347 uint16_t subsystem_vendor; 348 uint16_t subsystem_device; 349 unsigned int irq; 350 unsigned int devfn; 351 uint32_t class; 352 uint8_t revision; 353 uint8_t msi_cap; 354 uint8_t msix_cap; 355 bool managed; /* devres "pcim_*(). */ 356 bool want_iomap_res; 357 bool msi_enabled; 358 bool msix_enabled; 359 phys_addr_t rom; 360 size_t romlen; 361 struct msi_desc **msi_desc; 362 char *path_name; 363 spinlock_t pcie_cap_lock; 364 365 TAILQ_HEAD(, pci_mmio_region) mmio; 366 }; 367 368 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 369 unsigned int flags); 370 bool pci_device_is_present(struct pci_dev *pdev); 371 372 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 373 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 374 void *linuxkpi_pci_iomap_range(struct pci_dev *, int, 375 unsigned long, unsigned long); 376 void *linuxkpi_pci_iomap(struct pci_dev *, int, unsigned long); 377 void *linuxkpi_pcim_iomap(struct pci_dev *, int, unsigned long); 378 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 379 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 380 const char *name); 381 int linuxkpi_pci_request_region(struct pci_dev *, int, const char *); 382 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 383 int linuxkpi_pcim_request_all_regions(struct pci_dev *, const char *); 384 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 385 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 386 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 387 int nreq); 388 389 /* Internal helper function(s). */ 390 struct pci_dev *lkpinew_pci_dev(device_t); 391 void lkpi_pci_devres_release(struct device *, void *); 392 struct pci_dev *lkpi_pci_get_device(uint32_t, uint32_t, struct pci_dev *); 393 struct msi_desc *lkpi_pci_msi_desc_alloc(unsigned int); 394 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 395 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 396 397 #define pci_err(pdev, fmt, ...) \ 398 dev_err(&(pdev)->dev, fmt, ##__VA_ARGS__) 399 #define pci_info(pdev, fmt, ...) \ 400 dev_info(&(pdev)->dev, fmt, ##__VA_ARGS__) 401 402 static inline bool 403 dev_is_pci(struct device *dev) 404 { 405 return (is_pci_device(dev->bsddev)); 406 } 407 408 static inline uint16_t 409 pci_dev_id(struct pci_dev *pdev) 410 { 411 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 412 } 413 414 static inline int 415 pci_resource_type(struct pci_dev *pdev, int bar) 416 { 417 struct pci_map *pm; 418 419 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 420 if (!pm) 421 return (-1); 422 423 if (PCI_BAR_IO(pm->pm_value)) 424 return (SYS_RES_IOPORT); 425 else 426 return (SYS_RES_MEMORY); 427 } 428 429 /* 430 * All drivers just seem to want to inspect the type not flags. 431 */ 432 static inline int 433 pci_resource_flags(struct pci_dev *pdev, int bar) 434 { 435 int type; 436 437 type = pci_resource_type(pdev, bar); 438 if (type < 0) 439 return (0); 440 return (1 << type); 441 } 442 443 static inline int 444 pci_select_bars(struct pci_dev *pdev, unsigned long flags) 445 { 446 int bars, bar; 447 448 bars = 0; 449 /* We only support BARs here; Linux may support more types. */ 450 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 451 int bar_flags; 452 453 bar_flags = pci_resource_flags(pdev, bar); 454 if ((bar_flags & flags) != 0) 455 bars |= (1 << bar); 456 } 457 458 return (bars); 459 } 460 461 static inline const char * 462 pci_name(struct pci_dev *d) 463 { 464 return d->path_name; 465 } 466 467 static inline void * 468 pci_get_drvdata(struct pci_dev *pdev) 469 { 470 471 return dev_get_drvdata(&pdev->dev); 472 } 473 474 static inline void 475 pci_set_drvdata(struct pci_dev *pdev, void *data) 476 { 477 478 dev_set_drvdata(&pdev->dev, data); 479 } 480 481 static inline struct pci_dev * 482 pci_dev_get(struct pci_dev *pdev) 483 { 484 485 if (pdev != NULL) 486 get_device(&pdev->dev); 487 return (pdev); 488 } 489 490 static __inline void 491 pci_dev_put(struct pci_dev *pdev) 492 { 493 494 if (pdev != NULL) 495 put_device(&pdev->dev); 496 } 497 498 static inline int 499 pci_enable_device(struct pci_dev *pdev) 500 { 501 502 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 503 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 504 return (0); 505 } 506 507 static inline void 508 pci_disable_device(struct pci_dev *pdev) 509 { 510 511 pci_disable_busmaster(pdev->dev.bsddev); 512 } 513 514 static inline int 515 pci_set_master(struct pci_dev *pdev) 516 { 517 518 pci_enable_busmaster(pdev->dev.bsddev); 519 return (0); 520 } 521 522 static inline int 523 pci_set_power_state(struct pci_dev *pdev, int state) 524 { 525 526 pci_set_powerstate(pdev->dev.bsddev, state); 527 return (0); 528 } 529 530 static inline int 531 pci_clear_master(struct pci_dev *pdev) 532 { 533 534 pci_disable_busmaster(pdev->dev.bsddev); 535 return (0); 536 } 537 538 static inline bool 539 pci_is_root_bus(struct pci_bus *pbus) 540 { 541 542 return (pbus->self == NULL); 543 } 544 545 static inline struct pci_dev * 546 pci_upstream_bridge(struct pci_dev *pdev) 547 { 548 549 if (pci_is_root_bus(pdev->bus)) 550 return (NULL); 551 552 /* 553 * If we do not have a (proper) "upstream bridge" set, e.g., we point 554 * to ourselves, try to handle this case on the fly like we do 555 * for pcie_find_root_port(). 556 */ 557 if (pdev == pdev->bus->self) { 558 device_t bridge; 559 560 /* 561 * In the case of DRM drivers, the passed device is a child of 562 * `vgapci`. We want to start the lookup from `vgapci`, so the 563 * parent of the passed `drmn`. 564 * 565 * We can use the `isdrm` flag to determine this. 566 */ 567 bridge = pdev->dev.bsddev; 568 if (pdev->pdrv != NULL && pdev->pdrv->isdrm) 569 bridge = device_get_parent(bridge); 570 if (bridge == NULL) 571 goto done; 572 573 bridge = device_get_parent(bridge); 574 if (bridge == NULL) 575 goto done; 576 bridge = device_get_parent(bridge); 577 if (bridge == NULL) 578 goto done; 579 if (!is_pci_device(bridge)) 580 goto done; 581 582 /* 583 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 584 * for it so it can be returned. 585 */ 586 pdev->bus->self = lkpinew_pci_dev(bridge); 587 } 588 done: 589 return (pdev->bus->self); 590 } 591 592 #define pci_request_region(pdev, bar, res_name) \ 593 linuxkpi_pci_request_region(pdev, bar, res_name) 594 #define pci_release_region(pdev, bar) \ 595 linuxkpi_pci_release_region(pdev, bar) 596 #define pci_request_regions(pdev, res_name) \ 597 linuxkpi_pci_request_regions(pdev, res_name) 598 #define pci_release_regions(pdev) \ 599 linuxkpi_pci_release_regions(pdev) 600 #define pcim_request_all_regions(pdev, name) \ 601 linuxkpi_pcim_request_all_regions(pdev, name) 602 603 static inline void 604 lkpi_pci_disable_msix(struct pci_dev *pdev) 605 { 606 607 pci_release_msi(pdev->dev.bsddev); 608 609 /* 610 * The MSIX IRQ numbers associated with this PCI device are no 611 * longer valid and might be re-assigned. Make sure 612 * lkpi_pci_find_irq_dev() does no longer see them by 613 * resetting their references to zero: 614 */ 615 pdev->dev.irq_start = 0; 616 pdev->dev.irq_end = 0; 617 pdev->msix_enabled = false; 618 } 619 /* Only for consistency. No conflict on that one. */ 620 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 621 622 static inline void 623 lkpi_pci_disable_msi(struct pci_dev *pdev) 624 { 625 626 pci_release_msi(pdev->dev.bsddev); 627 628 pdev->dev.irq_start = 0; 629 pdev->dev.irq_end = 0; 630 pdev->irq = pdev->dev.irq; 631 pdev->msi_enabled = false; 632 } 633 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 634 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 635 636 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 637 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 638 639 static inline bus_addr_t 640 pci_bus_address(struct pci_dev *pdev, int bar) 641 { 642 643 return (pci_resource_start(pdev, bar)); 644 } 645 646 #define PCI_CAP_ID_EXP PCIY_EXPRESS 647 #define PCI_CAP_ID_PCIX PCIY_PCIX 648 #define PCI_CAP_ID_AGP PCIY_AGP 649 #define PCI_CAP_ID_PM PCIY_PMG 650 651 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 652 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 653 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 654 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 655 #define PCI_EXP_LNKSTA PCIER_LINK_STA 656 657 static inline int 658 pci_find_capability(struct pci_dev *pdev, int capid) 659 { 660 int reg; 661 662 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 663 return (0); 664 return (reg); 665 } 666 667 static inline int pci_pcie_cap(struct pci_dev *dev) 668 { 669 return pci_find_capability(dev, PCI_CAP_ID_EXP); 670 } 671 672 static inline int 673 pci_find_ext_capability(struct pci_dev *pdev, int capid) 674 { 675 int reg; 676 677 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 678 return (0); 679 return (reg); 680 } 681 682 static __inline bool 683 pci_pme_capable(struct pci_dev *pdev, pci_power_t state) 684 { 685 return (pci_has_pme(pdev->dev.bsddev, state)); 686 } 687 688 static inline int 689 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 690 { 691 692 if (!pci_enable_aspm) 693 return (-EPERM); 694 695 return (-ENXIO); 696 } 697 698 static inline int 699 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 700 { 701 702 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 703 return (0); 704 } 705 706 static inline int 707 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 708 { 709 710 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 711 return (0); 712 } 713 714 static inline int 715 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 716 { 717 718 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 719 return (0); 720 } 721 722 static inline int 723 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 724 { 725 726 pci_write_config(pdev->dev.bsddev, where, val, 1); 727 return (0); 728 } 729 730 static inline int 731 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 732 { 733 734 pci_write_config(pdev->dev.bsddev, where, val, 2); 735 return (0); 736 } 737 738 static inline int 739 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 740 { 741 742 pci_write_config(pdev->dev.bsddev, where, val, 4); 743 return (0); 744 } 745 746 int linux_pci_register_driver(struct pci_driver *pdrv); 747 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 748 void linux_pci_unregister_driver(struct pci_driver *pdrv); 749 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 750 751 #define pci_register_driver(pdrv) \ 752 linux_pci_register_driver(pdrv) 753 #define pci_unregister_driver(pdrv) \ 754 linux_pci_unregister_driver(pdrv) 755 756 /* 757 * Enable msix, positive errors indicate actual number of available 758 * vectors. Negative errors are failures. 759 * 760 * NB: define added to prevent this definition of pci_enable_msix from 761 * clashing with the native FreeBSD version. 762 */ 763 #define pci_enable_msix(...) \ 764 linuxkpi_pci_enable_msix(__VA_ARGS__) 765 766 #define pci_enable_msix_range(...) \ 767 linux_pci_enable_msix_range(__VA_ARGS__) 768 769 static inline int 770 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 771 int minvec, int maxvec) 772 { 773 int nvec = maxvec; 774 int rc; 775 776 if (maxvec < minvec) 777 return (-ERANGE); 778 779 do { 780 rc = pci_enable_msix(dev, entries, nvec); 781 if (rc < 0) { 782 return (rc); 783 } else if (rc > 0) { 784 if (rc < minvec) 785 return (-ENOSPC); 786 nvec = rc; 787 } 788 } while (rc); 789 return (nvec); 790 } 791 792 #define pci_enable_msi(pdev) \ 793 linux_pci_enable_msi(pdev) 794 795 static inline int 796 pci_enable_msi(struct pci_dev *pdev) 797 { 798 799 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 800 } 801 802 static inline int 803 pci_channel_offline(struct pci_dev *pdev) 804 { 805 806 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 807 } 808 809 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 810 { 811 return -ENODEV; 812 } 813 814 static inline void pci_disable_sriov(struct pci_dev *dev) 815 { 816 } 817 818 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \ 819 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) 820 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 821 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 822 #define pcim_iomap(pdev, bar, maxlen) \ 823 linuxkpi_pcim_iomap(pdev, bar, maxlen) 824 #define pci_iounmap(pdev, res) \ 825 linuxkpi_pci_iounmap(pdev, res) 826 827 static inline void 828 lkpi_pci_save_state(struct pci_dev *pdev) 829 { 830 831 pci_save_state(pdev->dev.bsddev); 832 } 833 834 static inline void 835 lkpi_pci_restore_state(struct pci_dev *pdev) 836 { 837 838 pci_restore_state(pdev->dev.bsddev); 839 } 840 841 #define pci_save_state(dev) lkpi_pci_save_state(dev) 842 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 843 844 static inline int 845 linuxkpi_pci_enable_wake(struct pci_dev *pdev, pci_power_t state, bool ena) 846 { 847 /* 848 * We do not currently support this in device.h either to 849 * check if the device is allowed to wake up in first place. 850 */ 851 pr_debug("%s: TODO\n", __func__); 852 return (0); 853 } 854 #define pci_enable_wake(dev, state, ena) \ 855 linuxkpi_pci_enable_wake(dev, state, ena) 856 857 static inline int 858 pci_reset_function(struct pci_dev *pdev) 859 { 860 861 return (-ENOSYS); 862 } 863 864 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 865 const struct pci_device_id _table[] __devinitdata 866 867 /* XXX This should not be necessary. */ 868 #define pcix_set_mmrbc(d, v) 0 869 #define pcix_get_max_mmrbc(d) 0 870 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 871 872 #define PCI_DMA_BIDIRECTIONAL 0 873 #define PCI_DMA_TODEVICE 1 874 #define PCI_DMA_FROMDEVICE 2 875 #define PCI_DMA_NONE 3 876 877 #define pci_pool dma_pool 878 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 879 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 880 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 881 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 882 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 883 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 884 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 885 _size, _vaddr, _dma_handle) 886 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 887 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 888 _sg, _nents, (enum dma_data_direction)_dir) 889 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 890 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 891 (_ptr), (_size), (enum dma_data_direction)_dir) 892 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 893 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 894 _addr, _size, (enum dma_data_direction)_dir) 895 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 896 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 897 _sg, _nents, (enum dma_data_direction)_dir) 898 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 899 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 900 _offset, _size, (enum dma_data_direction)_dir) 901 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 902 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 903 _dma_address, _size, (enum dma_data_direction)_dir) 904 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 905 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 906 dma_mapping_error(&(_pdev)->dev, _dma_addr) 907 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 908 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 909 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 910 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 911 #define pci_unmap_addr dma_unmap_addr 912 #define pci_unmap_addr_set dma_unmap_addr_set 913 #define pci_unmap_len dma_unmap_len 914 #define pci_unmap_len_set dma_unmap_len_set 915 916 void *linuxkpi_pci_map_rom(struct pci_dev *pdev, size_t *size); 917 void linuxkpi_pci_unmap_rom(struct pci_dev *pdev, void *rom); 918 #define pci_map_rom(pdev, size) linuxkpi_pci_map_rom(pdev, size) 919 #define pci_unmap_rom(pdev, rom) linuxkpi_pci_unmap_rom(pdev, rom) 920 921 typedef unsigned int __bitwise pci_channel_state_t; 922 typedef unsigned int __bitwise pci_ers_result_t; 923 924 enum pci_channel_state { 925 pci_channel_io_normal = 1, 926 pci_channel_io_frozen = 2, 927 pci_channel_io_perm_failure = 3, 928 }; 929 930 enum pci_ers_result { 931 PCI_ERS_RESULT_NONE = 1, 932 PCI_ERS_RESULT_CAN_RECOVER = 2, 933 PCI_ERS_RESULT_NEED_RESET = 3, 934 PCI_ERS_RESULT_DISCONNECT = 4, 935 PCI_ERS_RESULT_RECOVERED = 5, 936 }; 937 938 /* PCI bus error event callbacks */ 939 struct pci_error_handlers { 940 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 941 enum pci_channel_state error); 942 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 943 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 944 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 945 void (*resume)(struct pci_dev *dev); 946 void (*reset_prepare)(struct pci_dev *); 947 void (*reset_done)(struct pci_dev *); 948 }; 949 950 /* FreeBSD does not support SRIOV - yet */ 951 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 952 { 953 return dev; 954 } 955 956 static inline bool pci_is_pcie(struct pci_dev *dev) 957 { 958 return !!pci_pcie_cap(dev); 959 } 960 961 static inline u16 pcie_flags_reg(struct pci_dev *dev) 962 { 963 int pos; 964 u16 reg16; 965 966 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 967 if (!pos) 968 return 0; 969 970 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 971 972 return reg16; 973 } 974 975 static inline int pci_pcie_type(struct pci_dev *dev) 976 { 977 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 978 } 979 980 static inline int pcie_cap_version(struct pci_dev *dev) 981 { 982 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 983 } 984 985 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 986 { 987 int type = pci_pcie_type(dev); 988 989 return pcie_cap_version(dev) > 1 || 990 type == PCI_EXP_TYPE_ROOT_PORT || 991 type == PCI_EXP_TYPE_ENDPOINT || 992 type == PCI_EXP_TYPE_LEG_END; 993 } 994 995 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 996 { 997 return true; 998 } 999 1000 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1001 { 1002 int type = pci_pcie_type(dev); 1003 1004 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1005 (type == PCI_EXP_TYPE_DOWNSTREAM && 1006 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1007 } 1008 1009 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1010 { 1011 int type = pci_pcie_type(dev); 1012 1013 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1014 type == PCI_EXP_TYPE_RC_EC; 1015 } 1016 1017 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1018 { 1019 if (!pci_is_pcie(dev)) 1020 return false; 1021 1022 switch (pos) { 1023 case PCI_EXP_FLAGS_TYPE: 1024 return true; 1025 case PCI_EXP_DEVCAP: 1026 case PCI_EXP_DEVCTL: 1027 case PCI_EXP_DEVSTA: 1028 return pcie_cap_has_devctl(dev); 1029 case PCI_EXP_LNKCAP: 1030 case PCI_EXP_LNKCTL: 1031 case PCI_EXP_LNKSTA: 1032 return pcie_cap_has_lnkctl(dev); 1033 case PCI_EXP_SLTCAP: 1034 case PCI_EXP_SLTCTL: 1035 case PCI_EXP_SLTSTA: 1036 return pcie_cap_has_sltctl(dev); 1037 case PCI_EXP_RTCTL: 1038 case PCI_EXP_RTCAP: 1039 case PCI_EXP_RTSTA: 1040 return pcie_cap_has_rtctl(dev); 1041 case PCI_EXP_DEVCAP2: 1042 case PCI_EXP_DEVCTL2: 1043 case PCI_EXP_LNKCAP2: 1044 case PCI_EXP_LNKCTL2: 1045 case PCI_EXP_LNKSTA2: 1046 return pcie_cap_version(dev) > 1; 1047 default: 1048 return false; 1049 } 1050 } 1051 1052 static inline int 1053 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1054 { 1055 *dst = 0; 1056 if (pos & 3) 1057 return -EINVAL; 1058 1059 if (!pcie_capability_reg_implemented(dev, pos)) 1060 return -EINVAL; 1061 1062 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1063 } 1064 1065 static inline int 1066 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1067 { 1068 *dst = 0; 1069 if (pos & 3) 1070 return -EINVAL; 1071 1072 if (!pcie_capability_reg_implemented(dev, pos)) 1073 return -EINVAL; 1074 1075 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1076 } 1077 1078 static inline int 1079 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1080 { 1081 if (pos & 1) 1082 return -EINVAL; 1083 1084 if (!pcie_capability_reg_implemented(dev, pos)) 1085 return 0; 1086 1087 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1088 } 1089 1090 static inline int 1091 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1092 uint16_t clear, uint16_t set) 1093 { 1094 int error; 1095 uint16_t v; 1096 1097 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1098 spin_lock(&dev->pcie_cap_lock); 1099 1100 error = pcie_capability_read_word(dev, pos, &v); 1101 if (error == 0) { 1102 v &= ~clear; 1103 v |= set; 1104 error = pcie_capability_write_word(dev, pos, v); 1105 } 1106 1107 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1108 spin_unlock(&dev->pcie_cap_lock); 1109 1110 return (error); 1111 } 1112 1113 static inline int 1114 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1115 { 1116 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1117 } 1118 1119 static inline int 1120 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1121 { 1122 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1123 } 1124 1125 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1126 enum pci_bus_speed *speed, enum pcie_link_width *width) 1127 { 1128 *speed = PCI_SPEED_UNKNOWN; 1129 *width = PCIE_LNK_WIDTH_UNKNOWN; 1130 return (0); 1131 } 1132 1133 static inline int 1134 pci_num_vf(struct pci_dev *dev) 1135 { 1136 return (0); 1137 } 1138 1139 static inline enum pci_bus_speed 1140 pcie_get_speed_cap(struct pci_dev *dev) 1141 { 1142 struct pci_dev *pbus; 1143 device_t root; 1144 uint32_t lnkcap, lnkcap2; 1145 int error, pos; 1146 1147 /* 1148 * We should always be called on a PCI device. 1149 * The only current consumer I could find was amdgpu which either 1150 * calls us directly on a pdev(drmn?) or with the result of 1151 * pci_upstream_bridge(). 1152 * 1153 * Treat "drmn" as special again as it is not a PCI device. 1154 */ 1155 if (dev->pdrv != NULL && dev->pdrv->isdrm) { 1156 pbus = pci_upstream_bridge(dev); 1157 if (pbus == NULL) 1158 return (PCI_SPEED_UNKNOWN); 1159 } else 1160 pbus = dev; 1161 1162 /* "root" may be misleading as it may not be that. */ 1163 root = pbus->dev.bsddev; 1164 1165 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1166 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1167 return (PCI_SPEED_UNKNOWN); 1168 1169 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1170 return (PCI_SPEED_UNKNOWN); 1171 1172 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1173 1174 if (lnkcap2) { /* PCIe r3.0-compliant */ 1175 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1176 return (PCIE_SPEED_2_5GT); 1177 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1178 return (PCIE_SPEED_5_0GT); 1179 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1180 return (PCIE_SPEED_8_0GT); 1181 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1182 return (PCIE_SPEED_16_0GT); 1183 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1184 return (PCIE_SPEED_32_0GT); 1185 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1186 return (PCIE_SPEED_64_0GT); 1187 } else { /* pre-r3.0 */ 1188 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1189 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1190 return (PCIE_SPEED_2_5GT); 1191 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1192 return (PCIE_SPEED_5_0GT); 1193 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1194 return (PCIE_SPEED_8_0GT); 1195 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1196 return (PCIE_SPEED_16_0GT); 1197 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1198 return (PCIE_SPEED_32_0GT); 1199 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1200 return (PCIE_SPEED_64_0GT); 1201 } 1202 return (PCI_SPEED_UNKNOWN); 1203 } 1204 1205 static inline enum pcie_link_width 1206 pcie_get_width_cap(struct pci_dev *dev) 1207 { 1208 uint32_t lnkcap; 1209 1210 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1211 if (lnkcap) 1212 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1213 1214 return (PCIE_LNK_WIDTH_UNKNOWN); 1215 } 1216 1217 static inline int 1218 pcie_get_mps(struct pci_dev *dev) 1219 { 1220 return (pci_get_max_payload(dev->dev.bsddev)); 1221 } 1222 1223 static inline uint32_t 1224 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1225 { 1226 1227 switch(spd) { 1228 case PCIE_SPEED_64_0GT: 1229 return (64000 * 128 / 130); 1230 case PCIE_SPEED_32_0GT: 1231 return (32000 * 128 / 130); 1232 case PCIE_SPEED_16_0GT: 1233 return (16000 * 128 / 130); 1234 case PCIE_SPEED_8_0GT: 1235 return (8000 * 128 / 130); 1236 case PCIE_SPEED_5_0GT: 1237 return (5000 * 8 / 10); 1238 case PCIE_SPEED_2_5GT: 1239 return (2500 * 8 / 10); 1240 default: 1241 return (0); 1242 } 1243 } 1244 1245 static inline uint32_t 1246 pcie_bandwidth_available(struct pci_dev *pdev, 1247 struct pci_dev **limiting, 1248 enum pci_bus_speed *speed, 1249 enum pcie_link_width *width) 1250 { 1251 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1252 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1253 1254 if (speed) 1255 *speed = nspeed; 1256 if (width) 1257 *width = nwidth; 1258 1259 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1260 } 1261 1262 static inline bool 1263 pcie_aspm_enabled(struct pci_dev *pdev) 1264 { 1265 return (false); 1266 } 1267 1268 static inline struct pci_dev * 1269 pcie_find_root_port(struct pci_dev *pdev) 1270 { 1271 device_t root; 1272 1273 if (pdev->root != NULL) 1274 return (pdev->root); 1275 1276 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1277 if (root == NULL) 1278 return (NULL); 1279 1280 pdev->root = lkpinew_pci_dev(root); 1281 return (pdev->root); 1282 } 1283 1284 /* This is needed when people rip out the device "HotPlug". */ 1285 static inline void 1286 pci_lock_rescan_remove(void) 1287 { 1288 } 1289 1290 static inline void 1291 pci_unlock_rescan_remove(void) 1292 { 1293 } 1294 1295 static __inline void 1296 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1297 { 1298 } 1299 1300 static inline int 1301 pci_rescan_bus(struct pci_bus *pbus) 1302 { 1303 device_t *devlist, parent; 1304 int devcount, error; 1305 1306 if (!device_is_attached(pbus->self->dev.bsddev)) 1307 return (0); 1308 /* pci_rescan_method() will work on the pcib (parent). */ 1309 error = BUS_RESCAN(pbus->self->dev.bsddev); 1310 if (error != 0) 1311 return (0); 1312 1313 parent = device_get_parent(pbus->self->dev.bsddev); 1314 error = device_get_children(parent, &devlist, &devcount); 1315 if (error != 0) 1316 return (0); 1317 if (devcount != 0) 1318 free(devlist, M_TEMP); 1319 1320 return (devcount); 1321 } 1322 1323 /* 1324 * The following functions can be used to attach/detach the LinuxKPI's 1325 * PCI device runtime. The pci_driver and pci_device_id pointer is 1326 * allowed to be NULL. Other pointers must be all valid. 1327 * The pci_dev structure should be zero-initialized before passed 1328 * to the linux_pci_attach_device function. 1329 */ 1330 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1331 const struct pci_device_id *, struct pci_dev *); 1332 extern int linux_pci_detach_device(struct pci_dev *); 1333 1334 static inline int 1335 pci_dev_present(const struct pci_device_id *cur) 1336 { 1337 while (cur != NULL && (cur->vendor || cur->device)) { 1338 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1339 return (1); 1340 } 1341 cur++; 1342 } 1343 return (0); 1344 } 1345 1346 static inline bool 1347 pci_dev_is_disconnected(const struct pci_dev *pdev) 1348 { 1349 pr_debug("TODO: %s\n", __func__); 1350 return (false); 1351 } 1352 1353 static inline const struct pci_device_id * 1354 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 1355 { 1356 if (ids == NULL) 1357 return (NULL); 1358 1359 for (; 1360 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0; 1361 ids++) 1362 if ((ids->vendor == PCI_ANY_ID || 1363 ids->vendor == pdev->vendor) && 1364 (ids->device == PCI_ANY_ID || 1365 ids->device == pdev->device) && 1366 (ids->subvendor == PCI_ANY_ID || 1367 ids->subvendor == pdev->subsystem_vendor) && 1368 (ids->subdevice == PCI_ANY_ID || 1369 ids->subdevice == pdev->subsystem_device) && 1370 ((ids->class ^ pdev->class) & ids->class_mask) == 0) 1371 return (ids); 1372 1373 return (NULL); 1374 } 1375 1376 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1377 unsigned int bus, unsigned int devfn); 1378 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1379 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1380 1381 struct pci_dev *lkpi_pci_get_slot(struct pci_bus *, unsigned int); 1382 #ifndef WANT_NATIVE_PCI_GET_SLOT 1383 #define pci_get_slot(_pbus, _devfn) \ 1384 lkpi_pci_get_slot(_pbus, _devfn) 1385 #endif 1386 1387 static inline int 1388 pci_domain_nr(struct pci_bus *pbus) 1389 { 1390 1391 return (pbus->domain); 1392 } 1393 1394 static inline int 1395 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1396 int pos, uint32_t *val, int len) 1397 { 1398 1399 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1400 return (0); 1401 } 1402 1403 static inline int 1404 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1405 { 1406 uint32_t tmp; 1407 int ret; 1408 1409 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1410 *val = (u16)tmp; 1411 return (ret); 1412 } 1413 1414 static inline int 1415 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1416 { 1417 uint32_t tmp; 1418 int ret; 1419 1420 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1421 *val = (u8)tmp; 1422 return (ret); 1423 } 1424 1425 static inline int 1426 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1427 uint32_t val, int size) 1428 { 1429 1430 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1431 return (0); 1432 } 1433 1434 static inline int 1435 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1436 uint8_t val) 1437 { 1438 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1439 } 1440 1441 static inline int 1442 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1443 uint16_t val) 1444 { 1445 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1446 } 1447 1448 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1449 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1450 struct pci_dev *lkpi_pci_get_base_class(unsigned int class, 1451 struct pci_dev *from); 1452 #define pci_get_base_class(class, from) lkpi_pci_get_base_class(class, from) 1453 1454 /* -------------------------------------------------------------------------- */ 1455 1456 #define pcim_enable_device(pdev) \ 1457 linuxkpi_pcim_enable_device(pdev) 1458 #define pcim_iomap_table(pdev) \ 1459 linuxkpi_pcim_iomap_table(pdev) 1460 #define pcim_iomap_regions(pdev, mask, name) \ 1461 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1462 1463 static inline int 1464 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1465 { 1466 uint32_t requests, req_mask; 1467 int bar, error; 1468 1469 /* Request all the BARs ("regions") we do not iomap. */ 1470 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1471 for (bar = requests = 0; requests != req_mask; bar++) { 1472 if ((req_mask & (1 << bar)) == 0) 1473 continue; 1474 error = pci_request_region(pdev, bar, name); 1475 if (error != 0 && error != -ENODEV) 1476 goto err; 1477 requests |= (1 << bar); 1478 } 1479 1480 error = pcim_iomap_regions(pdev, mask, name); 1481 if (error != 0) 1482 goto err; 1483 1484 return (0); 1485 1486 err: 1487 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1488 if ((requests & (1 << bar)) != 0) 1489 pci_release_region(pdev, bar); 1490 } 1491 1492 return (-EINVAL); 1493 } 1494 1495 /* 1496 * We cannot simply re-define pci_get_device() as we would normally do 1497 * and then hide it in linux_pci.c as too many semi-native drivers still 1498 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1499 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1500 */ 1501 static inline struct pci_dev * 1502 linuxkpi_pci_get_device(uint32_t vendor, uint32_t device, struct pci_dev *odev) 1503 { 1504 1505 return (lkpi_pci_get_device(vendor, device, odev)); 1506 } 1507 1508 #define for_each_pci_dev(_pdev) \ 1509 while ((_pdev = linuxkpi_pci_get_device(PCI_ANY_ID, PCI_ANY_ID, _pdev)) != NULL) 1510 1511 /* This is a FreeBSD extension so we can use bus_*(). */ 1512 static inline void 1513 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1514 { 1515 pdev->want_iomap_res = true; 1516 } 1517 1518 static inline bool 1519 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1520 { 1521 1522 return (false); 1523 } 1524 1525 static inline void * 1526 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1527 { 1528 1529 return (NULL); 1530 } 1531 1532 static inline void 1533 pci_ignore_hotplug(struct pci_dev *pdev) 1534 { 1535 } 1536 1537 static inline const char * 1538 pci_power_name(pci_power_t state) 1539 { 1540 int pstate = state + 1; 1541 1542 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1543 return (pci_power_names[pstate]); 1544 else 1545 return (pci_power_names[0]); 1546 } 1547 1548 static inline int 1549 pcie_get_readrq(struct pci_dev *dev) 1550 { 1551 u16 ctl; 1552 1553 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1554 return (-EINVAL); 1555 1556 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1557 } 1558 1559 static inline bool 1560 pci_is_enabled(struct pci_dev *pdev) 1561 { 1562 1563 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1564 PCIM_CMD_BUSMASTEREN) != 0); 1565 } 1566 1567 static inline int 1568 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1569 { 1570 1571 return (0); 1572 } 1573 1574 static inline int 1575 pci_assign_resource(struct pci_dev *pdev, int bar) 1576 { 1577 1578 return (0); 1579 } 1580 1581 static inline int 1582 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1583 { 1584 1585 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1586 if (vector != 0) 1587 return (-EINVAL); 1588 return (pdev->irq); 1589 } 1590 1591 if (pdev->msix_enabled || pdev->msi_enabled) { 1592 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1593 return (-EINVAL); 1594 return (pdev->dev.irq_start + vector); 1595 } 1596 1597 return (-ENXIO); 1598 } 1599 1600 static inline int 1601 pci_msix_vec_count(struct pci_dev *pdev) 1602 { 1603 int avail; 1604 1605 avail = pci_msix_count(pdev->dev.bsddev); 1606 if (avail == 0) 1607 return (-EINVAL); 1608 return (avail); 1609 } 1610 1611 static inline int 1612 pci_wake_from_d3(struct pci_dev *pdev, bool enable) 1613 { 1614 1615 pr_debug("%s: TODO\n", __func__); 1616 return (0); 1617 } 1618 1619 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1620