1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 #include <linux/device/driver.h> 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_private.h> 49 50 #include <machine/resource.h> 51 52 #include <linux/list.h> 53 #include <linux/dmapool.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/compiler.h> 56 #include <linux/errno.h> 57 #include <asm/atomic.h> 58 #include <asm/memtype.h> 59 #include <linux/device.h> 60 #include <linux/pci_ids.h> 61 #include <linux/pm.h> 62 63 #include <linux/kernel.h> /* pr_debug */ 64 65 struct pci_device_id { 66 uint32_t vendor; 67 uint32_t device; 68 uint32_t subvendor; 69 uint32_t subdevice; 70 uint32_t class; 71 uint32_t class_mask; 72 uintptr_t driver_data; 73 }; 74 75 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 76 #define MODULE_DEVICE_TABLE(_bus, _table) \ 77 \ 78 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 79 DEVMETHOD_END \ 80 }; \ 81 \ 82 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 83 "lkpi_" #_bus #_table, \ 84 _ ## _bus ## _ ## _table ## _methods, \ 85 0 \ 86 }; \ 87 \ 88 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 89 0, 0); \ 90 \ 91 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 92 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 93 94 #define PCI_ANY_ID -1U 95 96 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 97 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 98 #define PCI_FUNC(devfn) ((devfn) & 0x07) 99 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 100 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 101 102 #define PCI_VDEVICE(_vendor, _device) \ 103 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 104 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 105 #define PCI_DEVICE(_vendor, _device) \ 106 .vendor = (_vendor), .device = (_device), \ 107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 108 109 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 110 111 #define PCI_STD_NUM_BARS 6 112 #define PCI_BASE_ADDRESS_0 PCIR_BARS 113 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 114 #define PCI_VENDOR_ID PCIR_VENDOR 115 #define PCI_DEVICE_ID PCIR_DEVICE 116 #define PCI_COMMAND PCIR_COMMAND 117 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 118 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 119 #define PCI_PRIMARY_BUS PCIR_PRIBUS_1 120 #define PCI_SECONDARY_BUS PCIR_SECBUS_1 121 #define PCI_SUBORDINATE_BUS PCIR_SUBBUS_1 122 #define PCI_SEC_LATENCY_TIMER PCIR_SECLAT_1 123 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 124 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 125 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 126 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 127 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 128 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 129 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 130 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 131 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 132 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 133 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 134 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 135 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 136 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 137 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 138 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 139 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 140 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 141 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 142 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 143 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 144 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 145 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 146 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 147 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 148 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 149 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 150 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 151 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 152 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 153 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 154 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 155 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 156 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 157 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 158 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 159 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 160 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 161 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 162 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 163 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 164 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 165 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 166 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 167 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 168 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 169 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 170 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 171 #define PCI_EXP_LNKCTL2_TLS 0x000f 172 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 173 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 174 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 175 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 176 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 177 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 178 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 179 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 180 181 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 182 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 183 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 184 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 185 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 186 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 187 188 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 189 #define PCI_EXP_DEVSTA_TRPND 0x0020 190 191 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 192 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 193 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 194 195 enum pci_bus_speed { 196 PCI_SPEED_UNKNOWN = -1, 197 PCIE_SPEED_2_5GT, 198 PCIE_SPEED_5_0GT, 199 PCIE_SPEED_8_0GT, 200 PCIE_SPEED_16_0GT, 201 PCIE_SPEED_32_0GT, 202 PCIE_SPEED_64_0GT, 203 }; 204 205 enum pcie_link_width { 206 PCIE_LNK_WIDTH_RESRV = 0x00, 207 PCIE_LNK_X1 = 0x01, 208 PCIE_LNK_X2 = 0x02, 209 PCIE_LNK_X4 = 0x04, 210 PCIE_LNK_X8 = 0x08, 211 PCIE_LNK_X12 = 0x0c, 212 PCIE_LNK_X16 = 0x10, 213 PCIE_LNK_X32 = 0x20, 214 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 215 }; 216 217 #define PCIE_LINK_STATE_L0S 0x00000001 218 #define PCIE_LINK_STATE_L1 0x00000002 219 #define PCIE_LINK_STATE_CLKPM 0x00000004 220 221 typedef int pci_power_t; 222 223 #define PCI_D0 PCI_POWERSTATE_D0 224 #define PCI_D1 PCI_POWERSTATE_D1 225 #define PCI_D2 PCI_POWERSTATE_D2 226 #define PCI_D3hot PCI_POWERSTATE_D3 227 #define PCI_D3cold 4 228 229 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 230 231 extern const char *pci_power_names[6]; 232 233 #define PCI_ERR_UNCOR_STATUS PCIR_AER_UC_STATUS 234 #define PCI_ERR_COR_STATUS PCIR_AER_COR_STATUS 235 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 236 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 237 238 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 239 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 240 241 #define PCI_L1SS_CTL1 0x8 242 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 243 244 #define PCI_IRQ_INTX 0x01 245 #define PCI_IRQ_MSI 0x02 246 #define PCI_IRQ_MSIX 0x04 247 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_INTX) 248 249 #if defined(LINUXKPI_VERSION) && (LINUXKPI_VERSION <= 61000) 250 #define PCI_IRQ_LEGACY PCI_IRQ_INTX 251 #endif 252 253 struct pci_dev; 254 255 struct pci_driver { 256 struct list_head node; 257 char *name; 258 const struct pci_device_id *id_table; 259 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 260 void (*remove)(struct pci_dev *dev); 261 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 262 int (*resume) (struct pci_dev *dev); /* Device woken up */ 263 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 264 driver_t bsddriver; 265 devclass_t bsdclass; 266 struct device_driver driver; 267 const struct pci_error_handlers *err_handler; 268 bool isdrm; 269 int bsd_probe_return; 270 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 271 const nvlist_t *pf_config); 272 void (*bsd_iov_uninit)(device_t dev); 273 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 274 const nvlist_t *vf_config); 275 }; 276 277 struct pci_bus { 278 struct pci_dev *self; 279 /* struct pci_bus *parent */ 280 int domain; 281 int number; 282 }; 283 284 extern struct list_head pci_drivers; 285 extern struct list_head pci_devices; 286 extern spinlock_t pci_lock; 287 288 #define __devexit_p(x) x 289 290 #define module_pci_driver(_drv) \ 291 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver) 292 293 struct msi_msg { 294 uint32_t data; 295 }; 296 297 struct pci_msi_desc { 298 struct { 299 bool is_64; 300 } msi_attrib; 301 }; 302 303 struct msi_desc { 304 struct msi_msg msg; 305 struct pci_msi_desc pci; 306 }; 307 308 struct msix_entry { 309 int entry; 310 int vector; 311 }; 312 313 /* 314 * If we find drivers accessing this from multiple KPIs we may have to 315 * refcount objects of this structure. 316 */ 317 struct resource; 318 struct pci_mmio_region { 319 TAILQ_ENTRY(pci_mmio_region) next; 320 struct resource *res; 321 int rid; 322 int type; 323 }; 324 325 struct pci_dev { 326 struct device dev; 327 struct list_head links; 328 struct pci_driver *pdrv; 329 struct pci_bus *bus; 330 struct pci_dev *root; 331 pci_power_t current_state; 332 uint16_t device; 333 uint16_t vendor; 334 uint16_t subsystem_vendor; 335 uint16_t subsystem_device; 336 unsigned int irq; 337 unsigned int devfn; 338 uint32_t class; 339 uint8_t revision; 340 uint8_t msi_cap; 341 uint8_t msix_cap; 342 bool managed; /* devres "pcim_*(). */ 343 bool want_iomap_res; 344 bool msi_enabled; 345 bool msix_enabled; 346 phys_addr_t rom; 347 size_t romlen; 348 struct msi_desc **msi_desc; 349 char *path_name; 350 spinlock_t pcie_cap_lock; 351 352 TAILQ_HEAD(, pci_mmio_region) mmio; 353 }; 354 355 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 356 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 357 unsigned int flags); 358 bool pci_device_is_present(struct pci_dev *pdev); 359 360 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 361 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 362 void *linuxkpi_pci_iomap_range(struct pci_dev *pdev, int mmio_bar, 363 unsigned long mmio_off, unsigned long mmio_size); 364 void *linuxkpi_pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size); 365 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 366 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 367 const char *name); 368 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 369 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 370 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 371 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 372 int nreq); 373 374 /* Internal helper function(s). */ 375 struct pci_dev *lkpinew_pci_dev(device_t); 376 void lkpi_pci_devres_release(struct device *, void *); 377 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 378 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 379 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 380 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 381 382 #define pci_err(pdev, fmt, ...) \ 383 dev_err(&(pdev)->dev, fmt, ##__VA_ARGS__) 384 #define pci_info(pdev, fmt, ...) \ 385 dev_info(&(pdev)->dev, fmt, ##__VA_ARGS__) 386 387 static inline bool 388 dev_is_pci(struct device *dev) 389 { 390 391 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 392 } 393 394 static inline uint16_t 395 pci_dev_id(struct pci_dev *pdev) 396 { 397 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 398 } 399 400 static inline int 401 pci_resource_type(struct pci_dev *pdev, int bar) 402 { 403 struct pci_map *pm; 404 405 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 406 if (!pm) 407 return (-1); 408 409 if (PCI_BAR_IO(pm->pm_value)) 410 return (SYS_RES_IOPORT); 411 else 412 return (SYS_RES_MEMORY); 413 } 414 415 /* 416 * All drivers just seem to want to inspect the type not flags. 417 */ 418 static inline int 419 pci_resource_flags(struct pci_dev *pdev, int bar) 420 { 421 int type; 422 423 type = pci_resource_type(pdev, bar); 424 if (type < 0) 425 return (0); 426 return (1 << type); 427 } 428 429 static inline const char * 430 pci_name(struct pci_dev *d) 431 { 432 return d->path_name; 433 } 434 435 static inline void * 436 pci_get_drvdata(struct pci_dev *pdev) 437 { 438 439 return dev_get_drvdata(&pdev->dev); 440 } 441 442 static inline void 443 pci_set_drvdata(struct pci_dev *pdev, void *data) 444 { 445 446 dev_set_drvdata(&pdev->dev, data); 447 } 448 449 static inline struct pci_dev * 450 pci_dev_get(struct pci_dev *pdev) 451 { 452 453 if (pdev != NULL) 454 get_device(&pdev->dev); 455 return (pdev); 456 } 457 458 static __inline void 459 pci_dev_put(struct pci_dev *pdev) 460 { 461 462 if (pdev != NULL) 463 put_device(&pdev->dev); 464 } 465 466 static inline int 467 pci_enable_device(struct pci_dev *pdev) 468 { 469 470 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 471 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 472 return (0); 473 } 474 475 static inline void 476 pci_disable_device(struct pci_dev *pdev) 477 { 478 479 pci_disable_busmaster(pdev->dev.bsddev); 480 } 481 482 static inline int 483 pci_set_master(struct pci_dev *pdev) 484 { 485 486 pci_enable_busmaster(pdev->dev.bsddev); 487 return (0); 488 } 489 490 static inline int 491 pci_set_power_state(struct pci_dev *pdev, int state) 492 { 493 494 pci_set_powerstate(pdev->dev.bsddev, state); 495 return (0); 496 } 497 498 static inline int 499 pci_clear_master(struct pci_dev *pdev) 500 { 501 502 pci_disable_busmaster(pdev->dev.bsddev); 503 return (0); 504 } 505 506 static inline bool 507 pci_is_root_bus(struct pci_bus *pbus) 508 { 509 510 return (pbus->self == NULL); 511 } 512 513 static inline struct pci_dev * 514 pci_upstream_bridge(struct pci_dev *pdev) 515 { 516 517 if (pci_is_root_bus(pdev->bus)) 518 return (NULL); 519 520 /* 521 * If we do not have a (proper) "upstream bridge" set, e.g., we point 522 * to ourselves, try to handle this case on the fly like we do 523 * for pcie_find_root_port(). 524 */ 525 if (pdev == pdev->bus->self) { 526 device_t bridge; 527 528 /* 529 * In the case of DRM drivers, the passed device is a child of 530 * `vgapci`. We want to start the lookup from `vgapci`, so the 531 * parent of the passed `drmn`. 532 * 533 * We can use the `isdrm` flag to determine this. 534 */ 535 bridge = pdev->dev.bsddev; 536 if (pdev->pdrv != NULL && pdev->pdrv->isdrm) 537 bridge = device_get_parent(bridge); 538 if (bridge == NULL) 539 goto done; 540 541 bridge = device_get_parent(bridge); 542 if (bridge == NULL) 543 goto done; 544 bridge = device_get_parent(bridge); 545 if (bridge == NULL) 546 goto done; 547 if (device_get_devclass(device_get_parent(bridge)) != 548 devclass_find("pci")) 549 goto done; 550 551 /* 552 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 553 * for it so it can be returned. 554 */ 555 pdev->bus->self = lkpinew_pci_dev(bridge); 556 } 557 done: 558 return (pdev->bus->self); 559 } 560 561 #define pci_release_region(pdev, bar) linuxkpi_pci_release_region(pdev, bar) 562 #define pci_release_regions(pdev) linuxkpi_pci_release_regions(pdev) 563 #define pci_request_regions(pdev, res_name) \ 564 linuxkpi_pci_request_regions(pdev, res_name) 565 566 static inline void 567 lkpi_pci_disable_msix(struct pci_dev *pdev) 568 { 569 570 pci_release_msi(pdev->dev.bsddev); 571 572 /* 573 * The MSIX IRQ numbers associated with this PCI device are no 574 * longer valid and might be re-assigned. Make sure 575 * lkpi_pci_find_irq_dev() does no longer see them by 576 * resetting their references to zero: 577 */ 578 pdev->dev.irq_start = 0; 579 pdev->dev.irq_end = 0; 580 pdev->msix_enabled = false; 581 } 582 /* Only for consistency. No conflict on that one. */ 583 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 584 585 static inline void 586 lkpi_pci_disable_msi(struct pci_dev *pdev) 587 { 588 589 pci_release_msi(pdev->dev.bsddev); 590 591 pdev->dev.irq_start = 0; 592 pdev->dev.irq_end = 0; 593 pdev->irq = pdev->dev.irq; 594 pdev->msi_enabled = false; 595 } 596 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 597 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 598 599 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 600 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 601 602 static inline bus_addr_t 603 pci_bus_address(struct pci_dev *pdev, int bar) 604 { 605 606 return (pci_resource_start(pdev, bar)); 607 } 608 609 #define PCI_CAP_ID_EXP PCIY_EXPRESS 610 #define PCI_CAP_ID_PCIX PCIY_PCIX 611 #define PCI_CAP_ID_AGP PCIY_AGP 612 #define PCI_CAP_ID_PM PCIY_PMG 613 614 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 615 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 616 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 617 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 618 #define PCI_EXP_LNKSTA PCIER_LINK_STA 619 620 static inline int 621 pci_find_capability(struct pci_dev *pdev, int capid) 622 { 623 int reg; 624 625 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 626 return (0); 627 return (reg); 628 } 629 630 static inline int pci_pcie_cap(struct pci_dev *dev) 631 { 632 return pci_find_capability(dev, PCI_CAP_ID_EXP); 633 } 634 635 static inline int 636 pci_find_ext_capability(struct pci_dev *pdev, int capid) 637 { 638 int reg; 639 640 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 641 return (0); 642 return (reg); 643 } 644 645 #define PCIM_PCAP_PME_SHIFT 11 646 static __inline bool 647 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 648 { 649 struct pci_devinfo *dinfo; 650 pcicfgregs *cfg; 651 652 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 653 return (false); 654 655 dinfo = device_get_ivars(pdev->dev.bsddev); 656 cfg = &dinfo->cfg; 657 658 if (cfg->pp.pp_cap == 0) 659 return (false); 660 661 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 662 return (true); 663 664 return (false); 665 } 666 667 static inline int 668 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 669 { 670 671 if (!pci_enable_aspm) 672 return (-EPERM); 673 674 return (-ENXIO); 675 } 676 677 static inline int 678 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 679 { 680 681 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 682 return (0); 683 } 684 685 static inline int 686 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 687 { 688 689 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 690 return (0); 691 } 692 693 static inline int 694 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 695 { 696 697 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 698 return (0); 699 } 700 701 static inline int 702 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 703 { 704 705 pci_write_config(pdev->dev.bsddev, where, val, 1); 706 return (0); 707 } 708 709 static inline int 710 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 711 { 712 713 pci_write_config(pdev->dev.bsddev, where, val, 2); 714 return (0); 715 } 716 717 static inline int 718 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 719 { 720 721 pci_write_config(pdev->dev.bsddev, where, val, 4); 722 return (0); 723 } 724 725 int linux_pci_register_driver(struct pci_driver *pdrv); 726 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 727 void linux_pci_unregister_driver(struct pci_driver *pdrv); 728 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 729 730 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 731 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 732 733 /* 734 * Enable msix, positive errors indicate actual number of available 735 * vectors. Negative errors are failures. 736 * 737 * NB: define added to prevent this definition of pci_enable_msix from 738 * clashing with the native FreeBSD version. 739 */ 740 #define pci_enable_msix(...) linuxkpi_pci_enable_msix(__VA_ARGS__) 741 742 #define pci_enable_msix_range(...) \ 743 linux_pci_enable_msix_range(__VA_ARGS__) 744 745 static inline int 746 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 747 int minvec, int maxvec) 748 { 749 int nvec = maxvec; 750 int rc; 751 752 if (maxvec < minvec) 753 return (-ERANGE); 754 755 do { 756 rc = pci_enable_msix(dev, entries, nvec); 757 if (rc < 0) { 758 return (rc); 759 } else if (rc > 0) { 760 if (rc < minvec) 761 return (-ENOSPC); 762 nvec = rc; 763 } 764 } while (rc); 765 return (nvec); 766 } 767 768 #define pci_enable_msi(pdev) \ 769 linux_pci_enable_msi(pdev) 770 771 static inline int 772 pci_enable_msi(struct pci_dev *pdev) 773 { 774 775 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 776 } 777 778 static inline int 779 pci_channel_offline(struct pci_dev *pdev) 780 { 781 782 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 783 } 784 785 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 786 { 787 return -ENODEV; 788 } 789 790 static inline void pci_disable_sriov(struct pci_dev *dev) 791 { 792 } 793 794 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \ 795 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) 796 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 797 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 798 #define pci_iounmap(pdev, res) linuxkpi_pci_iounmap(pdev, res) 799 800 static inline void 801 lkpi_pci_save_state(struct pci_dev *pdev) 802 { 803 804 pci_save_state(pdev->dev.bsddev); 805 } 806 807 static inline void 808 lkpi_pci_restore_state(struct pci_dev *pdev) 809 { 810 811 pci_restore_state(pdev->dev.bsddev); 812 } 813 814 #define pci_save_state(dev) lkpi_pci_save_state(dev) 815 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 816 817 static inline int 818 pci_reset_function(struct pci_dev *pdev) 819 { 820 821 return (-ENOSYS); 822 } 823 824 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 825 const struct pci_device_id _table[] __devinitdata 826 827 /* XXX This should not be necessary. */ 828 #define pcix_set_mmrbc(d, v) 0 829 #define pcix_get_max_mmrbc(d) 0 830 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 831 832 #define PCI_DMA_BIDIRECTIONAL 0 833 #define PCI_DMA_TODEVICE 1 834 #define PCI_DMA_FROMDEVICE 2 835 #define PCI_DMA_NONE 3 836 837 #define pci_pool dma_pool 838 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 839 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 840 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 841 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 842 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 843 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 844 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 845 _size, _vaddr, _dma_handle) 846 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 847 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 848 _sg, _nents, (enum dma_data_direction)_dir) 849 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 850 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 851 (_ptr), (_size), (enum dma_data_direction)_dir) 852 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 853 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 854 _addr, _size, (enum dma_data_direction)_dir) 855 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 856 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 857 _sg, _nents, (enum dma_data_direction)_dir) 858 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 859 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 860 _offset, _size, (enum dma_data_direction)_dir) 861 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 862 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 863 _dma_address, _size, (enum dma_data_direction)_dir) 864 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 865 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 866 dma_mapping_error(&(_pdev)->dev, _dma_addr) 867 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 868 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 869 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 870 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 871 #define pci_unmap_addr dma_unmap_addr 872 #define pci_unmap_addr_set dma_unmap_addr_set 873 #define pci_unmap_len dma_unmap_len 874 #define pci_unmap_len_set dma_unmap_len_set 875 876 typedef unsigned int __bitwise pci_channel_state_t; 877 typedef unsigned int __bitwise pci_ers_result_t; 878 879 enum pci_channel_state { 880 pci_channel_io_normal = 1, 881 pci_channel_io_frozen = 2, 882 pci_channel_io_perm_failure = 3, 883 }; 884 885 enum pci_ers_result { 886 PCI_ERS_RESULT_NONE = 1, 887 PCI_ERS_RESULT_CAN_RECOVER = 2, 888 PCI_ERS_RESULT_NEED_RESET = 3, 889 PCI_ERS_RESULT_DISCONNECT = 4, 890 PCI_ERS_RESULT_RECOVERED = 5, 891 }; 892 893 /* PCI bus error event callbacks */ 894 struct pci_error_handlers { 895 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 896 enum pci_channel_state error); 897 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 898 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 899 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 900 void (*resume)(struct pci_dev *dev); 901 }; 902 903 /* FreeBSD does not support SRIOV - yet */ 904 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 905 { 906 return dev; 907 } 908 909 static inline bool pci_is_pcie(struct pci_dev *dev) 910 { 911 return !!pci_pcie_cap(dev); 912 } 913 914 static inline u16 pcie_flags_reg(struct pci_dev *dev) 915 { 916 int pos; 917 u16 reg16; 918 919 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 920 if (!pos) 921 return 0; 922 923 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 924 925 return reg16; 926 } 927 928 static inline int pci_pcie_type(struct pci_dev *dev) 929 { 930 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 931 } 932 933 static inline int pcie_cap_version(struct pci_dev *dev) 934 { 935 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 936 } 937 938 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 939 { 940 int type = pci_pcie_type(dev); 941 942 return pcie_cap_version(dev) > 1 || 943 type == PCI_EXP_TYPE_ROOT_PORT || 944 type == PCI_EXP_TYPE_ENDPOINT || 945 type == PCI_EXP_TYPE_LEG_END; 946 } 947 948 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 949 { 950 return true; 951 } 952 953 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 954 { 955 int type = pci_pcie_type(dev); 956 957 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 958 (type == PCI_EXP_TYPE_DOWNSTREAM && 959 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 960 } 961 962 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 963 { 964 int type = pci_pcie_type(dev); 965 966 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 967 type == PCI_EXP_TYPE_RC_EC; 968 } 969 970 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 971 { 972 if (!pci_is_pcie(dev)) 973 return false; 974 975 switch (pos) { 976 case PCI_EXP_FLAGS_TYPE: 977 return true; 978 case PCI_EXP_DEVCAP: 979 case PCI_EXP_DEVCTL: 980 case PCI_EXP_DEVSTA: 981 return pcie_cap_has_devctl(dev); 982 case PCI_EXP_LNKCAP: 983 case PCI_EXP_LNKCTL: 984 case PCI_EXP_LNKSTA: 985 return pcie_cap_has_lnkctl(dev); 986 case PCI_EXP_SLTCAP: 987 case PCI_EXP_SLTCTL: 988 case PCI_EXP_SLTSTA: 989 return pcie_cap_has_sltctl(dev); 990 case PCI_EXP_RTCTL: 991 case PCI_EXP_RTCAP: 992 case PCI_EXP_RTSTA: 993 return pcie_cap_has_rtctl(dev); 994 case PCI_EXP_DEVCAP2: 995 case PCI_EXP_DEVCTL2: 996 case PCI_EXP_LNKCAP2: 997 case PCI_EXP_LNKCTL2: 998 case PCI_EXP_LNKSTA2: 999 return pcie_cap_version(dev) > 1; 1000 default: 1001 return false; 1002 } 1003 } 1004 1005 static inline int 1006 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1007 { 1008 *dst = 0; 1009 if (pos & 3) 1010 return -EINVAL; 1011 1012 if (!pcie_capability_reg_implemented(dev, pos)) 1013 return -EINVAL; 1014 1015 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1016 } 1017 1018 static inline int 1019 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1020 { 1021 *dst = 0; 1022 if (pos & 3) 1023 return -EINVAL; 1024 1025 if (!pcie_capability_reg_implemented(dev, pos)) 1026 return -EINVAL; 1027 1028 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1029 } 1030 1031 static inline int 1032 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1033 { 1034 if (pos & 1) 1035 return -EINVAL; 1036 1037 if (!pcie_capability_reg_implemented(dev, pos)) 1038 return 0; 1039 1040 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1041 } 1042 1043 static inline int 1044 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1045 uint16_t clear, uint16_t set) 1046 { 1047 int error; 1048 uint16_t v; 1049 1050 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1051 spin_lock(&dev->pcie_cap_lock); 1052 1053 error = pcie_capability_read_word(dev, pos, &v); 1054 if (error == 0) { 1055 v &= ~clear; 1056 v |= set; 1057 error = pcie_capability_write_word(dev, pos, v); 1058 } 1059 1060 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1061 spin_unlock(&dev->pcie_cap_lock); 1062 1063 return (error); 1064 } 1065 1066 static inline int 1067 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1068 { 1069 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1070 } 1071 1072 static inline int 1073 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1074 { 1075 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1076 } 1077 1078 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1079 enum pci_bus_speed *speed, enum pcie_link_width *width) 1080 { 1081 *speed = PCI_SPEED_UNKNOWN; 1082 *width = PCIE_LNK_WIDTH_UNKNOWN; 1083 return (0); 1084 } 1085 1086 static inline int 1087 pci_num_vf(struct pci_dev *dev) 1088 { 1089 return (0); 1090 } 1091 1092 static inline enum pci_bus_speed 1093 pcie_get_speed_cap(struct pci_dev *dev) 1094 { 1095 device_t root; 1096 uint32_t lnkcap, lnkcap2; 1097 int error, pos; 1098 1099 root = device_get_parent(dev->dev.bsddev); 1100 if (root == NULL) 1101 return (PCI_SPEED_UNKNOWN); 1102 root = device_get_parent(root); 1103 if (root == NULL) 1104 return (PCI_SPEED_UNKNOWN); 1105 root = device_get_parent(root); 1106 if (root == NULL) 1107 return (PCI_SPEED_UNKNOWN); 1108 1109 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1110 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1111 return (PCI_SPEED_UNKNOWN); 1112 1113 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1114 return (PCI_SPEED_UNKNOWN); 1115 1116 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1117 1118 if (lnkcap2) { /* PCIe r3.0-compliant */ 1119 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1120 return (PCIE_SPEED_2_5GT); 1121 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1122 return (PCIE_SPEED_5_0GT); 1123 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1124 return (PCIE_SPEED_8_0GT); 1125 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1126 return (PCIE_SPEED_16_0GT); 1127 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1128 return (PCIE_SPEED_32_0GT); 1129 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1130 return (PCIE_SPEED_64_0GT); 1131 } else { /* pre-r3.0 */ 1132 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1133 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1134 return (PCIE_SPEED_2_5GT); 1135 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1136 return (PCIE_SPEED_5_0GT); 1137 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1138 return (PCIE_SPEED_8_0GT); 1139 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1140 return (PCIE_SPEED_16_0GT); 1141 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1142 return (PCIE_SPEED_32_0GT); 1143 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1144 return (PCIE_SPEED_64_0GT); 1145 } 1146 return (PCI_SPEED_UNKNOWN); 1147 } 1148 1149 static inline enum pcie_link_width 1150 pcie_get_width_cap(struct pci_dev *dev) 1151 { 1152 uint32_t lnkcap; 1153 1154 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1155 if (lnkcap) 1156 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1157 1158 return (PCIE_LNK_WIDTH_UNKNOWN); 1159 } 1160 1161 static inline int 1162 pcie_get_mps(struct pci_dev *dev) 1163 { 1164 return (pci_get_max_payload(dev->dev.bsddev)); 1165 } 1166 1167 static inline uint32_t 1168 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1169 { 1170 1171 switch(spd) { 1172 case PCIE_SPEED_64_0GT: 1173 return (64000 * 128 / 130); 1174 case PCIE_SPEED_32_0GT: 1175 return (32000 * 128 / 130); 1176 case PCIE_SPEED_16_0GT: 1177 return (16000 * 128 / 130); 1178 case PCIE_SPEED_8_0GT: 1179 return (8000 * 128 / 130); 1180 case PCIE_SPEED_5_0GT: 1181 return (5000 * 8 / 10); 1182 case PCIE_SPEED_2_5GT: 1183 return (2500 * 8 / 10); 1184 default: 1185 return (0); 1186 } 1187 } 1188 1189 static inline uint32_t 1190 pcie_bandwidth_available(struct pci_dev *pdev, 1191 struct pci_dev **limiting, 1192 enum pci_bus_speed *speed, 1193 enum pcie_link_width *width) 1194 { 1195 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1196 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1197 1198 if (speed) 1199 *speed = nspeed; 1200 if (width) 1201 *width = nwidth; 1202 1203 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1204 } 1205 1206 static inline bool 1207 pcie_aspm_enabled(struct pci_dev *pdev) 1208 { 1209 return (false); 1210 } 1211 1212 static inline struct pci_dev * 1213 pcie_find_root_port(struct pci_dev *pdev) 1214 { 1215 device_t root; 1216 1217 if (pdev->root != NULL) 1218 return (pdev->root); 1219 1220 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1221 if (root == NULL) 1222 return (NULL); 1223 1224 pdev->root = lkpinew_pci_dev(root); 1225 return (pdev->root); 1226 } 1227 1228 /* This is needed when people rip out the device "HotPlug". */ 1229 static inline void 1230 pci_lock_rescan_remove(void) 1231 { 1232 } 1233 1234 static inline void 1235 pci_unlock_rescan_remove(void) 1236 { 1237 } 1238 1239 static __inline void 1240 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1241 { 1242 } 1243 1244 static inline int 1245 pci_rescan_bus(struct pci_bus *pbus) 1246 { 1247 device_t *devlist, parent; 1248 int devcount, error; 1249 1250 if (!device_is_attached(pbus->self->dev.bsddev)) 1251 return (0); 1252 /* pci_rescan_method() will work on the pcib (parent). */ 1253 error = BUS_RESCAN(pbus->self->dev.bsddev); 1254 if (error != 0) 1255 return (0); 1256 1257 parent = device_get_parent(pbus->self->dev.bsddev); 1258 error = device_get_children(parent, &devlist, &devcount); 1259 if (error != 0) 1260 return (0); 1261 if (devcount != 0) 1262 free(devlist, M_TEMP); 1263 1264 return (devcount); 1265 } 1266 1267 /* 1268 * The following functions can be used to attach/detach the LinuxKPI's 1269 * PCI device runtime. The pci_driver and pci_device_id pointer is 1270 * allowed to be NULL. Other pointers must be all valid. 1271 * The pci_dev structure should be zero-initialized before passed 1272 * to the linux_pci_attach_device function. 1273 */ 1274 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1275 const struct pci_device_id *, struct pci_dev *); 1276 extern int linux_pci_detach_device(struct pci_dev *); 1277 1278 static inline int 1279 pci_dev_present(const struct pci_device_id *cur) 1280 { 1281 while (cur != NULL && (cur->vendor || cur->device)) { 1282 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1283 return (1); 1284 } 1285 cur++; 1286 } 1287 return (0); 1288 } 1289 1290 static inline const struct pci_device_id * 1291 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 1292 { 1293 if (ids == NULL) 1294 return (NULL); 1295 1296 for (; 1297 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0; 1298 ids++) 1299 if ((ids->vendor == PCI_ANY_ID || 1300 ids->vendor == pdev->vendor) && 1301 (ids->device == PCI_ANY_ID || 1302 ids->device == pdev->device) && 1303 (ids->subvendor == PCI_ANY_ID || 1304 ids->subvendor == pdev->subsystem_vendor) && 1305 (ids->subdevice == PCI_ANY_ID || 1306 ids->subdevice == pdev->subsystem_device) && 1307 ((ids->class ^ pdev->class) & ids->class_mask) == 0) 1308 return (ids); 1309 1310 return (NULL); 1311 } 1312 1313 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1314 unsigned int bus, unsigned int devfn); 1315 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1316 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1317 1318 static inline int 1319 pci_domain_nr(struct pci_bus *pbus) 1320 { 1321 1322 return (pbus->domain); 1323 } 1324 1325 static inline int 1326 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1327 int pos, uint32_t *val, int len) 1328 { 1329 1330 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1331 return (0); 1332 } 1333 1334 static inline int 1335 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1336 { 1337 uint32_t tmp; 1338 int ret; 1339 1340 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1341 *val = (u16)tmp; 1342 return (ret); 1343 } 1344 1345 static inline int 1346 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1347 { 1348 uint32_t tmp; 1349 int ret; 1350 1351 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1352 *val = (u8)tmp; 1353 return (ret); 1354 } 1355 1356 static inline int 1357 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1358 uint32_t val, int size) 1359 { 1360 1361 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1362 return (0); 1363 } 1364 1365 static inline int 1366 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1367 uint8_t val) 1368 { 1369 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1370 } 1371 1372 static inline int 1373 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1374 uint16_t val) 1375 { 1376 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1377 } 1378 1379 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1380 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1381 struct pci_dev *lkpi_pci_get_base_class(unsigned int class, 1382 struct pci_dev *from); 1383 #define pci_get_base_class(class, from) lkpi_pci_get_base_class(class, from) 1384 1385 /* -------------------------------------------------------------------------- */ 1386 1387 #define pcim_enable_device(pdev) linuxkpi_pcim_enable_device(pdev) 1388 #define pcim_iomap_table(pdev) linuxkpi_pcim_iomap_table(pdev) 1389 #define pcim_iomap_regions(pdev, mask, name) \ 1390 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1391 1392 static inline int 1393 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1394 { 1395 uint32_t requests, req_mask; 1396 int bar, error; 1397 1398 /* Request all the BARs ("regions") we do not iomap. */ 1399 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1400 for (bar = requests = 0; requests != req_mask; bar++) { 1401 if ((req_mask & (1 << bar)) == 0) 1402 continue; 1403 error = pci_request_region(pdev, bar, name); 1404 if (error != 0 && error != -ENODEV) 1405 goto err; 1406 requests |= (1 << bar); 1407 } 1408 1409 error = pcim_iomap_regions(pdev, mask, name); 1410 if (error != 0) 1411 goto err; 1412 1413 return (0); 1414 1415 err: 1416 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1417 if ((requests & (1 << bar)) != 0) 1418 pci_release_region(pdev, bar); 1419 } 1420 1421 return (-EINVAL); 1422 } 1423 1424 /* 1425 * We cannot simply re-define pci_get_device() as we would normally do 1426 * and then hide it in linux_pci.c as too many semi-native drivers still 1427 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1428 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1429 */ 1430 static inline struct pci_dev * 1431 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1432 { 1433 1434 return (lkpi_pci_get_device(vendor, device, odev)); 1435 } 1436 1437 /* This is a FreeBSD extension so we can use bus_*(). */ 1438 static inline void 1439 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1440 { 1441 pdev->want_iomap_res = true; 1442 } 1443 1444 static inline bool 1445 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1446 { 1447 1448 return (false); 1449 } 1450 1451 static inline void * 1452 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1453 { 1454 1455 return (NULL); 1456 } 1457 1458 static inline void 1459 pci_ignore_hotplug(struct pci_dev *pdev) 1460 { 1461 } 1462 1463 static inline const char * 1464 pci_power_name(pci_power_t state) 1465 { 1466 int pstate = state + 1; 1467 1468 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1469 return (pci_power_names[pstate]); 1470 else 1471 return (pci_power_names[0]); 1472 } 1473 1474 static inline int 1475 pcie_get_readrq(struct pci_dev *dev) 1476 { 1477 u16 ctl; 1478 1479 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1480 return (-EINVAL); 1481 1482 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1483 } 1484 1485 static inline bool 1486 pci_is_enabled(struct pci_dev *pdev) 1487 { 1488 1489 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1490 PCIM_CMD_BUSMASTEREN) != 0); 1491 } 1492 1493 static inline int 1494 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1495 { 1496 1497 return (0); 1498 } 1499 1500 static inline int 1501 pci_assign_resource(struct pci_dev *pdev, int bar) 1502 { 1503 1504 return (0); 1505 } 1506 1507 static inline int 1508 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1509 { 1510 1511 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1512 if (vector != 0) 1513 return (-EINVAL); 1514 return (pdev->irq); 1515 } 1516 1517 if (pdev->msix_enabled || pdev->msi_enabled) { 1518 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1519 return (-EINVAL); 1520 return (pdev->dev.irq_start + vector); 1521 } 1522 1523 return (-ENXIO); 1524 } 1525 1526 static inline int 1527 pci_wake_from_d3(struct pci_dev *pdev, bool enable) 1528 { 1529 1530 pr_debug("%s: TODO\n", __func__); 1531 return (0); 1532 } 1533 1534 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1535