1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 #include <linux/device/driver.h> 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_private.h> 49 50 #include <machine/resource.h> 51 52 #include <linux/list.h> 53 #include <linux/dmapool.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/compiler.h> 56 #include <linux/errno.h> 57 #include <asm/atomic.h> 58 #include <asm/memtype.h> 59 #include <linux/device.h> 60 #include <linux/pci_ids.h> 61 #include <linux/pm.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 74 #define MODULE_DEVICE_TABLE(_bus, _table) \ 75 \ 76 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 77 DEVMETHOD_END \ 78 }; \ 79 \ 80 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 81 "lkpi_" #_bus #_table, \ 82 _ ## _bus ## _ ## _table ## _methods, \ 83 0 \ 84 }; \ 85 \ 86 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 87 0, 0); \ 88 \ 89 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 90 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 91 92 #define PCI_ANY_ID -1U 93 94 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 95 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 96 #define PCI_FUNC(devfn) ((devfn) & 0x07) 97 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 98 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 99 100 #define PCI_VDEVICE(_vendor, _device) \ 101 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 102 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 103 #define PCI_DEVICE(_vendor, _device) \ 104 .vendor = (_vendor), .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 107 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 108 109 #define PCI_STD_NUM_BARS 6 110 #define PCI_BASE_ADDRESS_0 PCIR_BARS 111 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 112 #define PCI_VENDOR_ID PCIR_VENDOR 113 #define PCI_DEVICE_ID PCIR_DEVICE 114 #define PCI_COMMAND PCIR_COMMAND 115 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 116 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 117 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 118 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 119 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 120 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 121 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 122 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 123 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 124 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 125 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 126 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 127 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 128 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 129 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 130 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 131 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 132 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 133 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 134 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 135 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 136 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 137 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 138 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 139 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 140 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 141 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 142 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 143 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 144 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 145 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 146 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 147 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 148 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 149 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 150 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 151 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 152 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 153 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 154 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 155 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 156 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 157 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 158 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 159 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 160 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 161 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 162 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 163 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 164 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 165 #define PCI_EXP_LNKCTL2_TLS 0x000f 166 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 167 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 168 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 169 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 170 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 171 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 172 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 173 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 174 175 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 176 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 177 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 178 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 179 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 180 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 181 182 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 183 #define PCI_EXP_DEVSTA_TRPND 0x0020 184 185 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 186 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 187 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 188 189 enum pci_bus_speed { 190 PCI_SPEED_UNKNOWN = -1, 191 PCIE_SPEED_2_5GT, 192 PCIE_SPEED_5_0GT, 193 PCIE_SPEED_8_0GT, 194 PCIE_SPEED_16_0GT, 195 PCIE_SPEED_32_0GT, 196 PCIE_SPEED_64_0GT, 197 }; 198 199 enum pcie_link_width { 200 PCIE_LNK_WIDTH_RESRV = 0x00, 201 PCIE_LNK_X1 = 0x01, 202 PCIE_LNK_X2 = 0x02, 203 PCIE_LNK_X4 = 0x04, 204 PCIE_LNK_X8 = 0x08, 205 PCIE_LNK_X12 = 0x0c, 206 PCIE_LNK_X16 = 0x10, 207 PCIE_LNK_X32 = 0x20, 208 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 209 }; 210 211 #define PCIE_LINK_STATE_L0S 0x00000001 212 #define PCIE_LINK_STATE_L1 0x00000002 213 #define PCIE_LINK_STATE_CLKPM 0x00000004 214 215 typedef int pci_power_t; 216 217 #define PCI_D0 PCI_POWERSTATE_D0 218 #define PCI_D1 PCI_POWERSTATE_D1 219 #define PCI_D2 PCI_POWERSTATE_D2 220 #define PCI_D3hot PCI_POWERSTATE_D3 221 #define PCI_D3cold 4 222 223 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 224 225 extern const char *pci_power_names[6]; 226 227 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 228 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 229 230 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 231 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 232 233 #define PCI_L1SS_CTL1 0x8 234 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 235 236 #define PCI_IRQ_INTX 0x01 237 #define PCI_IRQ_MSI 0x02 238 #define PCI_IRQ_MSIX 0x04 239 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_INTX) 240 241 #if defined(LINUXKPI_VERSION) && (LINUXKPI_VERSION >= 60800) 242 #define PCI_IRQ_LEGACY PCI_IRQ_INTX 243 #endif 244 245 struct pci_dev; 246 247 struct pci_driver { 248 struct list_head node; 249 char *name; 250 const struct pci_device_id *id_table; 251 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 252 void (*remove)(struct pci_dev *dev); 253 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 254 int (*resume) (struct pci_dev *dev); /* Device woken up */ 255 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 256 driver_t bsddriver; 257 devclass_t bsdclass; 258 struct device_driver driver; 259 const struct pci_error_handlers *err_handler; 260 bool isdrm; 261 int bsd_probe_return; 262 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 263 const nvlist_t *pf_config); 264 void (*bsd_iov_uninit)(device_t dev); 265 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 266 const nvlist_t *vf_config); 267 }; 268 269 struct pci_bus { 270 struct pci_dev *self; 271 /* struct pci_bus *parent */ 272 int domain; 273 int number; 274 }; 275 276 extern struct list_head pci_drivers; 277 extern struct list_head pci_devices; 278 extern spinlock_t pci_lock; 279 280 #define __devexit_p(x) x 281 282 #define module_pci_driver(_drv) \ 283 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver) 284 285 struct msi_msg { 286 uint32_t data; 287 }; 288 289 struct pci_msi_desc { 290 struct { 291 bool is_64; 292 } msi_attrib; 293 }; 294 295 struct msi_desc { 296 struct msi_msg msg; 297 struct pci_msi_desc pci; 298 }; 299 300 struct msix_entry { 301 int entry; 302 int vector; 303 }; 304 305 /* 306 * If we find drivers accessing this from multiple KPIs we may have to 307 * refcount objects of this structure. 308 */ 309 struct resource; 310 struct pci_mmio_region { 311 TAILQ_ENTRY(pci_mmio_region) next; 312 struct resource *res; 313 int rid; 314 int type; 315 }; 316 317 struct pci_dev { 318 struct device dev; 319 struct list_head links; 320 struct pci_driver *pdrv; 321 struct pci_bus *bus; 322 struct pci_dev *root; 323 pci_power_t current_state; 324 uint16_t device; 325 uint16_t vendor; 326 uint16_t subsystem_vendor; 327 uint16_t subsystem_device; 328 unsigned int irq; 329 unsigned int devfn; 330 uint32_t class; 331 uint8_t revision; 332 uint8_t msi_cap; 333 uint8_t msix_cap; 334 bool managed; /* devres "pcim_*(). */ 335 bool want_iomap_res; 336 bool msi_enabled; 337 bool msix_enabled; 338 phys_addr_t rom; 339 size_t romlen; 340 struct msi_desc **msi_desc; 341 char *path_name; 342 spinlock_t pcie_cap_lock; 343 344 TAILQ_HEAD(, pci_mmio_region) mmio; 345 }; 346 347 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 348 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 349 unsigned int flags); 350 bool pci_device_is_present(struct pci_dev *pdev); 351 352 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 353 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 354 void *linuxkpi_pci_iomap_range(struct pci_dev *pdev, int mmio_bar, 355 unsigned long mmio_off, unsigned long mmio_size); 356 void *linuxkpi_pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size); 357 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 358 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 359 const char *name); 360 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 361 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 362 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 363 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 364 int nreq); 365 366 /* Internal helper function(s). */ 367 struct pci_dev *lkpinew_pci_dev(device_t); 368 void lkpi_pci_devres_release(struct device *, void *); 369 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 370 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 371 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 372 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 373 374 #define pci_err(pdev, fmt, ...) \ 375 dev_err(&(pdev)->dev, fmt, __VA_ARGS__) 376 377 static inline bool 378 dev_is_pci(struct device *dev) 379 { 380 381 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 382 } 383 384 static inline uint16_t 385 pci_dev_id(struct pci_dev *pdev) 386 { 387 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 388 } 389 390 static inline int 391 pci_resource_type(struct pci_dev *pdev, int bar) 392 { 393 struct pci_map *pm; 394 395 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 396 if (!pm) 397 return (-1); 398 399 if (PCI_BAR_IO(pm->pm_value)) 400 return (SYS_RES_IOPORT); 401 else 402 return (SYS_RES_MEMORY); 403 } 404 405 /* 406 * All drivers just seem to want to inspect the type not flags. 407 */ 408 static inline int 409 pci_resource_flags(struct pci_dev *pdev, int bar) 410 { 411 int type; 412 413 type = pci_resource_type(pdev, bar); 414 if (type < 0) 415 return (0); 416 return (1 << type); 417 } 418 419 static inline const char * 420 pci_name(struct pci_dev *d) 421 { 422 return d->path_name; 423 } 424 425 static inline void * 426 pci_get_drvdata(struct pci_dev *pdev) 427 { 428 429 return dev_get_drvdata(&pdev->dev); 430 } 431 432 static inline void 433 pci_set_drvdata(struct pci_dev *pdev, void *data) 434 { 435 436 dev_set_drvdata(&pdev->dev, data); 437 } 438 439 static inline struct pci_dev * 440 pci_dev_get(struct pci_dev *pdev) 441 { 442 443 if (pdev != NULL) 444 get_device(&pdev->dev); 445 return (pdev); 446 } 447 448 static __inline void 449 pci_dev_put(struct pci_dev *pdev) 450 { 451 452 if (pdev != NULL) 453 put_device(&pdev->dev); 454 } 455 456 static inline int 457 pci_enable_device(struct pci_dev *pdev) 458 { 459 460 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 461 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 462 return (0); 463 } 464 465 static inline void 466 pci_disable_device(struct pci_dev *pdev) 467 { 468 469 pci_disable_busmaster(pdev->dev.bsddev); 470 } 471 472 static inline int 473 pci_set_master(struct pci_dev *pdev) 474 { 475 476 pci_enable_busmaster(pdev->dev.bsddev); 477 return (0); 478 } 479 480 static inline int 481 pci_set_power_state(struct pci_dev *pdev, int state) 482 { 483 484 pci_set_powerstate(pdev->dev.bsddev, state); 485 return (0); 486 } 487 488 static inline int 489 pci_clear_master(struct pci_dev *pdev) 490 { 491 492 pci_disable_busmaster(pdev->dev.bsddev); 493 return (0); 494 } 495 496 static inline bool 497 pci_is_root_bus(struct pci_bus *pbus) 498 { 499 500 return (pbus->self == NULL); 501 } 502 503 static inline struct pci_dev * 504 pci_upstream_bridge(struct pci_dev *pdev) 505 { 506 507 if (pci_is_root_bus(pdev->bus)) 508 return (NULL); 509 510 /* 511 * If we do not have a (proper) "upstream bridge" set, e.g., we point 512 * to ourselves, try to handle this case on the fly like we do 513 * for pcie_find_root_port(). 514 */ 515 if (pdev == pdev->bus->self) { 516 device_t bridge; 517 518 bridge = device_get_parent(pdev->dev.bsddev); 519 if (bridge == NULL) 520 goto done; 521 bridge = device_get_parent(bridge); 522 if (bridge == NULL) 523 goto done; 524 if (device_get_devclass(device_get_parent(bridge)) != 525 devclass_find("pci")) 526 goto done; 527 528 /* 529 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 530 * for it so it can be returned. 531 */ 532 pdev->bus->self = lkpinew_pci_dev(bridge); 533 } 534 done: 535 return (pdev->bus->self); 536 } 537 538 #define pci_release_region(pdev, bar) linuxkpi_pci_release_region(pdev, bar) 539 #define pci_release_regions(pdev) linuxkpi_pci_release_regions(pdev) 540 #define pci_request_regions(pdev, res_name) \ 541 linuxkpi_pci_request_regions(pdev, res_name) 542 543 static inline void 544 lkpi_pci_disable_msix(struct pci_dev *pdev) 545 { 546 547 pci_release_msi(pdev->dev.bsddev); 548 549 /* 550 * The MSIX IRQ numbers associated with this PCI device are no 551 * longer valid and might be re-assigned. Make sure 552 * lkpi_pci_find_irq_dev() does no longer see them by 553 * resetting their references to zero: 554 */ 555 pdev->dev.irq_start = 0; 556 pdev->dev.irq_end = 0; 557 pdev->msix_enabled = false; 558 } 559 /* Only for consistency. No conflict on that one. */ 560 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 561 562 static inline void 563 lkpi_pci_disable_msi(struct pci_dev *pdev) 564 { 565 566 pci_release_msi(pdev->dev.bsddev); 567 568 pdev->dev.irq_start = 0; 569 pdev->dev.irq_end = 0; 570 pdev->irq = pdev->dev.irq; 571 pdev->msi_enabled = false; 572 } 573 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 574 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 575 576 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 577 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 578 579 static inline bus_addr_t 580 pci_bus_address(struct pci_dev *pdev, int bar) 581 { 582 583 return (pci_resource_start(pdev, bar)); 584 } 585 586 #define PCI_CAP_ID_EXP PCIY_EXPRESS 587 #define PCI_CAP_ID_PCIX PCIY_PCIX 588 #define PCI_CAP_ID_AGP PCIY_AGP 589 #define PCI_CAP_ID_PM PCIY_PMG 590 591 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 592 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 593 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 594 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 595 #define PCI_EXP_LNKSTA PCIER_LINK_STA 596 597 static inline int 598 pci_find_capability(struct pci_dev *pdev, int capid) 599 { 600 int reg; 601 602 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 603 return (0); 604 return (reg); 605 } 606 607 static inline int pci_pcie_cap(struct pci_dev *dev) 608 { 609 return pci_find_capability(dev, PCI_CAP_ID_EXP); 610 } 611 612 static inline int 613 pci_find_ext_capability(struct pci_dev *pdev, int capid) 614 { 615 int reg; 616 617 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 618 return (0); 619 return (reg); 620 } 621 622 #define PCIM_PCAP_PME_SHIFT 11 623 static __inline bool 624 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 625 { 626 struct pci_devinfo *dinfo; 627 pcicfgregs *cfg; 628 629 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 630 return (false); 631 632 dinfo = device_get_ivars(pdev->dev.bsddev); 633 cfg = &dinfo->cfg; 634 635 if (cfg->pp.pp_cap == 0) 636 return (false); 637 638 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 639 return (true); 640 641 return (false); 642 } 643 644 static inline int 645 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 646 { 647 648 if (!pci_enable_aspm) 649 return (-EPERM); 650 651 return (-ENXIO); 652 } 653 654 static inline int 655 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 656 { 657 658 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 659 return (0); 660 } 661 662 static inline int 663 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 664 { 665 666 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 667 return (0); 668 } 669 670 static inline int 671 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 672 { 673 674 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 675 return (0); 676 } 677 678 static inline int 679 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 680 { 681 682 pci_write_config(pdev->dev.bsddev, where, val, 1); 683 return (0); 684 } 685 686 static inline int 687 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 688 { 689 690 pci_write_config(pdev->dev.bsddev, where, val, 2); 691 return (0); 692 } 693 694 static inline int 695 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 696 { 697 698 pci_write_config(pdev->dev.bsddev, where, val, 4); 699 return (0); 700 } 701 702 int linux_pci_register_driver(struct pci_driver *pdrv); 703 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 704 void linux_pci_unregister_driver(struct pci_driver *pdrv); 705 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 706 707 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 708 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 709 710 /* 711 * Enable msix, positive errors indicate actual number of available 712 * vectors. Negative errors are failures. 713 * 714 * NB: define added to prevent this definition of pci_enable_msix from 715 * clashing with the native FreeBSD version. 716 */ 717 #define pci_enable_msix(...) linuxkpi_pci_enable_msix(__VA_ARGS__) 718 719 #define pci_enable_msix_range(...) \ 720 linux_pci_enable_msix_range(__VA_ARGS__) 721 722 static inline int 723 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 724 int minvec, int maxvec) 725 { 726 int nvec = maxvec; 727 int rc; 728 729 if (maxvec < minvec) 730 return (-ERANGE); 731 732 do { 733 rc = pci_enable_msix(dev, entries, nvec); 734 if (rc < 0) { 735 return (rc); 736 } else if (rc > 0) { 737 if (rc < minvec) 738 return (-ENOSPC); 739 nvec = rc; 740 } 741 } while (rc); 742 return (nvec); 743 } 744 745 #define pci_enable_msi(pdev) \ 746 linux_pci_enable_msi(pdev) 747 748 static inline int 749 pci_enable_msi(struct pci_dev *pdev) 750 { 751 752 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 753 } 754 755 static inline int 756 pci_channel_offline(struct pci_dev *pdev) 757 { 758 759 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 760 } 761 762 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 763 { 764 return -ENODEV; 765 } 766 767 static inline void pci_disable_sriov(struct pci_dev *dev) 768 { 769 } 770 771 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \ 772 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) 773 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 774 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 775 #define pci_iounmap(pdev, res) linuxkpi_pci_iounmap(pdev, res) 776 777 static inline void 778 lkpi_pci_save_state(struct pci_dev *pdev) 779 { 780 781 pci_save_state(pdev->dev.bsddev); 782 } 783 784 static inline void 785 lkpi_pci_restore_state(struct pci_dev *pdev) 786 { 787 788 pci_restore_state(pdev->dev.bsddev); 789 } 790 791 #define pci_save_state(dev) lkpi_pci_save_state(dev) 792 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 793 794 static inline int 795 pci_reset_function(struct pci_dev *pdev) 796 { 797 798 return (-ENOSYS); 799 } 800 801 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 802 const struct pci_device_id _table[] __devinitdata 803 804 /* XXX This should not be necessary. */ 805 #define pcix_set_mmrbc(d, v) 0 806 #define pcix_get_max_mmrbc(d) 0 807 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 808 809 #define PCI_DMA_BIDIRECTIONAL 0 810 #define PCI_DMA_TODEVICE 1 811 #define PCI_DMA_FROMDEVICE 2 812 #define PCI_DMA_NONE 3 813 814 #define pci_pool dma_pool 815 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 816 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 817 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 818 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 819 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 820 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 821 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 822 _size, _vaddr, _dma_handle) 823 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 824 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 825 _sg, _nents, (enum dma_data_direction)_dir) 826 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 827 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 828 (_ptr), (_size), (enum dma_data_direction)_dir) 829 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 830 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 831 _addr, _size, (enum dma_data_direction)_dir) 832 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 833 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 834 _sg, _nents, (enum dma_data_direction)_dir) 835 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 836 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 837 _offset, _size, (enum dma_data_direction)_dir) 838 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 839 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 840 _dma_address, _size, (enum dma_data_direction)_dir) 841 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 842 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 843 dma_mapping_error(&(_pdev)->dev, _dma_addr) 844 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 845 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 846 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 847 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 848 #define pci_unmap_addr dma_unmap_addr 849 #define pci_unmap_addr_set dma_unmap_addr_set 850 #define pci_unmap_len dma_unmap_len 851 #define pci_unmap_len_set dma_unmap_len_set 852 853 typedef unsigned int __bitwise pci_channel_state_t; 854 typedef unsigned int __bitwise pci_ers_result_t; 855 856 enum pci_channel_state { 857 pci_channel_io_normal = 1, 858 pci_channel_io_frozen = 2, 859 pci_channel_io_perm_failure = 3, 860 }; 861 862 enum pci_ers_result { 863 PCI_ERS_RESULT_NONE = 1, 864 PCI_ERS_RESULT_CAN_RECOVER = 2, 865 PCI_ERS_RESULT_NEED_RESET = 3, 866 PCI_ERS_RESULT_DISCONNECT = 4, 867 PCI_ERS_RESULT_RECOVERED = 5, 868 }; 869 870 /* PCI bus error event callbacks */ 871 struct pci_error_handlers { 872 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 873 enum pci_channel_state error); 874 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 875 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 876 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 877 void (*resume)(struct pci_dev *dev); 878 }; 879 880 /* FreeBSD does not support SRIOV - yet */ 881 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 882 { 883 return dev; 884 } 885 886 static inline bool pci_is_pcie(struct pci_dev *dev) 887 { 888 return !!pci_pcie_cap(dev); 889 } 890 891 static inline u16 pcie_flags_reg(struct pci_dev *dev) 892 { 893 int pos; 894 u16 reg16; 895 896 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 897 if (!pos) 898 return 0; 899 900 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 901 902 return reg16; 903 } 904 905 static inline int pci_pcie_type(struct pci_dev *dev) 906 { 907 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 908 } 909 910 static inline int pcie_cap_version(struct pci_dev *dev) 911 { 912 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 913 } 914 915 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 916 { 917 int type = pci_pcie_type(dev); 918 919 return pcie_cap_version(dev) > 1 || 920 type == PCI_EXP_TYPE_ROOT_PORT || 921 type == PCI_EXP_TYPE_ENDPOINT || 922 type == PCI_EXP_TYPE_LEG_END; 923 } 924 925 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 926 { 927 return true; 928 } 929 930 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 931 { 932 int type = pci_pcie_type(dev); 933 934 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 935 (type == PCI_EXP_TYPE_DOWNSTREAM && 936 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 937 } 938 939 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 940 { 941 int type = pci_pcie_type(dev); 942 943 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 944 type == PCI_EXP_TYPE_RC_EC; 945 } 946 947 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 948 { 949 if (!pci_is_pcie(dev)) 950 return false; 951 952 switch (pos) { 953 case PCI_EXP_FLAGS_TYPE: 954 return true; 955 case PCI_EXP_DEVCAP: 956 case PCI_EXP_DEVCTL: 957 case PCI_EXP_DEVSTA: 958 return pcie_cap_has_devctl(dev); 959 case PCI_EXP_LNKCAP: 960 case PCI_EXP_LNKCTL: 961 case PCI_EXP_LNKSTA: 962 return pcie_cap_has_lnkctl(dev); 963 case PCI_EXP_SLTCAP: 964 case PCI_EXP_SLTCTL: 965 case PCI_EXP_SLTSTA: 966 return pcie_cap_has_sltctl(dev); 967 case PCI_EXP_RTCTL: 968 case PCI_EXP_RTCAP: 969 case PCI_EXP_RTSTA: 970 return pcie_cap_has_rtctl(dev); 971 case PCI_EXP_DEVCAP2: 972 case PCI_EXP_DEVCTL2: 973 case PCI_EXP_LNKCAP2: 974 case PCI_EXP_LNKCTL2: 975 case PCI_EXP_LNKSTA2: 976 return pcie_cap_version(dev) > 1; 977 default: 978 return false; 979 } 980 } 981 982 static inline int 983 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 984 { 985 *dst = 0; 986 if (pos & 3) 987 return -EINVAL; 988 989 if (!pcie_capability_reg_implemented(dev, pos)) 990 return -EINVAL; 991 992 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 993 } 994 995 static inline int 996 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 997 { 998 *dst = 0; 999 if (pos & 3) 1000 return -EINVAL; 1001 1002 if (!pcie_capability_reg_implemented(dev, pos)) 1003 return -EINVAL; 1004 1005 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1006 } 1007 1008 static inline int 1009 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1010 { 1011 if (pos & 1) 1012 return -EINVAL; 1013 1014 if (!pcie_capability_reg_implemented(dev, pos)) 1015 return 0; 1016 1017 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1018 } 1019 1020 static inline int 1021 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1022 uint16_t clear, uint16_t set) 1023 { 1024 int error; 1025 uint16_t v; 1026 1027 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1028 spin_lock(&dev->pcie_cap_lock); 1029 1030 error = pcie_capability_read_word(dev, pos, &v); 1031 if (error == 0) { 1032 v &= ~clear; 1033 v |= set; 1034 error = pcie_capability_write_word(dev, pos, v); 1035 } 1036 1037 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1038 spin_unlock(&dev->pcie_cap_lock); 1039 1040 return (error); 1041 } 1042 1043 static inline int 1044 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1045 { 1046 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1047 } 1048 1049 static inline int 1050 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1051 { 1052 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1053 } 1054 1055 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1056 enum pci_bus_speed *speed, enum pcie_link_width *width) 1057 { 1058 *speed = PCI_SPEED_UNKNOWN; 1059 *width = PCIE_LNK_WIDTH_UNKNOWN; 1060 return (0); 1061 } 1062 1063 static inline int 1064 pci_num_vf(struct pci_dev *dev) 1065 { 1066 return (0); 1067 } 1068 1069 static inline enum pci_bus_speed 1070 pcie_get_speed_cap(struct pci_dev *dev) 1071 { 1072 device_t root; 1073 uint32_t lnkcap, lnkcap2; 1074 int error, pos; 1075 1076 root = device_get_parent(dev->dev.bsddev); 1077 if (root == NULL) 1078 return (PCI_SPEED_UNKNOWN); 1079 root = device_get_parent(root); 1080 if (root == NULL) 1081 return (PCI_SPEED_UNKNOWN); 1082 root = device_get_parent(root); 1083 if (root == NULL) 1084 return (PCI_SPEED_UNKNOWN); 1085 1086 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1087 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1088 return (PCI_SPEED_UNKNOWN); 1089 1090 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1091 return (PCI_SPEED_UNKNOWN); 1092 1093 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1094 1095 if (lnkcap2) { /* PCIe r3.0-compliant */ 1096 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1097 return (PCIE_SPEED_2_5GT); 1098 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1099 return (PCIE_SPEED_5_0GT); 1100 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1101 return (PCIE_SPEED_8_0GT); 1102 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1103 return (PCIE_SPEED_16_0GT); 1104 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1105 return (PCIE_SPEED_32_0GT); 1106 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1107 return (PCIE_SPEED_64_0GT); 1108 } else { /* pre-r3.0 */ 1109 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1110 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1111 return (PCIE_SPEED_2_5GT); 1112 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1113 return (PCIE_SPEED_5_0GT); 1114 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1115 return (PCIE_SPEED_8_0GT); 1116 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1117 return (PCIE_SPEED_16_0GT); 1118 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1119 return (PCIE_SPEED_32_0GT); 1120 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1121 return (PCIE_SPEED_64_0GT); 1122 } 1123 return (PCI_SPEED_UNKNOWN); 1124 } 1125 1126 static inline enum pcie_link_width 1127 pcie_get_width_cap(struct pci_dev *dev) 1128 { 1129 uint32_t lnkcap; 1130 1131 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1132 if (lnkcap) 1133 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1134 1135 return (PCIE_LNK_WIDTH_UNKNOWN); 1136 } 1137 1138 static inline int 1139 pcie_get_mps(struct pci_dev *dev) 1140 { 1141 return (pci_get_max_payload(dev->dev.bsddev)); 1142 } 1143 1144 static inline uint32_t 1145 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1146 { 1147 1148 switch(spd) { 1149 case PCIE_SPEED_64_0GT: 1150 return (64000 * 128 / 130); 1151 case PCIE_SPEED_32_0GT: 1152 return (32000 * 128 / 130); 1153 case PCIE_SPEED_16_0GT: 1154 return (16000 * 128 / 130); 1155 case PCIE_SPEED_8_0GT: 1156 return (8000 * 128 / 130); 1157 case PCIE_SPEED_5_0GT: 1158 return (5000 * 8 / 10); 1159 case PCIE_SPEED_2_5GT: 1160 return (2500 * 8 / 10); 1161 default: 1162 return (0); 1163 } 1164 } 1165 1166 static inline uint32_t 1167 pcie_bandwidth_available(struct pci_dev *pdev, 1168 struct pci_dev **limiting, 1169 enum pci_bus_speed *speed, 1170 enum pcie_link_width *width) 1171 { 1172 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1173 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1174 1175 if (speed) 1176 *speed = nspeed; 1177 if (width) 1178 *width = nwidth; 1179 1180 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1181 } 1182 1183 static inline bool 1184 pcie_aspm_enabled(struct pci_dev *pdev) 1185 { 1186 return (false); 1187 } 1188 1189 static inline struct pci_dev * 1190 pcie_find_root_port(struct pci_dev *pdev) 1191 { 1192 device_t root; 1193 1194 if (pdev->root != NULL) 1195 return (pdev->root); 1196 1197 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1198 if (root == NULL) 1199 return (NULL); 1200 1201 pdev->root = lkpinew_pci_dev(root); 1202 return (pdev->root); 1203 } 1204 1205 /* This is needed when people rip out the device "HotPlug". */ 1206 static inline void 1207 pci_lock_rescan_remove(void) 1208 { 1209 } 1210 1211 static inline void 1212 pci_unlock_rescan_remove(void) 1213 { 1214 } 1215 1216 static __inline void 1217 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1218 { 1219 } 1220 1221 static inline int 1222 pci_rescan_bus(struct pci_bus *pbus) 1223 { 1224 device_t *devlist, parent; 1225 int devcount, error; 1226 1227 if (!device_is_attached(pbus->self->dev.bsddev)) 1228 return (0); 1229 /* pci_rescan_method() will work on the pcib (parent). */ 1230 error = BUS_RESCAN(pbus->self->dev.bsddev); 1231 if (error != 0) 1232 return (0); 1233 1234 parent = device_get_parent(pbus->self->dev.bsddev); 1235 error = device_get_children(parent, &devlist, &devcount); 1236 if (error != 0) 1237 return (0); 1238 if (devcount != 0) 1239 free(devlist, M_TEMP); 1240 1241 return (devcount); 1242 } 1243 1244 /* 1245 * The following functions can be used to attach/detach the LinuxKPI's 1246 * PCI device runtime. The pci_driver and pci_device_id pointer is 1247 * allowed to be NULL. Other pointers must be all valid. 1248 * The pci_dev structure should be zero-initialized before passed 1249 * to the linux_pci_attach_device function. 1250 */ 1251 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1252 const struct pci_device_id *, struct pci_dev *); 1253 extern int linux_pci_detach_device(struct pci_dev *); 1254 1255 static inline int 1256 pci_dev_present(const struct pci_device_id *cur) 1257 { 1258 while (cur != NULL && (cur->vendor || cur->device)) { 1259 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1260 return (1); 1261 } 1262 cur++; 1263 } 1264 return (0); 1265 } 1266 1267 static inline const struct pci_device_id * 1268 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 1269 { 1270 if (ids == NULL) 1271 return (NULL); 1272 1273 for (; 1274 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0; 1275 ids++) 1276 if ((ids->vendor == PCI_ANY_ID || 1277 ids->vendor == pdev->vendor) && 1278 (ids->device == PCI_ANY_ID || 1279 ids->device == pdev->device) && 1280 (ids->subvendor == PCI_ANY_ID || 1281 ids->subvendor == pdev->subsystem_vendor) && 1282 (ids->subdevice == PCI_ANY_ID || 1283 ids->subdevice == pdev->subsystem_device) && 1284 ((ids->class ^ pdev->class) & ids->class_mask) == 0) 1285 return (ids); 1286 1287 return (NULL); 1288 } 1289 1290 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1291 unsigned int bus, unsigned int devfn); 1292 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1293 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1294 1295 static inline int 1296 pci_domain_nr(struct pci_bus *pbus) 1297 { 1298 1299 return (pbus->domain); 1300 } 1301 1302 static inline int 1303 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1304 int pos, uint32_t *val, int len) 1305 { 1306 1307 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1308 return (0); 1309 } 1310 1311 static inline int 1312 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1313 { 1314 uint32_t tmp; 1315 int ret; 1316 1317 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1318 *val = (u16)tmp; 1319 return (ret); 1320 } 1321 1322 static inline int 1323 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1324 { 1325 uint32_t tmp; 1326 int ret; 1327 1328 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1329 *val = (u8)tmp; 1330 return (ret); 1331 } 1332 1333 static inline int 1334 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1335 uint32_t val, int size) 1336 { 1337 1338 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1339 return (0); 1340 } 1341 1342 static inline int 1343 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1344 uint8_t val) 1345 { 1346 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1347 } 1348 1349 static inline int 1350 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1351 uint16_t val) 1352 { 1353 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1354 } 1355 1356 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1357 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1358 1359 /* -------------------------------------------------------------------------- */ 1360 1361 #define pcim_enable_device(pdev) linuxkpi_pcim_enable_device(pdev) 1362 #define pcim_iomap_table(pdev) linuxkpi_pcim_iomap_table(pdev) 1363 #define pcim_iomap_regions(pdev, mask, name) \ 1364 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1365 1366 static inline int 1367 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1368 { 1369 uint32_t requests, req_mask; 1370 int bar, error; 1371 1372 /* Request all the BARs ("regions") we do not iomap. */ 1373 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1374 for (bar = requests = 0; requests != req_mask; bar++) { 1375 if ((req_mask & (1 << bar)) == 0) 1376 continue; 1377 error = pci_request_region(pdev, bar, name); 1378 if (error != 0 && error != -ENODEV) 1379 goto err; 1380 requests |= (1 << bar); 1381 } 1382 1383 error = pcim_iomap_regions(pdev, mask, name); 1384 if (error != 0) 1385 goto err; 1386 1387 return (0); 1388 1389 err: 1390 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1391 if ((requests & (1 << bar)) != 0) 1392 pci_release_region(pdev, bar); 1393 } 1394 1395 return (-EINVAL); 1396 } 1397 1398 /* 1399 * We cannot simply re-define pci_get_device() as we would normally do 1400 * and then hide it in linux_pci.c as too many semi-native drivers still 1401 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1402 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1403 */ 1404 static inline struct pci_dev * 1405 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1406 { 1407 1408 return (lkpi_pci_get_device(vendor, device, odev)); 1409 } 1410 1411 /* This is a FreeBSD extension so we can use bus_*(). */ 1412 static inline void 1413 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1414 { 1415 pdev->want_iomap_res = true; 1416 } 1417 1418 static inline bool 1419 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1420 { 1421 1422 return (false); 1423 } 1424 1425 static inline void * 1426 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1427 { 1428 1429 return (NULL); 1430 } 1431 1432 static inline void 1433 pci_ignore_hotplug(struct pci_dev *pdev) 1434 { 1435 } 1436 1437 static inline const char * 1438 pci_power_name(pci_power_t state) 1439 { 1440 int pstate = state + 1; 1441 1442 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1443 return (pci_power_names[pstate]); 1444 else 1445 return (pci_power_names[0]); 1446 } 1447 1448 static inline int 1449 pcie_get_readrq(struct pci_dev *dev) 1450 { 1451 u16 ctl; 1452 1453 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1454 return (-EINVAL); 1455 1456 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1457 } 1458 1459 static inline bool 1460 pci_is_enabled(struct pci_dev *pdev) 1461 { 1462 1463 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1464 PCIM_CMD_BUSMASTEREN) != 0); 1465 } 1466 1467 static inline int 1468 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1469 { 1470 1471 return (0); 1472 } 1473 1474 static inline int 1475 pci_assign_resource(struct pci_dev *pdev, int bar) 1476 { 1477 1478 return (0); 1479 } 1480 1481 static inline int 1482 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1483 { 1484 1485 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1486 if (vector != 0) 1487 return (-EINVAL); 1488 return (pdev->irq); 1489 } 1490 1491 if (pdev->msix_enabled || pdev->msi_enabled) { 1492 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1493 return (-EINVAL); 1494 return (pdev->dev.irq_start + vector); 1495 } 1496 1497 return (-ENXIO); 1498 } 1499 1500 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1501