1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/nv.h> 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 74 #define MODULE_DEVICE_TABLE(_bus, _table) \ 75 \ 76 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 77 DEVMETHOD_END \ 78 }; \ 79 \ 80 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 81 "lkpi_" #_bus #_table, \ 82 _ ## _bus ## _ ## _table ## _methods, \ 83 0 \ 84 }; \ 85 \ 86 static devclass_t _ ## _bus ## _ ## _table ## _devclass; \ 87 \ 88 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 89 _ ## _bus ## _ ## _table ## _devclass, 0, 0); \ 90 \ 91 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 92 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 93 94 #define PCI_ANY_ID -1U 95 96 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 97 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 98 #define PCI_FUNC(devfn) ((devfn) & 0x07) 99 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 100 101 #define PCI_VDEVICE(_vendor, _device) \ 102 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 103 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 104 #define PCI_DEVICE(_vendor, _device) \ 105 .vendor = (_vendor), .device = (_device), \ 106 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 107 108 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 109 110 #define PCI_VENDOR_ID PCIR_DEVVENDOR 111 #define PCI_COMMAND PCIR_COMMAND 112 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 115 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 116 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 117 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 118 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 119 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 120 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 121 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 122 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 123 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 124 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 125 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 126 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 127 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 128 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 129 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 130 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 131 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 132 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 133 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 134 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 135 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 136 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 137 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 138 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 139 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 140 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 141 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 142 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 143 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 144 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 145 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 146 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 147 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 148 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 149 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 150 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 151 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 152 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 153 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 154 #define PCI_EXP_LNKCTL2_TLS 0x000f 155 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 156 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 157 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 158 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 159 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 160 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 161 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 162 163 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 164 #define PCI_EXP_DEVSTA_TRPND 0x0020 165 166 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 167 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 168 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 169 170 enum pci_bus_speed { 171 PCI_SPEED_UNKNOWN = -1, 172 PCIE_SPEED_2_5GT, 173 PCIE_SPEED_5_0GT, 174 PCIE_SPEED_8_0GT, 175 PCIE_SPEED_16_0GT, 176 }; 177 178 enum pcie_link_width { 179 PCIE_LNK_WIDTH_RESRV = 0x00, 180 PCIE_LNK_X1 = 0x01, 181 PCIE_LNK_X2 = 0x02, 182 PCIE_LNK_X4 = 0x04, 183 PCIE_LNK_X8 = 0x08, 184 PCIE_LNK_X12 = 0x0c, 185 PCIE_LNK_X16 = 0x10, 186 PCIE_LNK_X32 = 0x20, 187 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 188 }; 189 190 #define PCIE_LINK_STATE_L0S 0x00000001 191 #define PCIE_LINK_STATE_L1 0x00000002 192 #define PCIE_LINK_STATE_CLKPM 0x00000004 193 194 typedef int pci_power_t; 195 196 #define PCI_D0 PCI_POWERSTATE_D0 197 #define PCI_D1 PCI_POWERSTATE_D1 198 #define PCI_D2 PCI_POWERSTATE_D2 199 #define PCI_D3hot PCI_POWERSTATE_D3 200 #define PCI_D3cold 4 201 202 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 203 204 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 205 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 206 207 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 208 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 209 210 #define PCI_L1SS_CTL1 0x8 211 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 212 213 #define PCI_IRQ_LEGACY 0x01 214 #define PCI_IRQ_MSI 0x02 215 #define PCI_IRQ_MSIX 0x04 216 217 struct pci_dev; 218 219 struct pci_driver { 220 struct list_head node; 221 char *name; 222 const struct pci_device_id *id_table; 223 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 224 void (*remove)(struct pci_dev *dev); 225 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 226 int (*resume) (struct pci_dev *dev); /* Device woken up */ 227 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 228 driver_t bsddriver; 229 devclass_t bsdclass; 230 struct device_driver driver; 231 const struct pci_error_handlers *err_handler; 232 bool isdrm; 233 int bsd_probe_return; 234 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 235 const nvlist_t *pf_config); 236 void (*bsd_iov_uninit)(device_t dev); 237 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 238 const nvlist_t *vf_config); 239 }; 240 241 struct pci_bus { 242 struct pci_dev *self; 243 int domain; 244 int number; 245 }; 246 247 extern struct list_head pci_drivers; 248 extern struct list_head pci_devices; 249 extern spinlock_t pci_lock; 250 251 #define __devexit_p(x) x 252 253 #define module_pci_driver(_driver) \ 254 \ 255 static inline int \ 256 _pci_init(void) \ 257 { \ 258 \ 259 return (linux_pci_register_driver(&_driver)); \ 260 } \ 261 \ 262 static inline void \ 263 _pci_exit(void) \ 264 { \ 265 \ 266 linux_pci_unregister_driver(&_driver); \ 267 } \ 268 \ 269 module_init(_pci_init); \ 270 module_exit(_pci_exit) 271 272 /* 273 * If we find drivers accessing this from multiple KPIs we may have to 274 * refcount objects of this structure. 275 */ 276 struct pci_mmio_region { 277 TAILQ_ENTRY(pci_mmio_region) next; 278 struct resource *res; 279 int rid; 280 int type; 281 }; 282 283 struct pci_dev { 284 struct device dev; 285 struct list_head links; 286 struct pci_driver *pdrv; 287 struct pci_bus *bus; 288 struct pci_dev *root; 289 uint16_t device; 290 uint16_t vendor; 291 uint16_t subsystem_vendor; 292 uint16_t subsystem_device; 293 unsigned int irq; 294 unsigned int devfn; 295 uint32_t class; 296 uint8_t revision; 297 bool managed; /* devres "pcim_*(). */ 298 bool want_iomap_res; 299 bool msi_enabled; 300 bool msix_enabled; 301 phys_addr_t rom; 302 size_t romlen; 303 304 TAILQ_HEAD(, pci_mmio_region) mmio; 305 }; 306 307 /* We need some meta-struct to keep track of these for devres. */ 308 struct pci_devres { 309 bool enable_io; 310 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 311 uint8_t region_mask; 312 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 313 }; 314 struct pcim_iomap_devres { 315 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 316 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 317 }; 318 319 /* Internal helper function(s). */ 320 struct pci_dev *lkpinew_pci_dev(device_t); 321 void lkpi_pci_devres_release(struct device *, void *); 322 void lkpi_pcim_iomap_table_release(struct device *, void *); 323 324 static inline int 325 pci_resource_type(struct pci_dev *pdev, int bar) 326 { 327 struct pci_map *pm; 328 329 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 330 if (!pm) 331 return (-1); 332 333 if (PCI_BAR_IO(pm->pm_value)) 334 return (SYS_RES_IOPORT); 335 else 336 return (SYS_RES_MEMORY); 337 } 338 339 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 340 struct resource_list *rl, int type, int rid); 341 342 static inline struct resource_list_entry * 343 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 344 { 345 struct pci_devinfo *dinfo; 346 struct resource_list *rl; 347 struct resource_list_entry *rle; 348 349 dinfo = device_get_ivars(pdev->dev.bsddev); 350 rl = &dinfo->resources; 351 rle = resource_list_find(rl, type, rid); 352 /* Reserve resources for this BAR if needed. */ 353 if (rle == NULL && reserve_bar) 354 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 355 return (rle); 356 } 357 358 static inline struct resource_list_entry * 359 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 360 { 361 int type; 362 363 type = pci_resource_type(pdev, bar); 364 if (type < 0) 365 return (NULL); 366 bar = PCIR_BAR(bar); 367 return (linux_pci_get_rle(pdev, type, bar, reserve)); 368 } 369 370 static inline struct device * 371 linux_pci_find_irq_dev(unsigned int irq) 372 { 373 struct pci_dev *pdev; 374 struct device *found; 375 376 found = NULL; 377 spin_lock(&pci_lock); 378 list_for_each_entry(pdev, &pci_devices, links) { 379 if (irq == pdev->dev.irq || 380 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 381 found = &pdev->dev; 382 break; 383 } 384 } 385 spin_unlock(&pci_lock); 386 return (found); 387 } 388 389 /* 390 * All drivers just seem to want to inspect the type not flags. 391 */ 392 static inline int 393 pci_resource_flags(struct pci_dev *pdev, int bar) 394 { 395 int type; 396 397 type = pci_resource_type(pdev, bar); 398 if (type < 0) 399 return (0); 400 return (1 << type); 401 } 402 403 static inline const char * 404 pci_name(struct pci_dev *d) 405 { 406 407 return device_get_desc(d->dev.bsddev); 408 } 409 410 static inline void * 411 pci_get_drvdata(struct pci_dev *pdev) 412 { 413 414 return dev_get_drvdata(&pdev->dev); 415 } 416 417 static inline void 418 pci_set_drvdata(struct pci_dev *pdev, void *data) 419 { 420 421 dev_set_drvdata(&pdev->dev, data); 422 } 423 424 static inline struct pci_dev * 425 pci_dev_get(struct pci_dev *pdev) 426 { 427 428 if (pdev != NULL) 429 get_device(&pdev->dev); 430 return (pdev); 431 } 432 433 static __inline void 434 pci_dev_put(struct pci_dev *pdev) 435 { 436 437 if (pdev != NULL) 438 put_device(&pdev->dev); 439 } 440 441 static inline int 442 pci_enable_device(struct pci_dev *pdev) 443 { 444 445 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 446 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 447 return (0); 448 } 449 450 static inline void 451 pci_disable_device(struct pci_dev *pdev) 452 { 453 454 pci_disable_busmaster(pdev->dev.bsddev); 455 } 456 457 static inline int 458 pci_set_master(struct pci_dev *pdev) 459 { 460 461 pci_enable_busmaster(pdev->dev.bsddev); 462 return (0); 463 } 464 465 static inline int 466 pci_set_power_state(struct pci_dev *pdev, int state) 467 { 468 469 pci_set_powerstate(pdev->dev.bsddev, state); 470 return (0); 471 } 472 473 static inline int 474 pci_clear_master(struct pci_dev *pdev) 475 { 476 477 pci_disable_busmaster(pdev->dev.bsddev); 478 return (0); 479 } 480 481 static inline bool 482 pci_is_root_bus(struct pci_bus *pbus) 483 { 484 485 return (pbus->self == NULL); 486 } 487 488 static inline struct pci_dev * 489 pci_upstream_bridge(struct pci_dev *pdev) 490 { 491 492 if (pci_is_root_bus(pdev->bus)) 493 return (NULL); 494 495 /* 496 * If we do not have a (proper) "upstream bridge" set, e.g., we point 497 * to ourselves, try to handle this case on the fly like we do 498 * for pcie_find_root_port(). 499 */ 500 if (pdev == pdev->bus->self) { 501 device_t bridge; 502 503 bridge = device_get_parent(pdev->dev.bsddev); 504 if (bridge == NULL) 505 goto done; 506 bridge = device_get_parent(bridge); 507 if (bridge == NULL) 508 goto done; 509 if (device_get_devclass(device_get_parent(bridge)) != 510 devclass_find("pci")) 511 goto done; 512 513 /* 514 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 515 * for it so it can be returned. 516 */ 517 pdev->bus->self = lkpinew_pci_dev(bridge); 518 } 519 done: 520 return (pdev->bus->self); 521 } 522 523 static inline struct pci_devres * 524 lkpi_pci_devres_get_alloc(struct pci_dev *pdev) 525 { 526 struct pci_devres *dr; 527 528 dr = lkpi_devres_find(&pdev->dev, lkpi_pci_devres_release, NULL, NULL); 529 if (dr == NULL) { 530 dr = lkpi_devres_alloc(lkpi_pci_devres_release, sizeof(*dr), 531 GFP_KERNEL | __GFP_ZERO); 532 if (dr != NULL) 533 lkpi_devres_add(&pdev->dev, dr); 534 } 535 536 return (dr); 537 } 538 static inline struct pci_devres * 539 lkpi_pci_devres_find(struct pci_dev *pdev) 540 { 541 542 if (!pdev->managed) 543 return (NULL); 544 545 return (lkpi_pci_devres_get_alloc(pdev)); 546 } 547 548 static inline int 549 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 550 { 551 struct resource *res; 552 struct pci_devres *dr; 553 struct pci_mmio_region *mmio; 554 int rid; 555 int type; 556 557 type = pci_resource_type(pdev, bar); 558 if (type < 0) 559 return (-ENODEV); 560 rid = PCIR_BAR(bar); 561 res = bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 562 RF_ACTIVE|RF_SHAREABLE); 563 if (res == NULL) { 564 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 565 "bar %d type %d rid %d\n", 566 __func__, bar, type, PCIR_BAR(bar)); 567 return (-ENODEV); 568 } 569 570 /* 571 * It seems there is an implicit devres tracking on these if the device 572 * is managed; otherwise the resources are not automatiaclly freed on 573 * FreeBSD/LinuxKPI tough they should be/are expected to be by Linux 574 * drivers. 575 */ 576 dr = lkpi_pci_devres_find(pdev); 577 if (dr != NULL) { 578 dr->region_mask |= (1 << bar); 579 dr->region_table[bar] = res; 580 } 581 582 /* Even if the device is not managed we need to track it for iomap. */ 583 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 584 mmio->rid = PCIR_BAR(bar); 585 mmio->type = type; 586 mmio->res = res; 587 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 588 589 return (0); 590 } 591 592 static inline void 593 pci_release_region(struct pci_dev *pdev, int bar) 594 { 595 struct resource_list_entry *rle; 596 struct pci_devres *dr; 597 struct pci_mmio_region *mmio, *p; 598 599 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 600 return; 601 602 /* 603 * As we implicitly track the requests we also need to clear them on 604 * release. Do clear before resource release. 605 */ 606 dr = lkpi_pci_devres_find(pdev); 607 if (dr != NULL) { 608 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 609 " region_table res %p != rel->res %p\n", __func__, pdev, 610 bar, dr->region_table[bar], rle->res)); 611 dr->region_table[bar] = NULL; 612 dr->region_mask &= ~(1 << bar); 613 } 614 615 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 616 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 617 continue; 618 TAILQ_REMOVE(&pdev->mmio, mmio, next); 619 free(mmio, M_DEVBUF); 620 } 621 622 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 623 } 624 625 static inline void 626 pci_release_regions(struct pci_dev *pdev) 627 { 628 int i; 629 630 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 631 pci_release_region(pdev, i); 632 } 633 634 static inline int 635 pci_request_regions(struct pci_dev *pdev, const char *res_name) 636 { 637 int error; 638 int i; 639 640 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 641 error = pci_request_region(pdev, i, res_name); 642 if (error && error != -ENODEV) { 643 pci_release_regions(pdev); 644 return (error); 645 } 646 } 647 return (0); 648 } 649 650 static inline void 651 lkpi_pci_disable_msix(struct pci_dev *pdev) 652 { 653 654 pci_release_msi(pdev->dev.bsddev); 655 656 /* 657 * The MSIX IRQ numbers associated with this PCI device are no 658 * longer valid and might be re-assigned. Make sure 659 * linux_pci_find_irq_dev() does no longer see them by 660 * resetting their references to zero: 661 */ 662 pdev->dev.irq_start = 0; 663 pdev->dev.irq_end = 0; 664 pdev->msix_enabled = false; 665 } 666 /* Only for consistency. No conflict on that one. */ 667 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 668 669 static inline void 670 lkpi_pci_disable_msi(struct pci_dev *pdev) 671 { 672 673 pci_release_msi(pdev->dev.bsddev); 674 675 pdev->dev.irq_start = 0; 676 pdev->dev.irq_end = 0; 677 pdev->irq = pdev->dev.irq; 678 pdev->msi_enabled = false; 679 } 680 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 681 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 682 683 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 684 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 685 686 static inline bus_addr_t 687 pci_bus_address(struct pci_dev *pdev, int bar) 688 { 689 690 return (pci_resource_start(pdev, bar)); 691 } 692 693 #define PCI_CAP_ID_EXP PCIY_EXPRESS 694 #define PCI_CAP_ID_PCIX PCIY_PCIX 695 #define PCI_CAP_ID_AGP PCIY_AGP 696 #define PCI_CAP_ID_PM PCIY_PMG 697 698 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 699 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 700 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 701 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 702 #define PCI_EXP_LNKSTA PCIER_LINK_STA 703 704 static inline int 705 pci_find_capability(struct pci_dev *pdev, int capid) 706 { 707 int reg; 708 709 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 710 return (0); 711 return (reg); 712 } 713 714 static inline int pci_pcie_cap(struct pci_dev *dev) 715 { 716 return pci_find_capability(dev, PCI_CAP_ID_EXP); 717 } 718 719 static inline int 720 pci_find_ext_capability(struct pci_dev *pdev, int capid) 721 { 722 int reg; 723 724 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 725 return (0); 726 return (reg); 727 } 728 729 #define PCIM_PCAP_PME_SHIFT 11 730 static __inline bool 731 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 732 { 733 struct pci_devinfo *dinfo; 734 pcicfgregs *cfg; 735 736 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 737 return (false); 738 739 dinfo = device_get_ivars(pdev->dev.bsddev); 740 cfg = &dinfo->cfg; 741 742 if (cfg->pp.pp_cap == 0) 743 return (false); 744 745 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 746 return (true); 747 748 return (false); 749 } 750 751 static inline int 752 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 753 { 754 755 if (!pci_enable_aspm) 756 return (-EPERM); 757 758 return (-ENXIO); 759 } 760 761 static inline int 762 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 763 { 764 765 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 766 return (0); 767 } 768 769 static inline int 770 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 771 { 772 773 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 774 return (0); 775 } 776 777 static inline int 778 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 779 { 780 781 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 782 return (0); 783 } 784 785 static inline int 786 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 787 { 788 789 pci_write_config(pdev->dev.bsddev, where, val, 1); 790 return (0); 791 } 792 793 static inline int 794 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 795 { 796 797 pci_write_config(pdev->dev.bsddev, where, val, 2); 798 return (0); 799 } 800 801 static inline int 802 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 803 { 804 805 pci_write_config(pdev->dev.bsddev, where, val, 4); 806 return (0); 807 } 808 809 int linux_pci_register_driver(struct pci_driver *pdrv); 810 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 811 void linux_pci_unregister_driver(struct pci_driver *pdrv); 812 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 813 814 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 815 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 816 817 struct msix_entry { 818 int entry; 819 int vector; 820 }; 821 822 /* 823 * Enable msix, positive errors indicate actual number of available 824 * vectors. Negative errors are failures. 825 * 826 * NB: define added to prevent this definition of pci_enable_msix from 827 * clashing with the native FreeBSD version. 828 */ 829 #define pci_enable_msix(...) \ 830 linux_pci_enable_msix(__VA_ARGS__) 831 832 static inline int 833 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 834 { 835 struct resource_list_entry *rle; 836 int error; 837 int avail; 838 int i; 839 840 avail = pci_msix_count(pdev->dev.bsddev); 841 if (avail < nreq) { 842 if (avail == 0) 843 return -EINVAL; 844 return avail; 845 } 846 avail = nreq; 847 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 848 return error; 849 /* 850 * Handle case where "pci_alloc_msix()" may allocate less 851 * interrupts than available and return with no error: 852 */ 853 if (avail < nreq) { 854 pci_release_msi(pdev->dev.bsddev); 855 return avail; 856 } 857 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 858 pdev->dev.irq_start = rle->start; 859 pdev->dev.irq_end = rle->start + avail; 860 for (i = 0; i < nreq; i++) 861 entries[i].vector = pdev->dev.irq_start + i; 862 pdev->msix_enabled = true; 863 return (0); 864 } 865 866 #define pci_enable_msix_range(...) \ 867 linux_pci_enable_msix_range(__VA_ARGS__) 868 869 static inline int 870 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 871 int minvec, int maxvec) 872 { 873 int nvec = maxvec; 874 int rc; 875 876 if (maxvec < minvec) 877 return (-ERANGE); 878 879 do { 880 rc = pci_enable_msix(dev, entries, nvec); 881 if (rc < 0) { 882 return (rc); 883 } else if (rc > 0) { 884 if (rc < minvec) 885 return (-ENOSPC); 886 nvec = rc; 887 } 888 } while (rc); 889 return (nvec); 890 } 891 892 #define pci_enable_msi(pdev) \ 893 linux_pci_enable_msi(pdev) 894 895 static inline int 896 pci_enable_msi(struct pci_dev *pdev) 897 { 898 struct resource_list_entry *rle; 899 int error; 900 int avail; 901 902 avail = pci_msi_count(pdev->dev.bsddev); 903 if (avail < 1) 904 return -EINVAL; 905 906 avail = 1; /* this function only enable one MSI IRQ */ 907 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 908 return error; 909 910 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 911 pdev->dev.irq_start = rle->start; 912 pdev->dev.irq_end = rle->start + avail; 913 pdev->irq = rle->start; 914 pdev->msi_enabled = true; 915 return (0); 916 } 917 918 static inline int 919 pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 920 unsigned int flags) 921 { 922 int error; 923 924 if (flags & PCI_IRQ_MSIX) { 925 struct msix_entry *entries; 926 int i; 927 928 entries = kcalloc(maxv, sizeof(*entries), GFP_KERNEL); 929 if (entries == NULL) { 930 error = -ENOMEM; 931 goto out; 932 } 933 for (i = 0; i < maxv; ++i) 934 entries[i].entry = i; 935 error = pci_enable_msix(pdev, entries, maxv); 936 out: 937 kfree(entries); 938 if (error == 0 && pdev->msix_enabled) 939 return (pdev->dev.irq_end - pdev->dev.irq_start); 940 } 941 if (flags & PCI_IRQ_MSI) { 942 error = pci_enable_msi(pdev); 943 if (error == 0 && pdev->msi_enabled) 944 return (pdev->dev.irq_end - pdev->dev.irq_start); 945 } 946 if (flags & PCI_IRQ_LEGACY) { 947 if (pdev->irq) 948 return (1); 949 } 950 951 return (-EINVAL); 952 } 953 954 static inline int 955 pci_channel_offline(struct pci_dev *pdev) 956 { 957 958 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 959 } 960 961 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 962 { 963 return -ENODEV; 964 } 965 static inline void pci_disable_sriov(struct pci_dev *dev) 966 { 967 } 968 969 static inline struct resource * 970 _lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size __unused) 971 { 972 struct pci_mmio_region *mmio, *p; 973 int type; 974 975 type = pci_resource_type(pdev, bar); 976 if (type < 0) { 977 device_printf(pdev->dev.bsddev, "%s: bar %d type %d\n", 978 __func__, bar, type); 979 return (NULL); 980 } 981 982 /* 983 * Check for duplicate mappings. 984 * This can happen if a driver calls pci_request_region() first. 985 */ 986 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 987 if (mmio->type == type && mmio->rid == PCIR_BAR(bar)) { 988 return (mmio->res); 989 } 990 } 991 992 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 993 mmio->rid = PCIR_BAR(bar); 994 mmio->type = type; 995 mmio->res = bus_alloc_resource_any(pdev->dev.bsddev, mmio->type, 996 &mmio->rid, RF_ACTIVE|RF_SHAREABLE); 997 if (mmio->res == NULL) { 998 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 999 "bar %d type %d rid %d\n", 1000 __func__, bar, type, PCIR_BAR(bar)); 1001 free(mmio, M_DEVBUF); 1002 return (NULL); 1003 } 1004 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 1005 1006 return (mmio->res); 1007 } 1008 1009 static inline void * 1010 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 1011 { 1012 struct resource *res; 1013 1014 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 1015 if (res == NULL) 1016 return (NULL); 1017 /* This is a FreeBSD extension so we can use bus_*(). */ 1018 if (pdev->want_iomap_res) 1019 return (res); 1020 return ((void *)rman_get_bushandle(res)); 1021 } 1022 1023 static inline void 1024 pci_iounmap(struct pci_dev *pdev, void *res) 1025 { 1026 struct pci_mmio_region *mmio, *p; 1027 1028 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 1029 if (res != (void *)rman_get_bushandle(mmio->res)) 1030 continue; 1031 bus_release_resource(pdev->dev.bsddev, 1032 mmio->type, mmio->rid, mmio->res); 1033 TAILQ_REMOVE(&pdev->mmio, mmio, next); 1034 free(mmio, M_DEVBUF); 1035 return; 1036 } 1037 } 1038 1039 static inline void 1040 lkpi_pci_save_state(struct pci_dev *pdev) 1041 { 1042 1043 pci_save_state(pdev->dev.bsddev); 1044 } 1045 1046 static inline void 1047 lkpi_pci_restore_state(struct pci_dev *pdev) 1048 { 1049 1050 pci_restore_state(pdev->dev.bsddev); 1051 } 1052 1053 #define pci_save_state(dev) lkpi_pci_save_state(dev) 1054 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 1055 1056 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 1057 const struct pci_device_id _table[] __devinitdata 1058 1059 /* XXX This should not be necessary. */ 1060 #define pcix_set_mmrbc(d, v) 0 1061 #define pcix_get_max_mmrbc(d) 0 1062 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 1063 1064 #define PCI_DMA_BIDIRECTIONAL 0 1065 #define PCI_DMA_TODEVICE 1 1066 #define PCI_DMA_FROMDEVICE 2 1067 #define PCI_DMA_NONE 3 1068 1069 #define pci_pool dma_pool 1070 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 1071 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 1072 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 1073 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 1074 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 1075 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 1076 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1077 _size, _vaddr, _dma_handle) 1078 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 1079 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1080 _sg, _nents, (enum dma_data_direction)_dir) 1081 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 1082 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1083 (_ptr), (_size), (enum dma_data_direction)_dir) 1084 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 1085 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1086 _addr, _size, (enum dma_data_direction)_dir) 1087 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 1088 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1089 _sg, _nents, (enum dma_data_direction)_dir) 1090 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 1091 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 1092 _offset, _size, (enum dma_data_direction)_dir) 1093 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 1094 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1095 _dma_address, _size, (enum dma_data_direction)_dir) 1096 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1097 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1098 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1099 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1100 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1101 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1102 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1103 #define pci_unmap_addr dma_unmap_addr 1104 #define pci_unmap_addr_set dma_unmap_addr_set 1105 #define pci_unmap_len dma_unmap_len 1106 #define pci_unmap_len_set dma_unmap_len_set 1107 1108 typedef unsigned int __bitwise pci_channel_state_t; 1109 typedef unsigned int __bitwise pci_ers_result_t; 1110 1111 enum pci_channel_state { 1112 pci_channel_io_normal = 1, 1113 pci_channel_io_frozen = 2, 1114 pci_channel_io_perm_failure = 3, 1115 }; 1116 1117 enum pci_ers_result { 1118 PCI_ERS_RESULT_NONE = 1, 1119 PCI_ERS_RESULT_CAN_RECOVER = 2, 1120 PCI_ERS_RESULT_NEED_RESET = 3, 1121 PCI_ERS_RESULT_DISCONNECT = 4, 1122 PCI_ERS_RESULT_RECOVERED = 5, 1123 }; 1124 1125 /* PCI bus error event callbacks */ 1126 struct pci_error_handlers { 1127 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1128 enum pci_channel_state error); 1129 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1130 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1131 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1132 void (*resume)(struct pci_dev *dev); 1133 }; 1134 1135 /* FreeBSD does not support SRIOV - yet */ 1136 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1137 { 1138 return dev; 1139 } 1140 1141 static inline bool pci_is_pcie(struct pci_dev *dev) 1142 { 1143 return !!pci_pcie_cap(dev); 1144 } 1145 1146 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1147 { 1148 int pos; 1149 u16 reg16; 1150 1151 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1152 if (!pos) 1153 return 0; 1154 1155 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1156 1157 return reg16; 1158 } 1159 1160 static inline int pci_pcie_type(struct pci_dev *dev) 1161 { 1162 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1163 } 1164 1165 static inline int pcie_cap_version(struct pci_dev *dev) 1166 { 1167 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1168 } 1169 1170 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1171 { 1172 int type = pci_pcie_type(dev); 1173 1174 return pcie_cap_version(dev) > 1 || 1175 type == PCI_EXP_TYPE_ROOT_PORT || 1176 type == PCI_EXP_TYPE_ENDPOINT || 1177 type == PCI_EXP_TYPE_LEG_END; 1178 } 1179 1180 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1181 { 1182 return true; 1183 } 1184 1185 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1186 { 1187 int type = pci_pcie_type(dev); 1188 1189 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1190 (type == PCI_EXP_TYPE_DOWNSTREAM && 1191 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1192 } 1193 1194 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1195 { 1196 int type = pci_pcie_type(dev); 1197 1198 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1199 type == PCI_EXP_TYPE_RC_EC; 1200 } 1201 1202 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1203 { 1204 if (!pci_is_pcie(dev)) 1205 return false; 1206 1207 switch (pos) { 1208 case PCI_EXP_FLAGS_TYPE: 1209 return true; 1210 case PCI_EXP_DEVCAP: 1211 case PCI_EXP_DEVCTL: 1212 case PCI_EXP_DEVSTA: 1213 return pcie_cap_has_devctl(dev); 1214 case PCI_EXP_LNKCAP: 1215 case PCI_EXP_LNKCTL: 1216 case PCI_EXP_LNKSTA: 1217 return pcie_cap_has_lnkctl(dev); 1218 case PCI_EXP_SLTCAP: 1219 case PCI_EXP_SLTCTL: 1220 case PCI_EXP_SLTSTA: 1221 return pcie_cap_has_sltctl(dev); 1222 case PCI_EXP_RTCTL: 1223 case PCI_EXP_RTCAP: 1224 case PCI_EXP_RTSTA: 1225 return pcie_cap_has_rtctl(dev); 1226 case PCI_EXP_DEVCAP2: 1227 case PCI_EXP_DEVCTL2: 1228 case PCI_EXP_LNKCAP2: 1229 case PCI_EXP_LNKCTL2: 1230 case PCI_EXP_LNKSTA2: 1231 return pcie_cap_version(dev) > 1; 1232 default: 1233 return false; 1234 } 1235 } 1236 1237 static inline int 1238 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1239 { 1240 if (pos & 3) 1241 return -EINVAL; 1242 1243 if (!pcie_capability_reg_implemented(dev, pos)) 1244 return -EINVAL; 1245 1246 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1247 } 1248 1249 static inline int 1250 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1251 { 1252 if (pos & 3) 1253 return -EINVAL; 1254 1255 if (!pcie_capability_reg_implemented(dev, pos)) 1256 return -EINVAL; 1257 1258 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1259 } 1260 1261 static inline int 1262 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1263 { 1264 if (pos & 1) 1265 return -EINVAL; 1266 1267 if (!pcie_capability_reg_implemented(dev, pos)) 1268 return 0; 1269 1270 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1271 } 1272 1273 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1274 enum pci_bus_speed *speed, enum pcie_link_width *width) 1275 { 1276 *speed = PCI_SPEED_UNKNOWN; 1277 *width = PCIE_LNK_WIDTH_UNKNOWN; 1278 return (0); 1279 } 1280 1281 static inline int 1282 pci_num_vf(struct pci_dev *dev) 1283 { 1284 return (0); 1285 } 1286 1287 static inline enum pci_bus_speed 1288 pcie_get_speed_cap(struct pci_dev *dev) 1289 { 1290 device_t root; 1291 uint32_t lnkcap, lnkcap2; 1292 int error, pos; 1293 1294 root = device_get_parent(dev->dev.bsddev); 1295 if (root == NULL) 1296 return (PCI_SPEED_UNKNOWN); 1297 root = device_get_parent(root); 1298 if (root == NULL) 1299 return (PCI_SPEED_UNKNOWN); 1300 root = device_get_parent(root); 1301 if (root == NULL) 1302 return (PCI_SPEED_UNKNOWN); 1303 1304 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1305 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1306 return (PCI_SPEED_UNKNOWN); 1307 1308 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1309 return (PCI_SPEED_UNKNOWN); 1310 1311 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1312 1313 if (lnkcap2) { /* PCIe r3.0-compliant */ 1314 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1315 return (PCIE_SPEED_2_5GT); 1316 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1317 return (PCIE_SPEED_5_0GT); 1318 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1319 return (PCIE_SPEED_8_0GT); 1320 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1321 return (PCIE_SPEED_16_0GT); 1322 } else { /* pre-r3.0 */ 1323 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1324 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1325 return (PCIE_SPEED_2_5GT); 1326 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1327 return (PCIE_SPEED_5_0GT); 1328 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1329 return (PCIE_SPEED_8_0GT); 1330 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1331 return (PCIE_SPEED_16_0GT); 1332 } 1333 return (PCI_SPEED_UNKNOWN); 1334 } 1335 1336 static inline enum pcie_link_width 1337 pcie_get_width_cap(struct pci_dev *dev) 1338 { 1339 uint32_t lnkcap; 1340 1341 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1342 if (lnkcap) 1343 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1344 1345 return (PCIE_LNK_WIDTH_UNKNOWN); 1346 } 1347 1348 static inline int 1349 pcie_get_mps(struct pci_dev *dev) 1350 { 1351 return (pci_get_max_payload(dev->dev.bsddev)); 1352 } 1353 1354 static inline uint32_t 1355 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1356 { 1357 1358 switch(spd) { 1359 case PCIE_SPEED_16_0GT: 1360 return (16000 * 128 / 130); 1361 case PCIE_SPEED_8_0GT: 1362 return (8000 * 128 / 130); 1363 case PCIE_SPEED_5_0GT: 1364 return (5000 * 8 / 10); 1365 case PCIE_SPEED_2_5GT: 1366 return (2500 * 8 / 10); 1367 default: 1368 return (0); 1369 } 1370 } 1371 1372 static inline uint32_t 1373 pcie_bandwidth_available(struct pci_dev *pdev, 1374 struct pci_dev **limiting, 1375 enum pci_bus_speed *speed, 1376 enum pcie_link_width *width) 1377 { 1378 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1379 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1380 1381 if (speed) 1382 *speed = nspeed; 1383 if (width) 1384 *width = nwidth; 1385 1386 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1387 } 1388 1389 static inline struct pci_dev * 1390 pcie_find_root_port(struct pci_dev *pdev) 1391 { 1392 device_t root; 1393 1394 if (pdev->root != NULL) 1395 return (pdev->root); 1396 1397 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1398 if (root == NULL) 1399 return (NULL); 1400 1401 pdev->root = lkpinew_pci_dev(root); 1402 return (pdev->root); 1403 } 1404 1405 /* This is needed when people rip out the device "HotPlug". */ 1406 static inline void 1407 pci_lock_rescan_remove(void) 1408 { 1409 } 1410 1411 static inline void 1412 pci_unlock_rescan_remove(void) 1413 { 1414 } 1415 1416 static __inline void 1417 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1418 { 1419 } 1420 1421 /* 1422 * The following functions can be used to attach/detach the LinuxKPI's 1423 * PCI device runtime. The pci_driver and pci_device_id pointer is 1424 * allowed to be NULL. Other pointers must be all valid. 1425 * The pci_dev structure should be zero-initialized before passed 1426 * to the linux_pci_attach_device function. 1427 */ 1428 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1429 const struct pci_device_id *, struct pci_dev *); 1430 extern int linux_pci_detach_device(struct pci_dev *); 1431 1432 static inline int 1433 pci_dev_present(const struct pci_device_id *cur) 1434 { 1435 while (cur != NULL && (cur->vendor || cur->device)) { 1436 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1437 return (1); 1438 } 1439 cur++; 1440 } 1441 return (0); 1442 } 1443 1444 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1445 unsigned int bus, unsigned int devfn); 1446 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1447 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1448 1449 static inline int 1450 pci_domain_nr(struct pci_bus *pbus) 1451 { 1452 1453 return (pbus->domain); 1454 } 1455 1456 static inline int 1457 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1458 int pos, uint32_t *val, int len) 1459 { 1460 1461 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1462 return (0); 1463 } 1464 1465 static inline int 1466 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1467 { 1468 uint32_t tmp; 1469 int ret; 1470 1471 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1472 *val = (u16)tmp; 1473 return (ret); 1474 } 1475 1476 static inline int 1477 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1478 { 1479 uint32_t tmp; 1480 int ret; 1481 1482 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1483 *val = (u8)tmp; 1484 return (ret); 1485 } 1486 1487 static inline int 1488 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1489 uint32_t val, int size) 1490 { 1491 1492 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1493 return (0); 1494 } 1495 1496 static inline int 1497 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1498 uint8_t val) 1499 { 1500 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1501 } 1502 1503 static inline int 1504 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1505 uint16_t val) 1506 { 1507 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1508 } 1509 1510 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1511 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1512 1513 /* -------------------------------------------------------------------------- */ 1514 1515 static inline int 1516 pcim_enable_device(struct pci_dev *pdev) 1517 { 1518 struct pci_devres *dr; 1519 int error; 1520 1521 /* Here we cannot run through the pdev->managed check. */ 1522 dr = lkpi_pci_devres_get_alloc(pdev); 1523 if (dr == NULL) 1524 return (-ENOMEM); 1525 1526 /* If resources were enabled before do not do it again. */ 1527 if (dr->enable_io) 1528 return (0); 1529 1530 error = pci_enable_device(pdev); 1531 if (error == 0) 1532 dr->enable_io = true; 1533 1534 /* This device is not managed. */ 1535 pdev->managed = true; 1536 1537 return (error); 1538 } 1539 1540 static inline struct pcim_iomap_devres * 1541 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev) 1542 { 1543 struct pcim_iomap_devres *dr; 1544 1545 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release, 1546 NULL, NULL); 1547 if (dr == NULL) { 1548 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release, 1549 sizeof(*dr), GFP_KERNEL | __GFP_ZERO); 1550 if (dr != NULL) 1551 lkpi_devres_add(&pdev->dev, dr); 1552 } 1553 1554 if (dr == NULL) 1555 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__); 1556 1557 return (dr); 1558 } 1559 1560 static inline void __iomem ** 1561 pcim_iomap_table(struct pci_dev *pdev) 1562 { 1563 struct pcim_iomap_devres *dr; 1564 1565 dr = lkpi_pcim_iomap_devres_find(pdev); 1566 if (dr == NULL) 1567 return (NULL); 1568 1569 /* 1570 * If the driver has manually set a flag to be able to request the 1571 * resource to use bus_read/write_<n>, return the shadow table. 1572 */ 1573 if (pdev->want_iomap_res) 1574 return ((void **)dr->res_table); 1575 1576 /* This is the Linux default. */ 1577 return (dr->mmio_table); 1578 } 1579 1580 static inline int 1581 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1582 { 1583 struct pcim_iomap_devres *dr; 1584 void *res; 1585 uint32_t mappings, requests, req_mask; 1586 int bar, error; 1587 1588 dr = lkpi_pcim_iomap_devres_find(pdev); 1589 if (dr == NULL) 1590 return (-ENOMEM); 1591 1592 /* Request all the BARs ("regions") we do not iomap. */ 1593 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1594 for (bar = requests = 0; requests != req_mask; bar++) { 1595 if ((req_mask & (1 << bar)) == 0) 1596 continue; 1597 error = pci_request_region(pdev, bar, name); 1598 if (error != 0 && error != -ENODEV) 1599 goto err; 1600 requests |= (1 << bar); 1601 } 1602 1603 /* Now iomap all the requested (by "mask") ones. */ 1604 for (bar = mappings = 0; mappings != mask; bar++) { 1605 if ((mask & (1 << bar)) == 0) 1606 continue; 1607 1608 /* Request double is not allowed. */ 1609 if (dr->mmio_table[bar] != NULL) { 1610 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1611 __func__, bar, dr->mmio_table[bar]); 1612 goto err; 1613 } 1614 1615 res = _lkpi_pci_iomap(pdev, bar, 0); 1616 if (res == NULL) 1617 goto err; 1618 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1619 dr->res_table[bar] = res; 1620 1621 mappings |= (1 << bar); 1622 } 1623 1624 return (0); 1625 1626 err: 1627 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1628 if ((mappings & (1 << bar)) != 0) { 1629 res = dr->mmio_table[bar]; 1630 if (res == NULL) 1631 continue; 1632 pci_iounmap(pdev, res); 1633 } else if ((requests & (1 << bar)) != 0) { 1634 pci_release_region(pdev, bar); 1635 } 1636 } 1637 1638 return (-EINVAL); 1639 } 1640 1641 /* This is a FreeBSD extension so we can use bus_*(). */ 1642 static inline void 1643 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1644 { 1645 pdev->want_iomap_res = true; 1646 } 1647 1648 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1649