1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/nv.h> 41 #include <sys/pciio.h> 42 #include <sys/rman.h> 43 #include <sys/bus.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pci_private.h> 47 48 #include <machine/resource.h> 49 50 #include <linux/list.h> 51 #include <linux/dmapool.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/compiler.h> 54 #include <linux/errno.h> 55 #include <asm/atomic.h> 56 #include <linux/device.h> 57 #include <linux/pci_ids.h> 58 59 struct pci_device_id { 60 uint32_t vendor; 61 uint32_t device; 62 uint32_t subvendor; 63 uint32_t subdevice; 64 uint32_t class; 65 uint32_t class_mask; 66 uintptr_t driver_data; 67 }; 68 69 #define MODULE_DEVICE_TABLE(bus, table) 70 71 #define PCI_ANY_ID -1U 72 73 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 74 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 75 #define PCI_FUNC(devfn) ((devfn) & 0x07) 76 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 77 78 #define PCI_VDEVICE(_vendor, _device) \ 79 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 80 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 81 #define PCI_DEVICE(_vendor, _device) \ 82 .vendor = (_vendor), .device = (_device), \ 83 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 84 85 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 86 87 #define PCI_VENDOR_ID PCIR_DEVVENDOR 88 #define PCI_COMMAND PCIR_COMMAND 89 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 90 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 91 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 92 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 93 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 94 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 95 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 96 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 97 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 98 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 99 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 100 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 101 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 102 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 103 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 104 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 105 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 106 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 107 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 108 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 109 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 110 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 111 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 112 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 113 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 114 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 115 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 116 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 117 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 118 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 119 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 120 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 121 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 122 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 123 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 124 125 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 126 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 127 #define PCI_EXP_DEVSTA_TRPND 0x0020 128 129 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 130 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 131 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 132 133 enum pci_bus_speed { 134 PCI_SPEED_UNKNOWN = -1, 135 PCIE_SPEED_2_5GT, 136 PCIE_SPEED_5_0GT, 137 PCIE_SPEED_8_0GT, 138 PCIE_SPEED_16_0GT, 139 }; 140 141 enum pcie_link_width { 142 PCIE_LNK_WIDTH_RESRV = 0x00, 143 PCIE_LNK_X1 = 0x01, 144 PCIE_LNK_X2 = 0x02, 145 PCIE_LNK_X4 = 0x04, 146 PCIE_LNK_X8 = 0x08, 147 PCIE_LNK_X12 = 0x0c, 148 PCIE_LNK_X16 = 0x10, 149 PCIE_LNK_X32 = 0x20, 150 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 151 }; 152 153 typedef int pci_power_t; 154 155 #define PCI_D0 PCI_POWERSTATE_D0 156 #define PCI_D1 PCI_POWERSTATE_D1 157 #define PCI_D2 PCI_POWERSTATE_D2 158 #define PCI_D3hot PCI_POWERSTATE_D3 159 #define PCI_D3cold 4 160 161 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 162 163 struct pci_dev; 164 165 struct pci_driver { 166 struct list_head links; 167 char *name; 168 const struct pci_device_id *id_table; 169 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 170 void (*remove)(struct pci_dev *dev); 171 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 172 int (*resume) (struct pci_dev *dev); /* Device woken up */ 173 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 174 driver_t bsddriver; 175 devclass_t bsdclass; 176 struct device_driver driver; 177 const struct pci_error_handlers *err_handler; 178 bool isdrm; 179 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 180 const nvlist_t *pf_config); 181 void (*bsd_iov_uninit)(device_t dev); 182 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 183 const nvlist_t *vf_config); 184 }; 185 186 struct pci_bus { 187 struct pci_dev *self; 188 int domain; 189 int number; 190 }; 191 192 extern struct list_head pci_drivers; 193 extern struct list_head pci_devices; 194 extern spinlock_t pci_lock; 195 196 #define __devexit_p(x) x 197 198 struct pci_mmio_region { 199 TAILQ_ENTRY(pci_mmio_region) next; 200 struct resource *res; 201 int rid; 202 int type; 203 }; 204 205 struct pci_dev { 206 struct device dev; 207 struct list_head links; 208 struct pci_driver *pdrv; 209 struct pci_bus *bus; 210 uint16_t device; 211 uint16_t vendor; 212 uint16_t subsystem_vendor; 213 uint16_t subsystem_device; 214 unsigned int irq; 215 unsigned int devfn; 216 uint32_t class; 217 uint8_t revision; 218 bool msi_enabled; 219 220 TAILQ_HEAD(, pci_mmio_region) mmio; 221 }; 222 223 static inline struct resource_list_entry * 224 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 225 { 226 struct pci_devinfo *dinfo; 227 struct resource_list *rl; 228 229 dinfo = device_get_ivars(pdev->dev.bsddev); 230 rl = &dinfo->resources; 231 return resource_list_find(rl, type, rid); 232 } 233 234 static inline struct resource_list_entry * 235 linux_pci_get_bar(struct pci_dev *pdev, int bar) 236 { 237 struct resource_list_entry *rle; 238 239 bar = PCIR_BAR(bar); 240 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 241 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 242 return (rle); 243 } 244 245 static inline struct device * 246 linux_pci_find_irq_dev(unsigned int irq) 247 { 248 struct pci_dev *pdev; 249 struct device *found; 250 251 found = NULL; 252 spin_lock(&pci_lock); 253 list_for_each_entry(pdev, &pci_devices, links) { 254 if (irq == pdev->dev.irq || 255 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 256 found = &pdev->dev; 257 break; 258 } 259 } 260 spin_unlock(&pci_lock); 261 return (found); 262 } 263 264 static inline int 265 pci_resource_type(struct pci_dev *pdev, int bar) 266 { 267 struct pci_map *pm; 268 269 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 270 if (!pm) 271 return (-1); 272 273 if (PCI_BAR_IO(pm->pm_value)) 274 return (SYS_RES_IOPORT); 275 else 276 return (SYS_RES_MEMORY); 277 } 278 279 /* 280 * All drivers just seem to want to inspect the type not flags. 281 */ 282 static inline int 283 pci_resource_flags(struct pci_dev *pdev, int bar) 284 { 285 int type; 286 287 type = pci_resource_type(pdev, bar); 288 if (type < 0) 289 return (0); 290 return (1 << type); 291 } 292 293 static inline const char * 294 pci_name(struct pci_dev *d) 295 { 296 297 return device_get_desc(d->dev.bsddev); 298 } 299 300 static inline void * 301 pci_get_drvdata(struct pci_dev *pdev) 302 { 303 304 return dev_get_drvdata(&pdev->dev); 305 } 306 307 static inline void 308 pci_set_drvdata(struct pci_dev *pdev, void *data) 309 { 310 311 dev_set_drvdata(&pdev->dev, data); 312 } 313 314 static __inline void 315 pci_dev_put(struct pci_dev *pdev) 316 { 317 318 if (pdev != NULL) 319 put_device(&pdev->dev); 320 } 321 322 static inline int 323 pci_enable_device(struct pci_dev *pdev) 324 { 325 326 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 327 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 328 return (0); 329 } 330 331 static inline void 332 pci_disable_device(struct pci_dev *pdev) 333 { 334 335 pci_disable_busmaster(pdev->dev.bsddev); 336 } 337 338 static inline int 339 pci_set_master(struct pci_dev *pdev) 340 { 341 342 pci_enable_busmaster(pdev->dev.bsddev); 343 return (0); 344 } 345 346 static inline int 347 pci_set_power_state(struct pci_dev *pdev, int state) 348 { 349 350 pci_set_powerstate(pdev->dev.bsddev, state); 351 return (0); 352 } 353 354 static inline int 355 pci_clear_master(struct pci_dev *pdev) 356 { 357 358 pci_disable_busmaster(pdev->dev.bsddev); 359 return (0); 360 } 361 362 static inline int 363 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 364 { 365 int rid; 366 int type; 367 368 type = pci_resource_type(pdev, bar); 369 if (type < 0) 370 return (-ENODEV); 371 rid = PCIR_BAR(bar); 372 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 373 RF_ACTIVE) == NULL) 374 return (-EINVAL); 375 return (0); 376 } 377 378 static inline void 379 pci_release_region(struct pci_dev *pdev, int bar) 380 { 381 struct resource_list_entry *rle; 382 383 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 384 return; 385 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 386 } 387 388 static inline void 389 pci_release_regions(struct pci_dev *pdev) 390 { 391 int i; 392 393 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 394 pci_release_region(pdev, i); 395 } 396 397 static inline int 398 pci_request_regions(struct pci_dev *pdev, const char *res_name) 399 { 400 int error; 401 int i; 402 403 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 404 error = pci_request_region(pdev, i, res_name); 405 if (error && error != -ENODEV) { 406 pci_release_regions(pdev); 407 return (error); 408 } 409 } 410 return (0); 411 } 412 413 static inline void 414 pci_disable_msix(struct pci_dev *pdev) 415 { 416 417 pci_release_msi(pdev->dev.bsddev); 418 419 /* 420 * The MSIX IRQ numbers associated with this PCI device are no 421 * longer valid and might be re-assigned. Make sure 422 * linux_pci_find_irq_dev() does no longer see them by 423 * resetting their references to zero: 424 */ 425 pdev->dev.irq_start = 0; 426 pdev->dev.irq_end = 0; 427 } 428 429 #define pci_disable_msi(pdev) \ 430 linux_pci_disable_msi(pdev) 431 432 static inline void 433 linux_pci_disable_msi(struct pci_dev *pdev) 434 { 435 436 pci_release_msi(pdev->dev.bsddev); 437 438 pdev->dev.irq_start = 0; 439 pdev->dev.irq_end = 0; 440 pdev->irq = pdev->dev.irq; 441 pdev->msi_enabled = false; 442 } 443 444 #define pci_free_irq_vectors(pdev) \ 445 linux_pci_disable_msi(pdev) 446 447 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 448 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 449 450 static inline bus_addr_t 451 pci_bus_address(struct pci_dev *pdev, int bar) 452 { 453 454 return (pci_resource_start(pdev, bar)); 455 } 456 457 #define PCI_CAP_ID_EXP PCIY_EXPRESS 458 #define PCI_CAP_ID_PCIX PCIY_PCIX 459 #define PCI_CAP_ID_AGP PCIY_AGP 460 #define PCI_CAP_ID_PM PCIY_PMG 461 462 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 463 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 464 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 465 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 466 #define PCI_EXP_LNKSTA PCIER_LINK_STA 467 468 static inline int 469 pci_find_capability(struct pci_dev *pdev, int capid) 470 { 471 int reg; 472 473 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 474 return (0); 475 return (reg); 476 } 477 478 static inline int pci_pcie_cap(struct pci_dev *dev) 479 { 480 return pci_find_capability(dev, PCI_CAP_ID_EXP); 481 } 482 483 static inline int 484 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 485 { 486 487 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 488 return (0); 489 } 490 491 static inline int 492 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 493 { 494 495 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 496 return (0); 497 } 498 499 static inline int 500 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 501 { 502 503 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 504 return (0); 505 } 506 507 static inline int 508 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 509 { 510 511 pci_write_config(pdev->dev.bsddev, where, val, 1); 512 return (0); 513 } 514 515 static inline int 516 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 517 { 518 519 pci_write_config(pdev->dev.bsddev, where, val, 2); 520 return (0); 521 } 522 523 static inline int 524 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 525 { 526 527 pci_write_config(pdev->dev.bsddev, where, val, 4); 528 return (0); 529 } 530 531 int linux_pci_register_driver(struct pci_driver *pdrv); 532 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 533 void linux_pci_unregister_driver(struct pci_driver *pdrv); 534 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 535 536 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 537 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 538 539 struct msix_entry { 540 int entry; 541 int vector; 542 }; 543 544 /* 545 * Enable msix, positive errors indicate actual number of available 546 * vectors. Negative errors are failures. 547 * 548 * NB: define added to prevent this definition of pci_enable_msix from 549 * clashing with the native FreeBSD version. 550 */ 551 #define pci_enable_msix(...) \ 552 linux_pci_enable_msix(__VA_ARGS__) 553 554 static inline int 555 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 556 { 557 struct resource_list_entry *rle; 558 int error; 559 int avail; 560 int i; 561 562 avail = pci_msix_count(pdev->dev.bsddev); 563 if (avail < nreq) { 564 if (avail == 0) 565 return -EINVAL; 566 return avail; 567 } 568 avail = nreq; 569 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 570 return error; 571 /* 572 * Handle case where "pci_alloc_msix()" may allocate less 573 * interrupts than available and return with no error: 574 */ 575 if (avail < nreq) { 576 pci_release_msi(pdev->dev.bsddev); 577 return avail; 578 } 579 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 580 pdev->dev.irq_start = rle->start; 581 pdev->dev.irq_end = rle->start + avail; 582 for (i = 0; i < nreq; i++) 583 entries[i].vector = pdev->dev.irq_start + i; 584 return (0); 585 } 586 587 #define pci_enable_msix_range(...) \ 588 linux_pci_enable_msix_range(__VA_ARGS__) 589 590 static inline int 591 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 592 int minvec, int maxvec) 593 { 594 int nvec = maxvec; 595 int rc; 596 597 if (maxvec < minvec) 598 return (-ERANGE); 599 600 do { 601 rc = pci_enable_msix(dev, entries, nvec); 602 if (rc < 0) { 603 return (rc); 604 } else if (rc > 0) { 605 if (rc < minvec) 606 return (-ENOSPC); 607 nvec = rc; 608 } 609 } while (rc); 610 return (nvec); 611 } 612 613 #define pci_enable_msi(pdev) \ 614 linux_pci_enable_msi(pdev) 615 616 static inline int 617 pci_enable_msi(struct pci_dev *pdev) 618 { 619 struct resource_list_entry *rle; 620 int error; 621 int avail; 622 623 avail = pci_msi_count(pdev->dev.bsddev); 624 if (avail < 1) 625 return -EINVAL; 626 627 avail = 1; /* this function only enable one MSI IRQ */ 628 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 629 return error; 630 631 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 632 pdev->dev.irq_start = rle->start; 633 pdev->dev.irq_end = rle->start + avail; 634 pdev->irq = rle->start; 635 pdev->msi_enabled = true; 636 return (0); 637 } 638 639 static inline int 640 pci_channel_offline(struct pci_dev *pdev) 641 { 642 643 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 644 } 645 646 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 647 { 648 return -ENODEV; 649 } 650 static inline void pci_disable_sriov(struct pci_dev *dev) 651 { 652 } 653 654 static inline void * 655 pci_iomap(struct pci_dev *dev, int mmio_bar, int mmio_size __unused) 656 { 657 struct pci_mmio_region *mmio; 658 659 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 660 mmio->rid = PCIR_BAR(mmio_bar); 661 mmio->type = pci_resource_type(dev, mmio_bar); 662 mmio->res = bus_alloc_resource_any(dev->dev.bsddev, mmio->type, 663 &mmio->rid, RF_ACTIVE); 664 if (mmio->res == NULL) { 665 free(mmio, M_DEVBUF); 666 return (NULL); 667 } 668 TAILQ_INSERT_TAIL(&dev->mmio, mmio, next); 669 670 return ((void *)rman_get_bushandle(mmio->res)); 671 } 672 673 static inline void 674 pci_iounmap(struct pci_dev *dev, void *res) 675 { 676 struct pci_mmio_region *mmio, *p; 677 678 TAILQ_FOREACH_SAFE(mmio, &dev->mmio, next, p) { 679 if (res != (void *)rman_get_bushandle(mmio->res)) 680 continue; 681 bus_release_resource(dev->dev.bsddev, 682 mmio->type, mmio->rid, mmio->res); 683 TAILQ_REMOVE(&dev->mmio, mmio, next); 684 free(mmio, M_DEVBUF); 685 return; 686 } 687 } 688 689 static inline void 690 lkpi_pci_save_state(struct pci_dev *pdev) 691 { 692 693 pci_save_state(pdev->dev.bsddev); 694 } 695 696 static inline void 697 lkpi_pci_restore_state(struct pci_dev *pdev) 698 { 699 700 pci_restore_state(pdev->dev.bsddev); 701 } 702 703 #define pci_save_state(dev) lkpi_pci_save_state(dev) 704 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 705 706 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 707 const struct pci_device_id _table[] __devinitdata 708 709 /* XXX This should not be necessary. */ 710 #define pcix_set_mmrbc(d, v) 0 711 #define pcix_get_max_mmrbc(d) 0 712 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 713 714 #define PCI_DMA_BIDIRECTIONAL 0 715 #define PCI_DMA_TODEVICE 1 716 #define PCI_DMA_FROMDEVICE 2 717 #define PCI_DMA_NONE 3 718 719 #define pci_pool dma_pool 720 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 721 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 722 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 723 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 724 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 725 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 726 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 727 _size, _vaddr, _dma_handle) 728 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 729 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 730 _sg, _nents, (enum dma_data_direction)_dir) 731 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 732 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 733 (_ptr), (_size), (enum dma_data_direction)_dir) 734 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 735 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 736 _addr, _size, (enum dma_data_direction)_dir) 737 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 738 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 739 _sg, _nents, (enum dma_data_direction)_dir) 740 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 741 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 742 _offset, _size, (enum dma_data_direction)_dir) 743 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 744 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 745 _dma_address, _size, (enum dma_data_direction)_dir) 746 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 747 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 748 dma_mapping_error(&(_pdev)->dev, _dma_addr) 749 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 750 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 751 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 752 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 753 #define pci_unmap_addr dma_unmap_addr 754 #define pci_unmap_addr_set dma_unmap_addr_set 755 #define pci_unmap_len dma_unmap_len 756 #define pci_unmap_len_set dma_unmap_len_set 757 758 typedef unsigned int __bitwise pci_channel_state_t; 759 typedef unsigned int __bitwise pci_ers_result_t; 760 761 enum pci_channel_state { 762 pci_channel_io_normal = 1, 763 pci_channel_io_frozen = 2, 764 pci_channel_io_perm_failure = 3, 765 }; 766 767 enum pci_ers_result { 768 PCI_ERS_RESULT_NONE = 1, 769 PCI_ERS_RESULT_CAN_RECOVER = 2, 770 PCI_ERS_RESULT_NEED_RESET = 3, 771 PCI_ERS_RESULT_DISCONNECT = 4, 772 PCI_ERS_RESULT_RECOVERED = 5, 773 }; 774 775 /* PCI bus error event callbacks */ 776 struct pci_error_handlers { 777 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 778 enum pci_channel_state error); 779 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 780 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 781 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 782 void (*resume)(struct pci_dev *dev); 783 }; 784 785 /* FreeBSD does not support SRIOV - yet */ 786 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 787 { 788 return dev; 789 } 790 791 static inline bool pci_is_pcie(struct pci_dev *dev) 792 { 793 return !!pci_pcie_cap(dev); 794 } 795 796 static inline u16 pcie_flags_reg(struct pci_dev *dev) 797 { 798 int pos; 799 u16 reg16; 800 801 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 802 if (!pos) 803 return 0; 804 805 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 806 807 return reg16; 808 } 809 810 static inline int pci_pcie_type(struct pci_dev *dev) 811 { 812 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 813 } 814 815 static inline int pcie_cap_version(struct pci_dev *dev) 816 { 817 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 818 } 819 820 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 821 { 822 int type = pci_pcie_type(dev); 823 824 return pcie_cap_version(dev) > 1 || 825 type == PCI_EXP_TYPE_ROOT_PORT || 826 type == PCI_EXP_TYPE_ENDPOINT || 827 type == PCI_EXP_TYPE_LEG_END; 828 } 829 830 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 831 { 832 return true; 833 } 834 835 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 836 { 837 int type = pci_pcie_type(dev); 838 839 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 840 (type == PCI_EXP_TYPE_DOWNSTREAM && 841 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 842 } 843 844 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 845 { 846 int type = pci_pcie_type(dev); 847 848 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 849 type == PCI_EXP_TYPE_RC_EC; 850 } 851 852 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 853 { 854 if (!pci_is_pcie(dev)) 855 return false; 856 857 switch (pos) { 858 case PCI_EXP_FLAGS_TYPE: 859 return true; 860 case PCI_EXP_DEVCAP: 861 case PCI_EXP_DEVCTL: 862 case PCI_EXP_DEVSTA: 863 return pcie_cap_has_devctl(dev); 864 case PCI_EXP_LNKCAP: 865 case PCI_EXP_LNKCTL: 866 case PCI_EXP_LNKSTA: 867 return pcie_cap_has_lnkctl(dev); 868 case PCI_EXP_SLTCAP: 869 case PCI_EXP_SLTCTL: 870 case PCI_EXP_SLTSTA: 871 return pcie_cap_has_sltctl(dev); 872 case PCI_EXP_RTCTL: 873 case PCI_EXP_RTCAP: 874 case PCI_EXP_RTSTA: 875 return pcie_cap_has_rtctl(dev); 876 case PCI_EXP_DEVCAP2: 877 case PCI_EXP_DEVCTL2: 878 case PCI_EXP_LNKCAP2: 879 case PCI_EXP_LNKCTL2: 880 case PCI_EXP_LNKSTA2: 881 return pcie_cap_version(dev) > 1; 882 default: 883 return false; 884 } 885 } 886 887 static inline int 888 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 889 { 890 if (pos & 3) 891 return -EINVAL; 892 893 if (!pcie_capability_reg_implemented(dev, pos)) 894 return -EINVAL; 895 896 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 897 } 898 899 static inline int 900 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 901 { 902 if (pos & 3) 903 return -EINVAL; 904 905 if (!pcie_capability_reg_implemented(dev, pos)) 906 return -EINVAL; 907 908 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 909 } 910 911 static inline int 912 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 913 { 914 if (pos & 1) 915 return -EINVAL; 916 917 if (!pcie_capability_reg_implemented(dev, pos)) 918 return 0; 919 920 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 921 } 922 923 static inline int pcie_get_minimum_link(struct pci_dev *dev, 924 enum pci_bus_speed *speed, enum pcie_link_width *width) 925 { 926 *speed = PCI_SPEED_UNKNOWN; 927 *width = PCIE_LNK_WIDTH_UNKNOWN; 928 return (0); 929 } 930 931 static inline int 932 pci_num_vf(struct pci_dev *dev) 933 { 934 return (0); 935 } 936 937 static inline enum pci_bus_speed 938 pcie_get_speed_cap(struct pci_dev *dev) 939 { 940 device_t root; 941 uint32_t lnkcap, lnkcap2; 942 int error, pos; 943 944 root = device_get_parent(dev->dev.bsddev); 945 if (root == NULL) 946 return (PCI_SPEED_UNKNOWN); 947 root = device_get_parent(root); 948 if (root == NULL) 949 return (PCI_SPEED_UNKNOWN); 950 root = device_get_parent(root); 951 if (root == NULL) 952 return (PCI_SPEED_UNKNOWN); 953 954 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 955 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 956 return (PCI_SPEED_UNKNOWN); 957 958 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 959 return (PCI_SPEED_UNKNOWN); 960 961 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 962 963 if (lnkcap2) { /* PCIe r3.0-compliant */ 964 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 965 return (PCIE_SPEED_2_5GT); 966 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 967 return (PCIE_SPEED_5_0GT); 968 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 969 return (PCIE_SPEED_8_0GT); 970 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 971 return (PCIE_SPEED_16_0GT); 972 } else { /* pre-r3.0 */ 973 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 974 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 975 return (PCIE_SPEED_2_5GT); 976 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 977 return (PCIE_SPEED_5_0GT); 978 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 979 return (PCIE_SPEED_8_0GT); 980 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 981 return (PCIE_SPEED_16_0GT); 982 } 983 return (PCI_SPEED_UNKNOWN); 984 } 985 986 static inline enum pcie_link_width 987 pcie_get_width_cap(struct pci_dev *dev) 988 { 989 uint32_t lnkcap; 990 991 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 992 if (lnkcap) 993 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 994 995 return (PCIE_LNK_WIDTH_UNKNOWN); 996 } 997 998 static inline int 999 pcie_get_mps(struct pci_dev *dev) 1000 { 1001 return (pci_get_max_payload(dev->dev.bsddev)); 1002 } 1003 1004 static inline uint32_t 1005 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1006 { 1007 1008 switch(spd) { 1009 case PCIE_SPEED_16_0GT: 1010 return (16000 * 128 / 130); 1011 case PCIE_SPEED_8_0GT: 1012 return (8000 * 128 / 130); 1013 case PCIE_SPEED_5_0GT: 1014 return (5000 * 8 / 10); 1015 case PCIE_SPEED_2_5GT: 1016 return (2500 * 8 / 10); 1017 default: 1018 return (0); 1019 } 1020 } 1021 1022 static inline uint32_t 1023 pcie_bandwidth_available(struct pci_dev *pdev, 1024 struct pci_dev **limiting, 1025 enum pci_bus_speed *speed, 1026 enum pcie_link_width *width) 1027 { 1028 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1029 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1030 1031 if (speed) 1032 *speed = nspeed; 1033 if (width) 1034 *width = nwidth; 1035 1036 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1037 } 1038 1039 /* 1040 * The following functions can be used to attach/detach the LinuxKPI's 1041 * PCI device runtime. The pci_driver and pci_device_id pointer is 1042 * allowed to be NULL. Other pointers must be all valid. 1043 * The pci_dev structure should be zero-initialized before passed 1044 * to the linux_pci_attach_device function. 1045 */ 1046 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1047 const struct pci_device_id *, struct pci_dev *); 1048 extern int linux_pci_detach_device(struct pci_dev *); 1049 1050 static inline int 1051 pci_dev_present(const struct pci_device_id *cur) 1052 { 1053 while (cur != NULL && (cur->vendor || cur->device)) { 1054 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1055 return (1); 1056 } 1057 cur++; 1058 } 1059 return (0); 1060 } 1061 1062 static inline bool 1063 pci_is_root_bus(struct pci_bus *pbus) 1064 { 1065 1066 return (pbus->self == NULL); 1067 } 1068 1069 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1070 unsigned int bus, unsigned int devfn); 1071 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1072 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1073 1074 static inline int 1075 pci_domain_nr(struct pci_bus *pbus) 1076 { 1077 1078 return (pbus->domain); 1079 } 1080 1081 static inline int 1082 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1083 int pos, uint32_t *val, int len) 1084 { 1085 1086 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1087 return (0); 1088 } 1089 1090 static inline int 1091 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1092 { 1093 uint32_t tmp; 1094 int ret; 1095 1096 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1097 *val = (u16)tmp; 1098 return (ret); 1099 } 1100 1101 static inline int 1102 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1103 { 1104 uint32_t tmp; 1105 int ret; 1106 1107 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1108 *val = (u8)tmp; 1109 return (ret); 1110 } 1111 1112 static inline int 1113 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1114 uint32_t val, int size) 1115 { 1116 1117 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1118 return (0); 1119 } 1120 1121 static inline int 1122 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1123 uint8_t val) 1124 { 1125 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1126 } 1127 1128 static inline int 1129 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1130 uint16_t val) 1131 { 1132 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1133 } 1134 1135 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1136 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1137 1138 #endif /* _LINUX_PCI_H_ */ 1139