1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUX_PCI_H_ 36 #define _LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <sys/rman.h> 47 #include <sys/bus.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 #define MODULE_DEVICE_TABLE(bus, table) 74 75 #define PCI_ANY_ID -1U 76 77 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 78 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 79 #define PCI_FUNC(devfn) ((devfn) & 0x07) 80 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 81 82 #define PCI_VDEVICE(_vendor, _device) \ 83 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 84 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 85 #define PCI_DEVICE(_vendor, _device) \ 86 .vendor = (_vendor), .device = (_device), \ 87 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 88 89 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 90 91 #define PCI_VENDOR_ID PCIR_DEVVENDOR 92 #define PCI_COMMAND PCIR_COMMAND 93 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 94 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 95 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 96 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 97 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 98 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 99 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 100 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 101 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 102 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 103 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 104 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 105 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 106 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 107 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 108 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 109 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 110 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 111 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 112 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 113 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 114 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 115 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 116 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 117 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 118 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 119 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 120 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 121 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 122 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 123 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 124 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 125 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 126 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 127 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 128 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 129 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 130 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 131 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 132 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 133 #define PCI_EXP_LNKCTL2_TLS 0x000f 134 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 135 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 136 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 137 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 138 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 139 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 140 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 141 142 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 143 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 144 #define PCI_EXP_DEVSTA_TRPND 0x0020 145 146 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 147 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 148 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 149 150 enum pci_bus_speed { 151 PCI_SPEED_UNKNOWN = -1, 152 PCIE_SPEED_2_5GT, 153 PCIE_SPEED_5_0GT, 154 PCIE_SPEED_8_0GT, 155 PCIE_SPEED_16_0GT, 156 }; 157 158 enum pcie_link_width { 159 PCIE_LNK_WIDTH_RESRV = 0x00, 160 PCIE_LNK_X1 = 0x01, 161 PCIE_LNK_X2 = 0x02, 162 PCIE_LNK_X4 = 0x04, 163 PCIE_LNK_X8 = 0x08, 164 PCIE_LNK_X12 = 0x0c, 165 PCIE_LNK_X16 = 0x10, 166 PCIE_LNK_X32 = 0x20, 167 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 168 }; 169 170 #define PCIE_LINK_STATE_L0S 0x00000001 171 #define PCIE_LINK_STATE_L1 0x00000002 172 #define PCIE_LINK_STATE_CLKPM 0x00000004 173 174 typedef int pci_power_t; 175 176 #define PCI_D0 PCI_POWERSTATE_D0 177 #define PCI_D1 PCI_POWERSTATE_D1 178 #define PCI_D2 PCI_POWERSTATE_D2 179 #define PCI_D3hot PCI_POWERSTATE_D3 180 #define PCI_D3cold 4 181 182 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 183 184 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 185 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 186 187 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 188 189 #define PCI_IRQ_LEGACY 0x01 190 #define PCI_IRQ_MSI 0x02 191 #define PCI_IRQ_MSIX 0x04 192 193 struct pci_dev; 194 195 struct pci_driver { 196 struct list_head node; 197 char *name; 198 const struct pci_device_id *id_table; 199 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 200 void (*remove)(struct pci_dev *dev); 201 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 202 int (*resume) (struct pci_dev *dev); /* Device woken up */ 203 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 204 driver_t bsddriver; 205 devclass_t bsdclass; 206 struct device_driver driver; 207 const struct pci_error_handlers *err_handler; 208 bool isdrm; 209 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 210 const nvlist_t *pf_config); 211 void (*bsd_iov_uninit)(device_t dev); 212 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 213 const nvlist_t *vf_config); 214 }; 215 216 struct pci_bus { 217 struct pci_dev *self; 218 int domain; 219 int number; 220 }; 221 222 extern struct list_head pci_drivers; 223 extern struct list_head pci_devices; 224 extern spinlock_t pci_lock; 225 226 #define __devexit_p(x) x 227 228 #define module_pci_driver(_driver) \ 229 \ 230 static inline int \ 231 _pci_init(void) \ 232 { \ 233 \ 234 return (linux_pci_register_driver(&_driver)); \ 235 } \ 236 \ 237 static inline void \ 238 _pci_exit(void) \ 239 { \ 240 \ 241 linux_pci_unregister_driver(&_driver); \ 242 } \ 243 \ 244 module_init(_pci_init); \ 245 module_exit(_pci_exit) 246 247 /* 248 * If we find drivers accessing this from multiple KPIs we may have to 249 * refcount objects of this structure. 250 */ 251 struct pci_mmio_region { 252 TAILQ_ENTRY(pci_mmio_region) next; 253 struct resource *res; 254 int rid; 255 int type; 256 }; 257 258 struct pci_dev { 259 struct device dev; 260 struct list_head links; 261 struct pci_driver *pdrv; 262 struct pci_bus *bus; 263 struct pci_dev *root; 264 uint16_t device; 265 uint16_t vendor; 266 uint16_t subsystem_vendor; 267 uint16_t subsystem_device; 268 unsigned int irq; 269 unsigned int devfn; 270 uint32_t class; 271 uint8_t revision; 272 bool managed; /* devres "pcim_*(). */ 273 bool want_iomap_res; 274 bool msi_enabled; 275 bool msix_enabled; 276 phys_addr_t rom; 277 size_t romlen; 278 279 TAILQ_HEAD(, pci_mmio_region) mmio; 280 }; 281 282 /* We need some meta-struct to keep track of these for devres. */ 283 struct pci_devres { 284 bool enable_io; 285 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 286 uint8_t region_mask; 287 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 288 }; 289 struct pcim_iomap_devres { 290 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 291 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 292 }; 293 294 /* Internal helper function(s). */ 295 struct pci_dev *lkpinew_pci_dev(device_t); 296 void lkpi_pci_devres_release(struct device *, void *); 297 void lkpi_pcim_iomap_table_release(struct device *, void *); 298 299 static inline int 300 pci_resource_type(struct pci_dev *pdev, int bar) 301 { 302 struct pci_map *pm; 303 304 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 305 if (!pm) 306 return (-1); 307 308 if (PCI_BAR_IO(pm->pm_value)) 309 return (SYS_RES_IOPORT); 310 else 311 return (SYS_RES_MEMORY); 312 } 313 314 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 315 struct resource_list *rl, int type, int rid); 316 317 static inline struct resource_list_entry * 318 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 319 { 320 struct pci_devinfo *dinfo; 321 struct resource_list *rl; 322 struct resource_list_entry *rle; 323 324 dinfo = device_get_ivars(pdev->dev.bsddev); 325 rl = &dinfo->resources; 326 rle = resource_list_find(rl, type, rid); 327 /* Reserve resources for this BAR if needed. */ 328 if (rle == NULL && reserve_bar) 329 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 330 return (rle); 331 } 332 333 static inline struct resource_list_entry * 334 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 335 { 336 int type; 337 338 type = pci_resource_type(pdev, bar); 339 if (type < 0) 340 return (NULL); 341 bar = PCIR_BAR(bar); 342 return (linux_pci_get_rle(pdev, type, bar, reserve)); 343 } 344 345 static inline struct device * 346 linux_pci_find_irq_dev(unsigned int irq) 347 { 348 struct pci_dev *pdev; 349 struct device *found; 350 351 found = NULL; 352 spin_lock(&pci_lock); 353 list_for_each_entry(pdev, &pci_devices, links) { 354 if (irq == pdev->dev.irq || 355 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 356 found = &pdev->dev; 357 break; 358 } 359 } 360 spin_unlock(&pci_lock); 361 return (found); 362 } 363 364 /* 365 * All drivers just seem to want to inspect the type not flags. 366 */ 367 static inline int 368 pci_resource_flags(struct pci_dev *pdev, int bar) 369 { 370 int type; 371 372 type = pci_resource_type(pdev, bar); 373 if (type < 0) 374 return (0); 375 return (1 << type); 376 } 377 378 static inline const char * 379 pci_name(struct pci_dev *d) 380 { 381 382 return device_get_desc(d->dev.bsddev); 383 } 384 385 static inline void * 386 pci_get_drvdata(struct pci_dev *pdev) 387 { 388 389 return dev_get_drvdata(&pdev->dev); 390 } 391 392 static inline void 393 pci_set_drvdata(struct pci_dev *pdev, void *data) 394 { 395 396 dev_set_drvdata(&pdev->dev, data); 397 } 398 399 static inline struct pci_dev * 400 pci_dev_get(struct pci_dev *pdev) 401 { 402 403 if (pdev != NULL) 404 get_device(&pdev->dev); 405 return (pdev); 406 } 407 408 static __inline void 409 pci_dev_put(struct pci_dev *pdev) 410 { 411 412 if (pdev != NULL) 413 put_device(&pdev->dev); 414 } 415 416 static inline int 417 pci_enable_device(struct pci_dev *pdev) 418 { 419 420 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 421 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 422 return (0); 423 } 424 425 static inline void 426 pci_disable_device(struct pci_dev *pdev) 427 { 428 429 pci_disable_busmaster(pdev->dev.bsddev); 430 } 431 432 static inline int 433 pci_set_master(struct pci_dev *pdev) 434 { 435 436 pci_enable_busmaster(pdev->dev.bsddev); 437 return (0); 438 } 439 440 static inline int 441 pci_set_power_state(struct pci_dev *pdev, int state) 442 { 443 444 pci_set_powerstate(pdev->dev.bsddev, state); 445 return (0); 446 } 447 448 static inline int 449 pci_clear_master(struct pci_dev *pdev) 450 { 451 452 pci_disable_busmaster(pdev->dev.bsddev); 453 return (0); 454 } 455 456 static inline struct pci_devres * 457 lkpi_pci_devres_get_alloc(struct pci_dev *pdev) 458 { 459 struct pci_devres *dr; 460 461 dr = lkpi_devres_find(&pdev->dev, lkpi_pci_devres_release, NULL, NULL); 462 if (dr == NULL) { 463 dr = lkpi_devres_alloc(lkpi_pci_devres_release, sizeof(*dr), 464 GFP_KERNEL | __GFP_ZERO); 465 if (dr != NULL) 466 lkpi_devres_add(&pdev->dev, dr); 467 } 468 469 return (dr); 470 } 471 static inline struct pci_devres * 472 lkpi_pci_devres_find(struct pci_dev *pdev) 473 { 474 475 if (!pdev->managed) 476 return (NULL); 477 478 return (lkpi_pci_devres_get_alloc(pdev)); 479 } 480 481 static inline int 482 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 483 { 484 struct resource *res; 485 struct pci_devres *dr; 486 struct pci_mmio_region *mmio; 487 int rid; 488 int type; 489 490 type = pci_resource_type(pdev, bar); 491 if (type < 0) 492 return (-ENODEV); 493 rid = PCIR_BAR(bar); 494 res = bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 495 RF_ACTIVE|RF_SHAREABLE); 496 if (res == NULL) { 497 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 498 "bar %d type %d rid %d\n", 499 __func__, bar, type, PCIR_BAR(bar)); 500 return (-ENODEV); 501 } 502 503 /* 504 * It seems there is an implicit devres tracking on these if the device 505 * is managed; otherwise the resources are not automatiaclly freed on 506 * FreeBSD/LinuxKPI tough they should be/are expected to be by Linux 507 * drivers. 508 */ 509 dr = lkpi_pci_devres_find(pdev); 510 if (dr != NULL) { 511 dr->region_mask |= (1 << bar); 512 dr->region_table[bar] = res; 513 } 514 515 /* Even if the device is not managed we need to track it for iomap. */ 516 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 517 mmio->rid = PCIR_BAR(bar); 518 mmio->type = type; 519 mmio->res = res; 520 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 521 522 return (0); 523 } 524 525 static inline void 526 pci_release_region(struct pci_dev *pdev, int bar) 527 { 528 struct resource_list_entry *rle; 529 struct pci_devres *dr; 530 struct pci_mmio_region *mmio, *p; 531 532 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 533 return; 534 535 /* 536 * As we implicitly track the requests we also need to clear them on 537 * release. Do clear before resource release. 538 */ 539 dr = lkpi_pci_devres_find(pdev); 540 if (dr != NULL) { 541 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 542 " region_table res %p != rel->res %p\n", __func__, pdev, 543 bar, dr->region_table[bar], rle->res)); 544 dr->region_table[bar] = NULL; 545 dr->region_mask &= ~(1 << bar); 546 } 547 548 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 549 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 550 continue; 551 TAILQ_REMOVE(&pdev->mmio, mmio, next); 552 free(mmio, M_DEVBUF); 553 } 554 555 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 556 } 557 558 static inline void 559 pci_release_regions(struct pci_dev *pdev) 560 { 561 int i; 562 563 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 564 pci_release_region(pdev, i); 565 } 566 567 static inline int 568 pci_request_regions(struct pci_dev *pdev, const char *res_name) 569 { 570 int error; 571 int i; 572 573 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 574 error = pci_request_region(pdev, i, res_name); 575 if (error && error != -ENODEV) { 576 pci_release_regions(pdev); 577 return (error); 578 } 579 } 580 return (0); 581 } 582 583 static inline void 584 lkpi_pci_disable_msix(struct pci_dev *pdev) 585 { 586 587 pci_release_msi(pdev->dev.bsddev); 588 589 /* 590 * The MSIX IRQ numbers associated with this PCI device are no 591 * longer valid and might be re-assigned. Make sure 592 * linux_pci_find_irq_dev() does no longer see them by 593 * resetting their references to zero: 594 */ 595 pdev->dev.irq_start = 0; 596 pdev->dev.irq_end = 0; 597 pdev->msix_enabled = false; 598 } 599 /* Only for consistency. No conflict on that one. */ 600 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 601 602 static inline void 603 lkpi_pci_disable_msi(struct pci_dev *pdev) 604 { 605 606 pci_release_msi(pdev->dev.bsddev); 607 608 pdev->dev.irq_start = 0; 609 pdev->dev.irq_end = 0; 610 pdev->irq = pdev->dev.irq; 611 pdev->msi_enabled = false; 612 } 613 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 614 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 615 616 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 617 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 618 619 static inline bus_addr_t 620 pci_bus_address(struct pci_dev *pdev, int bar) 621 { 622 623 return (pci_resource_start(pdev, bar)); 624 } 625 626 #define PCI_CAP_ID_EXP PCIY_EXPRESS 627 #define PCI_CAP_ID_PCIX PCIY_PCIX 628 #define PCI_CAP_ID_AGP PCIY_AGP 629 #define PCI_CAP_ID_PM PCIY_PMG 630 631 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 632 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 633 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 634 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 635 #define PCI_EXP_LNKSTA PCIER_LINK_STA 636 637 static inline int 638 pci_find_capability(struct pci_dev *pdev, int capid) 639 { 640 int reg; 641 642 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 643 return (0); 644 return (reg); 645 } 646 647 static inline int pci_pcie_cap(struct pci_dev *dev) 648 { 649 return pci_find_capability(dev, PCI_CAP_ID_EXP); 650 } 651 652 static inline int 653 pci_find_ext_capability(struct pci_dev *pdev, int capid) 654 { 655 int reg; 656 657 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 658 return (0); 659 return (reg); 660 } 661 662 #define PCIM_PCAP_PME_SHIFT 11 663 static __inline bool 664 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 665 { 666 struct pci_devinfo *dinfo; 667 pcicfgregs *cfg; 668 669 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 670 return (false); 671 672 dinfo = device_get_ivars(pdev->dev.bsddev); 673 cfg = &dinfo->cfg; 674 675 if (cfg->pp.pp_cap == 0) 676 return (false); 677 678 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 679 return (true); 680 681 return (false); 682 } 683 684 static inline int 685 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 686 { 687 688 if (!pci_enable_aspm) 689 return (-EPERM); 690 691 return (-ENXIO); 692 } 693 694 static inline int 695 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 696 { 697 698 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 699 return (0); 700 } 701 702 static inline int 703 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 704 { 705 706 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 707 return (0); 708 } 709 710 static inline int 711 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 712 { 713 714 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 715 return (0); 716 } 717 718 static inline int 719 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 720 { 721 722 pci_write_config(pdev->dev.bsddev, where, val, 1); 723 return (0); 724 } 725 726 static inline int 727 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 728 { 729 730 pci_write_config(pdev->dev.bsddev, where, val, 2); 731 return (0); 732 } 733 734 static inline int 735 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 736 { 737 738 pci_write_config(pdev->dev.bsddev, where, val, 4); 739 return (0); 740 } 741 742 int linux_pci_register_driver(struct pci_driver *pdrv); 743 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 744 void linux_pci_unregister_driver(struct pci_driver *pdrv); 745 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 746 747 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 748 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 749 750 struct msix_entry { 751 int entry; 752 int vector; 753 }; 754 755 /* 756 * Enable msix, positive errors indicate actual number of available 757 * vectors. Negative errors are failures. 758 * 759 * NB: define added to prevent this definition of pci_enable_msix from 760 * clashing with the native FreeBSD version. 761 */ 762 #define pci_enable_msix(...) \ 763 linux_pci_enable_msix(__VA_ARGS__) 764 765 static inline int 766 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 767 { 768 struct resource_list_entry *rle; 769 int error; 770 int avail; 771 int i; 772 773 avail = pci_msix_count(pdev->dev.bsddev); 774 if (avail < nreq) { 775 if (avail == 0) 776 return -EINVAL; 777 return avail; 778 } 779 avail = nreq; 780 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 781 return error; 782 /* 783 * Handle case where "pci_alloc_msix()" may allocate less 784 * interrupts than available and return with no error: 785 */ 786 if (avail < nreq) { 787 pci_release_msi(pdev->dev.bsddev); 788 return avail; 789 } 790 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 791 pdev->dev.irq_start = rle->start; 792 pdev->dev.irq_end = rle->start + avail; 793 for (i = 0; i < nreq; i++) 794 entries[i].vector = pdev->dev.irq_start + i; 795 pdev->msix_enabled = true; 796 return (0); 797 } 798 799 #define pci_enable_msix_range(...) \ 800 linux_pci_enable_msix_range(__VA_ARGS__) 801 802 static inline int 803 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 804 int minvec, int maxvec) 805 { 806 int nvec = maxvec; 807 int rc; 808 809 if (maxvec < minvec) 810 return (-ERANGE); 811 812 do { 813 rc = pci_enable_msix(dev, entries, nvec); 814 if (rc < 0) { 815 return (rc); 816 } else if (rc > 0) { 817 if (rc < minvec) 818 return (-ENOSPC); 819 nvec = rc; 820 } 821 } while (rc); 822 return (nvec); 823 } 824 825 #define pci_enable_msi(pdev) \ 826 linux_pci_enable_msi(pdev) 827 828 static inline int 829 pci_enable_msi(struct pci_dev *pdev) 830 { 831 struct resource_list_entry *rle; 832 int error; 833 int avail; 834 835 avail = pci_msi_count(pdev->dev.bsddev); 836 if (avail < 1) 837 return -EINVAL; 838 839 avail = 1; /* this function only enable one MSI IRQ */ 840 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 841 return error; 842 843 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 844 pdev->dev.irq_start = rle->start; 845 pdev->dev.irq_end = rle->start + avail; 846 pdev->irq = rle->start; 847 pdev->msi_enabled = true; 848 return (0); 849 } 850 851 static inline int 852 pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 853 unsigned int flags) 854 { 855 int error; 856 857 if (flags & PCI_IRQ_MSIX) { 858 struct msix_entry *entries; 859 int i; 860 861 entries = kcalloc(maxv, sizeof(*entries), GFP_KERNEL); 862 if (entries == NULL) { 863 error = -ENOMEM; 864 goto out; 865 } 866 for (i = 0; i < maxv; ++i) 867 entries[i].entry = i; 868 error = pci_enable_msix(pdev, entries, maxv); 869 out: 870 kfree(entries); 871 if (error == 0 && pdev->msix_enabled) 872 return (pdev->dev.irq_end - pdev->dev.irq_start); 873 } 874 if (flags & PCI_IRQ_MSI) { 875 error = pci_enable_msi(pdev); 876 if (error == 0 && pdev->msi_enabled) 877 return (pdev->dev.irq_end - pdev->dev.irq_start); 878 } 879 if (flags & PCI_IRQ_LEGACY) { 880 if (pdev->irq) 881 return (1); 882 } 883 884 return (-EINVAL); 885 } 886 887 static inline int 888 pci_channel_offline(struct pci_dev *pdev) 889 { 890 891 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 892 } 893 894 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 895 { 896 return -ENODEV; 897 } 898 static inline void pci_disable_sriov(struct pci_dev *dev) 899 { 900 } 901 902 static inline struct resource * 903 _lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size __unused) 904 { 905 struct pci_mmio_region *mmio, *p; 906 int type; 907 908 type = pci_resource_type(pdev, bar); 909 if (type < 0) { 910 device_printf(pdev->dev.bsddev, "%s: bar %d type %d\n", 911 __func__, bar, type); 912 return (NULL); 913 } 914 915 /* 916 * Check for duplicate mappings. 917 * This can happen if a driver calls pci_request_region() first. 918 */ 919 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 920 if (mmio->type == type && mmio->rid == PCIR_BAR(bar)) { 921 return (mmio->res); 922 } 923 } 924 925 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 926 mmio->rid = PCIR_BAR(bar); 927 mmio->type = type; 928 mmio->res = bus_alloc_resource_any(pdev->dev.bsddev, mmio->type, 929 &mmio->rid, RF_ACTIVE|RF_SHAREABLE); 930 if (mmio->res == NULL) { 931 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 932 "bar %d type %d rid %d\n", 933 __func__, bar, type, PCIR_BAR(bar)); 934 free(mmio, M_DEVBUF); 935 return (NULL); 936 } 937 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 938 939 return (mmio->res); 940 } 941 942 static inline void * 943 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 944 { 945 struct resource *res; 946 947 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 948 if (res == NULL) 949 return (NULL); 950 /* This is a FreeBSD extension so we can use bus_*(). */ 951 if (pdev->want_iomap_res) 952 return (res); 953 return ((void *)rman_get_bushandle(res)); 954 } 955 956 static inline void 957 pci_iounmap(struct pci_dev *pdev, void *res) 958 { 959 struct pci_mmio_region *mmio, *p; 960 961 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 962 if (res != (void *)rman_get_bushandle(mmio->res)) 963 continue; 964 bus_release_resource(pdev->dev.bsddev, 965 mmio->type, mmio->rid, mmio->res); 966 TAILQ_REMOVE(&pdev->mmio, mmio, next); 967 free(mmio, M_DEVBUF); 968 return; 969 } 970 } 971 972 static inline void 973 lkpi_pci_save_state(struct pci_dev *pdev) 974 { 975 976 pci_save_state(pdev->dev.bsddev); 977 } 978 979 static inline void 980 lkpi_pci_restore_state(struct pci_dev *pdev) 981 { 982 983 pci_restore_state(pdev->dev.bsddev); 984 } 985 986 #define pci_save_state(dev) lkpi_pci_save_state(dev) 987 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 988 989 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 990 const struct pci_device_id _table[] __devinitdata 991 992 /* XXX This should not be necessary. */ 993 #define pcix_set_mmrbc(d, v) 0 994 #define pcix_get_max_mmrbc(d) 0 995 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 996 997 #define PCI_DMA_BIDIRECTIONAL 0 998 #define PCI_DMA_TODEVICE 1 999 #define PCI_DMA_FROMDEVICE 2 1000 #define PCI_DMA_NONE 3 1001 1002 #define pci_pool dma_pool 1003 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 1004 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 1005 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 1006 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 1007 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 1008 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 1009 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1010 _size, _vaddr, _dma_handle) 1011 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 1012 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1013 _sg, _nents, (enum dma_data_direction)_dir) 1014 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 1015 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1016 (_ptr), (_size), (enum dma_data_direction)_dir) 1017 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 1018 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1019 _addr, _size, (enum dma_data_direction)_dir) 1020 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 1021 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1022 _sg, _nents, (enum dma_data_direction)_dir) 1023 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 1024 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 1025 _offset, _size, (enum dma_data_direction)_dir) 1026 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 1027 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1028 _dma_address, _size, (enum dma_data_direction)_dir) 1029 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1030 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1031 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1032 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1033 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1034 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1035 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1036 #define pci_unmap_addr dma_unmap_addr 1037 #define pci_unmap_addr_set dma_unmap_addr_set 1038 #define pci_unmap_len dma_unmap_len 1039 #define pci_unmap_len_set dma_unmap_len_set 1040 1041 typedef unsigned int __bitwise pci_channel_state_t; 1042 typedef unsigned int __bitwise pci_ers_result_t; 1043 1044 enum pci_channel_state { 1045 pci_channel_io_normal = 1, 1046 pci_channel_io_frozen = 2, 1047 pci_channel_io_perm_failure = 3, 1048 }; 1049 1050 enum pci_ers_result { 1051 PCI_ERS_RESULT_NONE = 1, 1052 PCI_ERS_RESULT_CAN_RECOVER = 2, 1053 PCI_ERS_RESULT_NEED_RESET = 3, 1054 PCI_ERS_RESULT_DISCONNECT = 4, 1055 PCI_ERS_RESULT_RECOVERED = 5, 1056 }; 1057 1058 /* PCI bus error event callbacks */ 1059 struct pci_error_handlers { 1060 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1061 enum pci_channel_state error); 1062 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1063 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1064 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1065 void (*resume)(struct pci_dev *dev); 1066 }; 1067 1068 /* FreeBSD does not support SRIOV - yet */ 1069 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1070 { 1071 return dev; 1072 } 1073 1074 static inline bool pci_is_pcie(struct pci_dev *dev) 1075 { 1076 return !!pci_pcie_cap(dev); 1077 } 1078 1079 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1080 { 1081 int pos; 1082 u16 reg16; 1083 1084 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1085 if (!pos) 1086 return 0; 1087 1088 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1089 1090 return reg16; 1091 } 1092 1093 static inline int pci_pcie_type(struct pci_dev *dev) 1094 { 1095 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1096 } 1097 1098 static inline int pcie_cap_version(struct pci_dev *dev) 1099 { 1100 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1101 } 1102 1103 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1104 { 1105 int type = pci_pcie_type(dev); 1106 1107 return pcie_cap_version(dev) > 1 || 1108 type == PCI_EXP_TYPE_ROOT_PORT || 1109 type == PCI_EXP_TYPE_ENDPOINT || 1110 type == PCI_EXP_TYPE_LEG_END; 1111 } 1112 1113 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1114 { 1115 return true; 1116 } 1117 1118 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1119 { 1120 int type = pci_pcie_type(dev); 1121 1122 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1123 (type == PCI_EXP_TYPE_DOWNSTREAM && 1124 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1125 } 1126 1127 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1128 { 1129 int type = pci_pcie_type(dev); 1130 1131 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1132 type == PCI_EXP_TYPE_RC_EC; 1133 } 1134 1135 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1136 { 1137 if (!pci_is_pcie(dev)) 1138 return false; 1139 1140 switch (pos) { 1141 case PCI_EXP_FLAGS_TYPE: 1142 return true; 1143 case PCI_EXP_DEVCAP: 1144 case PCI_EXP_DEVCTL: 1145 case PCI_EXP_DEVSTA: 1146 return pcie_cap_has_devctl(dev); 1147 case PCI_EXP_LNKCAP: 1148 case PCI_EXP_LNKCTL: 1149 case PCI_EXP_LNKSTA: 1150 return pcie_cap_has_lnkctl(dev); 1151 case PCI_EXP_SLTCAP: 1152 case PCI_EXP_SLTCTL: 1153 case PCI_EXP_SLTSTA: 1154 return pcie_cap_has_sltctl(dev); 1155 case PCI_EXP_RTCTL: 1156 case PCI_EXP_RTCAP: 1157 case PCI_EXP_RTSTA: 1158 return pcie_cap_has_rtctl(dev); 1159 case PCI_EXP_DEVCAP2: 1160 case PCI_EXP_DEVCTL2: 1161 case PCI_EXP_LNKCAP2: 1162 case PCI_EXP_LNKCTL2: 1163 case PCI_EXP_LNKSTA2: 1164 return pcie_cap_version(dev) > 1; 1165 default: 1166 return false; 1167 } 1168 } 1169 1170 static inline int 1171 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1172 { 1173 if (pos & 3) 1174 return -EINVAL; 1175 1176 if (!pcie_capability_reg_implemented(dev, pos)) 1177 return -EINVAL; 1178 1179 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1180 } 1181 1182 static inline int 1183 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1184 { 1185 if (pos & 3) 1186 return -EINVAL; 1187 1188 if (!pcie_capability_reg_implemented(dev, pos)) 1189 return -EINVAL; 1190 1191 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1192 } 1193 1194 static inline int 1195 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1196 { 1197 if (pos & 1) 1198 return -EINVAL; 1199 1200 if (!pcie_capability_reg_implemented(dev, pos)) 1201 return 0; 1202 1203 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1204 } 1205 1206 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1207 enum pci_bus_speed *speed, enum pcie_link_width *width) 1208 { 1209 *speed = PCI_SPEED_UNKNOWN; 1210 *width = PCIE_LNK_WIDTH_UNKNOWN; 1211 return (0); 1212 } 1213 1214 static inline int 1215 pci_num_vf(struct pci_dev *dev) 1216 { 1217 return (0); 1218 } 1219 1220 static inline enum pci_bus_speed 1221 pcie_get_speed_cap(struct pci_dev *dev) 1222 { 1223 device_t root; 1224 uint32_t lnkcap, lnkcap2; 1225 int error, pos; 1226 1227 root = device_get_parent(dev->dev.bsddev); 1228 if (root == NULL) 1229 return (PCI_SPEED_UNKNOWN); 1230 root = device_get_parent(root); 1231 if (root == NULL) 1232 return (PCI_SPEED_UNKNOWN); 1233 root = device_get_parent(root); 1234 if (root == NULL) 1235 return (PCI_SPEED_UNKNOWN); 1236 1237 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1238 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1239 return (PCI_SPEED_UNKNOWN); 1240 1241 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1242 return (PCI_SPEED_UNKNOWN); 1243 1244 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1245 1246 if (lnkcap2) { /* PCIe r3.0-compliant */ 1247 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1248 return (PCIE_SPEED_2_5GT); 1249 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1250 return (PCIE_SPEED_5_0GT); 1251 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1252 return (PCIE_SPEED_8_0GT); 1253 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1254 return (PCIE_SPEED_16_0GT); 1255 } else { /* pre-r3.0 */ 1256 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1257 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1258 return (PCIE_SPEED_2_5GT); 1259 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1260 return (PCIE_SPEED_5_0GT); 1261 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1262 return (PCIE_SPEED_8_0GT); 1263 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1264 return (PCIE_SPEED_16_0GT); 1265 } 1266 return (PCI_SPEED_UNKNOWN); 1267 } 1268 1269 static inline enum pcie_link_width 1270 pcie_get_width_cap(struct pci_dev *dev) 1271 { 1272 uint32_t lnkcap; 1273 1274 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1275 if (lnkcap) 1276 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1277 1278 return (PCIE_LNK_WIDTH_UNKNOWN); 1279 } 1280 1281 static inline int 1282 pcie_get_mps(struct pci_dev *dev) 1283 { 1284 return (pci_get_max_payload(dev->dev.bsddev)); 1285 } 1286 1287 static inline uint32_t 1288 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1289 { 1290 1291 switch(spd) { 1292 case PCIE_SPEED_16_0GT: 1293 return (16000 * 128 / 130); 1294 case PCIE_SPEED_8_0GT: 1295 return (8000 * 128 / 130); 1296 case PCIE_SPEED_5_0GT: 1297 return (5000 * 8 / 10); 1298 case PCIE_SPEED_2_5GT: 1299 return (2500 * 8 / 10); 1300 default: 1301 return (0); 1302 } 1303 } 1304 1305 static inline uint32_t 1306 pcie_bandwidth_available(struct pci_dev *pdev, 1307 struct pci_dev **limiting, 1308 enum pci_bus_speed *speed, 1309 enum pcie_link_width *width) 1310 { 1311 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1312 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1313 1314 if (speed) 1315 *speed = nspeed; 1316 if (width) 1317 *width = nwidth; 1318 1319 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1320 } 1321 1322 static inline struct pci_dev * 1323 pcie_find_root_port(struct pci_dev *pdev) 1324 { 1325 device_t root; 1326 1327 if (pdev->root != NULL) 1328 return (pdev->root); 1329 1330 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1331 if (root == NULL) 1332 return (NULL); 1333 1334 pdev->root = lkpinew_pci_dev(root); 1335 return (pdev->root); 1336 } 1337 1338 /* This is needed when people rip out the device "HotPlug". */ 1339 static inline void 1340 pci_lock_rescan_remove(void) 1341 { 1342 } 1343 1344 static inline void 1345 pci_unlock_rescan_remove(void) 1346 { 1347 } 1348 1349 static __inline void 1350 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1351 { 1352 } 1353 1354 /* 1355 * The following functions can be used to attach/detach the LinuxKPI's 1356 * PCI device runtime. The pci_driver and pci_device_id pointer is 1357 * allowed to be NULL. Other pointers must be all valid. 1358 * The pci_dev structure should be zero-initialized before passed 1359 * to the linux_pci_attach_device function. 1360 */ 1361 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1362 const struct pci_device_id *, struct pci_dev *); 1363 extern int linux_pci_detach_device(struct pci_dev *); 1364 1365 static inline int 1366 pci_dev_present(const struct pci_device_id *cur) 1367 { 1368 while (cur != NULL && (cur->vendor || cur->device)) { 1369 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1370 return (1); 1371 } 1372 cur++; 1373 } 1374 return (0); 1375 } 1376 1377 static inline bool 1378 pci_is_root_bus(struct pci_bus *pbus) 1379 { 1380 1381 return (pbus->self == NULL); 1382 } 1383 1384 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1385 unsigned int bus, unsigned int devfn); 1386 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1387 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1388 1389 static inline int 1390 pci_domain_nr(struct pci_bus *pbus) 1391 { 1392 1393 return (pbus->domain); 1394 } 1395 1396 static inline int 1397 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1398 int pos, uint32_t *val, int len) 1399 { 1400 1401 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1402 return (0); 1403 } 1404 1405 static inline int 1406 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1407 { 1408 uint32_t tmp; 1409 int ret; 1410 1411 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1412 *val = (u16)tmp; 1413 return (ret); 1414 } 1415 1416 static inline int 1417 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1418 { 1419 uint32_t tmp; 1420 int ret; 1421 1422 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1423 *val = (u8)tmp; 1424 return (ret); 1425 } 1426 1427 static inline int 1428 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1429 uint32_t val, int size) 1430 { 1431 1432 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1433 return (0); 1434 } 1435 1436 static inline int 1437 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1438 uint8_t val) 1439 { 1440 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1441 } 1442 1443 static inline int 1444 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1445 uint16_t val) 1446 { 1447 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1448 } 1449 1450 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1451 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1452 1453 /* -------------------------------------------------------------------------- */ 1454 1455 static inline int 1456 pcim_enable_device(struct pci_dev *pdev) 1457 { 1458 struct pci_devres *dr; 1459 int error; 1460 1461 /* Here we cannot run through the pdev->managed check. */ 1462 dr = lkpi_pci_devres_get_alloc(pdev); 1463 if (dr == NULL) 1464 return (-ENOMEM); 1465 1466 /* If resources were enabled before do not do it again. */ 1467 if (dr->enable_io) 1468 return (0); 1469 1470 error = pci_enable_device(pdev); 1471 if (error == 0) 1472 dr->enable_io = true; 1473 1474 /* This device is not managed. */ 1475 pdev->managed = true; 1476 1477 return (error); 1478 } 1479 1480 static inline struct pcim_iomap_devres * 1481 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev) 1482 { 1483 struct pcim_iomap_devres *dr; 1484 1485 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release, 1486 NULL, NULL); 1487 if (dr == NULL) { 1488 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release, 1489 sizeof(*dr), GFP_KERNEL | __GFP_ZERO); 1490 if (dr != NULL) 1491 lkpi_devres_add(&pdev->dev, dr); 1492 } 1493 1494 if (dr == NULL) 1495 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__); 1496 1497 return (dr); 1498 } 1499 1500 static inline void __iomem ** 1501 pcim_iomap_table(struct pci_dev *pdev) 1502 { 1503 struct pcim_iomap_devres *dr; 1504 1505 dr = lkpi_pcim_iomap_devres_find(pdev); 1506 if (dr == NULL) 1507 return (NULL); 1508 1509 /* 1510 * If the driver has manually set a flag to be able to request the 1511 * resource to use bus_read/write_<n>, return the shadow table. 1512 */ 1513 if (pdev->want_iomap_res) 1514 return ((void **)dr->res_table); 1515 1516 /* This is the Linux default. */ 1517 return (dr->mmio_table); 1518 } 1519 1520 static inline int 1521 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1522 { 1523 struct pcim_iomap_devres *dr; 1524 void *res; 1525 uint32_t mappings, requests, req_mask; 1526 int bar, error; 1527 1528 dr = lkpi_pcim_iomap_devres_find(pdev); 1529 if (dr == NULL) 1530 return (-ENOMEM); 1531 1532 /* Request all the BARs ("regions") we do not iomap. */ 1533 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1534 for (bar = requests = 0; requests != req_mask; bar++) { 1535 if ((req_mask & (1 << bar)) == 0) 1536 continue; 1537 error = pci_request_region(pdev, bar, name); 1538 if (error != 0 && error != -ENODEV) 1539 goto err; 1540 requests |= (1 << bar); 1541 } 1542 1543 /* Now iomap all the requested (by "mask") ones. */ 1544 for (bar = mappings = 0; mappings != mask; bar++) { 1545 if ((mask & (1 << bar)) == 0) 1546 continue; 1547 1548 /* Request double is not allowed. */ 1549 if (dr->mmio_table[bar] != NULL) { 1550 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1551 __func__, bar, dr->mmio_table[bar]); 1552 goto err; 1553 } 1554 1555 res = _lkpi_pci_iomap(pdev, bar, 0); 1556 if (res == NULL) 1557 goto err; 1558 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1559 dr->res_table[bar] = res; 1560 1561 mappings |= (1 << bar); 1562 } 1563 1564 return (0); 1565 1566 err: 1567 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1568 if ((mappings & (1 << bar)) != 0) { 1569 res = dr->mmio_table[bar]; 1570 if (res == NULL) 1571 continue; 1572 pci_iounmap(pdev, res); 1573 } else if ((requests & (1 << bar)) != 0) { 1574 pci_release_region(pdev, bar); 1575 } 1576 } 1577 1578 return (-EINVAL); 1579 } 1580 1581 /* This is a FreeBSD extension so we can use bus_*(). */ 1582 static inline void 1583 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1584 { 1585 pdev->want_iomap_res = true; 1586 } 1587 1588 #endif /* _LINUX_PCI_H_ */ 1589