xref: /freebsd/sys/compat/linuxkpi/common/include/linux/pci.h (revision 924226fba12cc9a228c73b956e1b7fa24c60b055)
1 /*-
2  * Copyright (c) 2010 Isilon Systems, Inc.
3  * Copyright (c) 2010 iX Systems, Inc.
4  * Copyright (c) 2010 Panasas, Inc.
5  * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
6  * All rights reserved.
7  * Copyright (c) 2020-2021 The FreeBSD Foundation
8  *
9  * Portions of this software were developed by Björn Zeeb
10  * under sponsorship from the FreeBSD Foundation.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice unmodified, this list of conditions, and the following
17  *    disclaimer.
18  * 2. Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the distribution.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD$
34  */
35 #ifndef	_LINUXKPI_LINUX_PCI_H_
36 #define	_LINUXKPI_LINUX_PCI_H_
37 
38 #define	CONFIG_PCI_MSI
39 
40 #include <linux/types.h>
41 
42 #include <sys/param.h>
43 #include <sys/bus.h>
44 #include <sys/module.h>
45 #include <sys/nv.h>
46 #include <sys/pciio.h>
47 #include <sys/rman.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pci_private.h>
51 
52 #include <machine/resource.h>
53 
54 #include <linux/list.h>
55 #include <linux/dmapool.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/compiler.h>
58 #include <linux/errno.h>
59 #include <asm/atomic.h>
60 #include <linux/device.h>
61 #include <linux/pci_ids.h>
62 #include <linux/pm.h>
63 
64 struct pci_device_id {
65 	uint32_t	vendor;
66 	uint32_t	device;
67 	uint32_t	subvendor;
68 	uint32_t	subdevice;
69 	uint32_t	class;
70 	uint32_t	class_mask;
71 	uintptr_t	driver_data;
72 };
73 
74 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */
75 #define	MODULE_DEVICE_TABLE(_bus, _table)				\
76 									\
77 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = {	\
78 	DEVMETHOD_END							\
79 };									\
80 									\
81 static driver_t _ ## _bus ## _ ## _table ## _driver = {			\
82 	"lkpi_" #_bus #_table,						\
83 	_ ## _bus ## _ ## _table ## _methods,				\
84 	0								\
85 };									\
86 									\
87 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\
88 	0, 0);								\
89 									\
90 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice",	\
91     _bus, lkpi_ ## _table, _table, nitems(_table) - 1)
92 
93 #define	PCI_ANY_ID			-1U
94 
95 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
96 #define PCI_SLOT(devfn)		(((devfn) >> 3) & 0x1f)
97 #define PCI_FUNC(devfn)		((devfn) & 0x07)
98 #define	PCI_BUS_NUM(devfn)	(((devfn) >> 8) & 0xff)
99 
100 #define PCI_VDEVICE(_vendor, _device)					\
101 	    .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device),	\
102 	    .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
103 #define	PCI_DEVICE(_vendor, _device)					\
104 	    .vendor = (_vendor), .device = (_device),			\
105 	    .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
106 
107 #define	to_pci_dev(n)	container_of(n, struct pci_dev, dev)
108 
109 #define	PCI_VENDOR_ID		PCIR_DEVVENDOR
110 #define	PCI_COMMAND		PCIR_COMMAND
111 #define	PCI_COMMAND_INTX_DISABLE	PCIM_CMD_INTxDIS
112 #define	PCI_EXP_DEVCTL		PCIER_DEVICE_CTL		/* Device Control */
113 #define	PCI_EXP_LNKCTL		PCIER_LINK_CTL			/* Link Control */
114 #define	PCI_EXP_LNKCTL_ASPM_L0S	PCIEM_LINK_CTL_ASPMC_L0S
115 #define	PCI_EXP_LNKCTL_ASPM_L1	PCIEM_LINK_CTL_ASPMC_L1
116 #define PCI_EXP_LNKCTL_ASPMC	PCIEM_LINK_CTL_ASPMC
117 #define	PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM		/* Enable clock PM */
118 #define PCI_EXP_LNKCTL_HAWD	PCIEM_LINK_CTL_HAWD
119 #define	PCI_EXP_FLAGS_TYPE	PCIEM_FLAGS_TYPE		/* Device/Port type */
120 #define	PCI_EXP_DEVCAP		PCIER_DEVICE_CAP		/* Device capabilities */
121 #define	PCI_EXP_DEVSTA		PCIER_DEVICE_STA		/* Device Status */
122 #define	PCI_EXP_LNKCAP		PCIER_LINK_CAP			/* Link Capabilities */
123 #define	PCI_EXP_LNKSTA		PCIER_LINK_STA			/* Link Status */
124 #define	PCI_EXP_SLTCAP		PCIER_SLOT_CAP			/* Slot Capabilities */
125 #define	PCI_EXP_SLTCTL		PCIER_SLOT_CTL			/* Slot Control */
126 #define	PCI_EXP_SLTSTA		PCIER_SLOT_STA			/* Slot Status */
127 #define	PCI_EXP_RTCTL		PCIER_ROOT_CTL			/* Root Control */
128 #define	PCI_EXP_RTCAP		PCIER_ROOT_CAP			/* Root Capabilities */
129 #define	PCI_EXP_RTSTA		PCIER_ROOT_STA			/* Root Status */
130 #define	PCI_EXP_DEVCAP2		PCIER_DEVICE_CAP2		/* Device Capabilities 2 */
131 #define	PCI_EXP_DEVCTL2		PCIER_DEVICE_CTL2		/* Device Control 2 */
132 #define	PCI_EXP_DEVCTL2_LTR_EN	PCIEM_CTL2_LTR_ENABLE
133 #define	PCI_EXP_DEVCTL2_COMP_TMOUT_DIS	PCIEM_CTL2_COMP_TIMO_DISABLE
134 #define	PCI_EXP_LNKCAP2		PCIER_LINK_CAP2			/* Link Capabilities 2 */
135 #define	PCI_EXP_LNKCTL2		PCIER_LINK_CTL2			/* Link Control 2 */
136 #define	PCI_EXP_LNKSTA2		PCIER_LINK_STA2			/* Link Status 2 */
137 #define	PCI_EXP_FLAGS		PCIER_FLAGS			/* Capabilities register */
138 #define	PCI_EXP_FLAGS_VERS	PCIEM_FLAGS_VERSION		/* Capability version */
139 #define	PCI_EXP_TYPE_ROOT_PORT	PCIEM_TYPE_ROOT_PORT		/* Root Port */
140 #define	PCI_EXP_TYPE_ENDPOINT	PCIEM_TYPE_ENDPOINT		/* Express Endpoint */
141 #define	PCI_EXP_TYPE_LEG_END	PCIEM_TYPE_LEGACY_ENDPOINT	/* Legacy Endpoint */
142 #define	PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT	/* Downstream Port */
143 #define	PCI_EXP_FLAGS_SLOT	PCIEM_FLAGS_SLOT		/* Slot implemented */
144 #define	PCI_EXP_TYPE_RC_EC	PCIEM_TYPE_ROOT_EC		/* Root Complex Event Collector */
145 #define	PCI_EXP_LNKCAP_SLS_2_5GB 0x01	/* Supported Link Speed 2.5GT/s */
146 #define	PCI_EXP_LNKCAP_SLS_5_0GB 0x02	/* Supported Link Speed 5.0GT/s */
147 #define	PCI_EXP_LNKCAP_SLS_8_0GB 0x04	/* Supported Link Speed 8.0GT/s */
148 #define	PCI_EXP_LNKCAP_SLS_16_0GB 0x08	/* Supported Link Speed 16.0GT/s */
149 #define	PCI_EXP_LNKCAP_MLW	0x03f0	/* Maximum Link Width */
150 #define	PCI_EXP_LNKCAP2_SLS_2_5GB 0x02	/* Supported Link Speed 2.5GT/s */
151 #define	PCI_EXP_LNKCAP2_SLS_5_0GB 0x04	/* Supported Link Speed 5.0GT/s */
152 #define	PCI_EXP_LNKCAP2_SLS_8_0GB 0x08	/* Supported Link Speed 8.0GT/s */
153 #define	PCI_EXP_LNKCAP2_SLS_16_0GB 0x10	/* Supported Link Speed 16.0GT/s */
154 #define	PCI_EXP_LNKCTL2_TLS		0x000f
155 #define	PCI_EXP_LNKCTL2_TLS_2_5GT	0x0001	/* Supported Speed 2.5GT/s */
156 #define	PCI_EXP_LNKCTL2_TLS_5_0GT	0x0002	/* Supported Speed 5GT/s */
157 #define	PCI_EXP_LNKCTL2_TLS_8_0GT	0x0003	/* Supported Speed 8GT/s */
158 #define	PCI_EXP_LNKCTL2_TLS_16_0GT	0x0004	/* Supported Speed 16GT/s */
159 #define	PCI_EXP_LNKCTL2_TLS_32_0GT	0x0005	/* Supported Speed 32GT/s */
160 #define	PCI_EXP_LNKCTL2_ENTER_COMP	0x0010	/* Enter Compliance */
161 #define	PCI_EXP_LNKCTL2_TX_MARGIN	0x0380	/* Transmit Margin */
162 
163 #define PCI_EXP_LNKCAP_CLKPM	0x00040000
164 #define PCI_EXP_DEVSTA_TRPND	0x0020
165 
166 #define	IORESOURCE_MEM	(1 << SYS_RES_MEMORY)
167 #define	IORESOURCE_IO	(1 << SYS_RES_IOPORT)
168 #define	IORESOURCE_IRQ	(1 << SYS_RES_IRQ)
169 
170 enum pci_bus_speed {
171 	PCI_SPEED_UNKNOWN = -1,
172 	PCIE_SPEED_2_5GT,
173 	PCIE_SPEED_5_0GT,
174 	PCIE_SPEED_8_0GT,
175 	PCIE_SPEED_16_0GT,
176 };
177 
178 enum pcie_link_width {
179 	PCIE_LNK_WIDTH_RESRV	= 0x00,
180 	PCIE_LNK_X1		= 0x01,
181 	PCIE_LNK_X2		= 0x02,
182 	PCIE_LNK_X4		= 0x04,
183 	PCIE_LNK_X8		= 0x08,
184 	PCIE_LNK_X12		= 0x0c,
185 	PCIE_LNK_X16		= 0x10,
186 	PCIE_LNK_X32		= 0x20,
187 	PCIE_LNK_WIDTH_UNKNOWN	= 0xff,
188 };
189 
190 #define	PCIE_LINK_STATE_L0S		0x00000001
191 #define	PCIE_LINK_STATE_L1		0x00000002
192 #define	PCIE_LINK_STATE_CLKPM		0x00000004
193 
194 typedef int pci_power_t;
195 
196 #define PCI_D0	PCI_POWERSTATE_D0
197 #define PCI_D1	PCI_POWERSTATE_D1
198 #define PCI_D2	PCI_POWERSTATE_D2
199 #define PCI_D3hot	PCI_POWERSTATE_D3
200 #define PCI_D3cold	4
201 
202 #define PCI_POWER_ERROR	PCI_POWERSTATE_UNKNOWN
203 
204 #define	PCI_ERR_ROOT_COMMAND		PCIR_AER_ROOTERR_CMD
205 #define	PCI_ERR_ROOT_ERR_SRC		PCIR_AER_COR_SOURCE_ID
206 
207 #define	PCI_EXT_CAP_ID_ERR		PCIZ_AER
208 #define	PCI_EXT_CAP_ID_L1SS		PCIZ_L1PM
209 
210 #define	PCI_L1SS_CTL1			0x8
211 #define	PCI_L1SS_CTL1_L1SS_MASK		0xf
212 
213 #define	PCI_IRQ_LEGACY			0x01
214 #define	PCI_IRQ_MSI			0x02
215 #define	PCI_IRQ_MSIX			0x04
216 
217 struct pci_dev;
218 
219 struct pci_driver {
220 	struct list_head		node;
221 	char				*name;
222 	const struct pci_device_id		*id_table;
223 	int  (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
224 	void (*remove)(struct pci_dev *dev);
225 	int  (*suspend) (struct pci_dev *dev, pm_message_t state);	/* Device suspended */
226 	int  (*resume) (struct pci_dev *dev);		/* Device woken up */
227 	void (*shutdown) (struct pci_dev *dev);		/* Device shutdown */
228 	driver_t			bsddriver;
229 	devclass_t			bsdclass;
230 	struct device_driver		driver;
231 	const struct pci_error_handlers       *err_handler;
232 	bool				isdrm;
233 	int				bsd_probe_return;
234 	int  (*bsd_iov_init)(device_t dev, uint16_t num_vfs,
235 	    const nvlist_t *pf_config);
236 	void  (*bsd_iov_uninit)(device_t dev);
237 	int  (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum,
238 	    const nvlist_t *vf_config);
239 };
240 
241 struct pci_bus {
242 	struct pci_dev	*self;
243 	int		domain;
244 	int		number;
245 };
246 
247 extern struct list_head pci_drivers;
248 extern struct list_head pci_devices;
249 extern spinlock_t pci_lock;
250 
251 #define	__devexit_p(x)	x
252 
253 #define module_pci_driver(_driver)					\
254 									\
255 static inline int							\
256 _pci_init(void)								\
257 {									\
258 									\
259 	return (linux_pci_register_driver(&_driver));			\
260 }									\
261 									\
262 static inline void							\
263 _pci_exit(void)								\
264 {									\
265 									\
266 	linux_pci_unregister_driver(&_driver);				\
267 }									\
268 									\
269 module_init(_pci_init);							\
270 module_exit(_pci_exit)
271 
272 /*
273  * If we find drivers accessing this from multiple KPIs we may have to
274  * refcount objects of this structure.
275  */
276 struct pci_mmio_region {
277 	TAILQ_ENTRY(pci_mmio_region)	next;
278 	struct resource			*res;
279 	int				rid;
280 	int				type;
281 };
282 
283 struct pci_dev {
284 	struct device		dev;
285 	struct list_head	links;
286 	struct pci_driver	*pdrv;
287 	struct pci_bus		*bus;
288 	struct pci_dev		*root;
289 	uint16_t		device;
290 	uint16_t		vendor;
291 	uint16_t		subsystem_vendor;
292 	uint16_t		subsystem_device;
293 	unsigned int		irq;
294 	unsigned int		devfn;
295 	uint32_t		class;
296 	uint8_t			revision;
297 	bool			managed;	/* devres "pcim_*(). */
298 	bool			want_iomap_res;
299 	bool			msi_enabled;
300 	bool			msix_enabled;
301 	phys_addr_t		rom;
302 	size_t			romlen;
303 
304 	TAILQ_HEAD(, pci_mmio_region)	mmio;
305 };
306 
307 /* We need some meta-struct to keep track of these for devres. */
308 struct pci_devres {
309 	bool		enable_io;
310 	/* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */
311 	uint8_t		region_mask;
312 	struct resource	*region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */
313 };
314 struct pcim_iomap_devres {
315 	void		*mmio_table[PCIR_MAX_BAR_0 + 1];
316 	struct resource	*res_table[PCIR_MAX_BAR_0 + 1];
317 };
318 
319 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name);
320 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv,
321     unsigned int flags);
322 
323 /* Internal helper function(s). */
324 struct pci_dev *lkpinew_pci_dev(device_t);
325 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev);
326 void lkpi_pci_devres_release(struct device *, void *);
327 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size);
328 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev);
329 void lkpi_pcim_iomap_table_release(struct device *, void *);
330 
331 static inline int
332 pci_resource_type(struct pci_dev *pdev, int bar)
333 {
334 	struct pci_map *pm;
335 
336 	pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar));
337 	if (!pm)
338 		return (-1);
339 
340 	if (PCI_BAR_IO(pm->pm_value))
341 		return (SYS_RES_IOPORT);
342 	else
343 		return (SYS_RES_MEMORY);
344 }
345 
346 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev,
347 		    struct resource_list *rl, int type, int rid);
348 
349 static inline struct resource_list_entry *
350 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar)
351 {
352 	struct pci_devinfo *dinfo;
353 	struct resource_list *rl;
354 	struct resource_list_entry *rle;
355 
356 	dinfo = device_get_ivars(pdev->dev.bsddev);
357 	rl = &dinfo->resources;
358 	rle = resource_list_find(rl, type, rid);
359 	/* Reserve resources for this BAR if needed. */
360 	if (rle == NULL && reserve_bar)
361 		rle = linux_pci_reserve_bar(pdev, rl, type, rid);
362 	return (rle);
363 }
364 
365 static inline struct resource_list_entry *
366 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve)
367 {
368 	int type;
369 
370 	type = pci_resource_type(pdev, bar);
371 	if (type < 0)
372 		return (NULL);
373 	bar = PCIR_BAR(bar);
374 	return (linux_pci_get_rle(pdev, type, bar, reserve));
375 }
376 
377 static inline struct device *
378 linux_pci_find_irq_dev(unsigned int irq)
379 {
380 	struct pci_dev *pdev;
381 	struct device *found;
382 
383 	found = NULL;
384 	spin_lock(&pci_lock);
385 	list_for_each_entry(pdev, &pci_devices, links) {
386 		if (irq == pdev->dev.irq ||
387 		    (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) {
388 			found = &pdev->dev;
389 			break;
390 		}
391 	}
392 	spin_unlock(&pci_lock);
393 	return (found);
394 }
395 
396 /*
397  * All drivers just seem to want to inspect the type not flags.
398  */
399 static inline int
400 pci_resource_flags(struct pci_dev *pdev, int bar)
401 {
402 	int type;
403 
404 	type = pci_resource_type(pdev, bar);
405 	if (type < 0)
406 		return (0);
407 	return (1 << type);
408 }
409 
410 static inline const char *
411 pci_name(struct pci_dev *d)
412 {
413 
414 	return device_get_desc(d->dev.bsddev);
415 }
416 
417 static inline void *
418 pci_get_drvdata(struct pci_dev *pdev)
419 {
420 
421 	return dev_get_drvdata(&pdev->dev);
422 }
423 
424 static inline void
425 pci_set_drvdata(struct pci_dev *pdev, void *data)
426 {
427 
428 	dev_set_drvdata(&pdev->dev, data);
429 }
430 
431 static inline struct pci_dev *
432 pci_dev_get(struct pci_dev *pdev)
433 {
434 
435 	if (pdev != NULL)
436 		get_device(&pdev->dev);
437 	return (pdev);
438 }
439 
440 static __inline void
441 pci_dev_put(struct pci_dev *pdev)
442 {
443 
444 	if (pdev != NULL)
445 		put_device(&pdev->dev);
446 }
447 
448 static inline int
449 pci_enable_device(struct pci_dev *pdev)
450 {
451 
452 	pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
453 	pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
454 	return (0);
455 }
456 
457 static inline void
458 pci_disable_device(struct pci_dev *pdev)
459 {
460 
461 	pci_disable_busmaster(pdev->dev.bsddev);
462 }
463 
464 static inline int
465 pci_set_master(struct pci_dev *pdev)
466 {
467 
468 	pci_enable_busmaster(pdev->dev.bsddev);
469 	return (0);
470 }
471 
472 static inline int
473 pci_set_power_state(struct pci_dev *pdev, int state)
474 {
475 
476 	pci_set_powerstate(pdev->dev.bsddev, state);
477 	return (0);
478 }
479 
480 static inline int
481 pci_clear_master(struct pci_dev *pdev)
482 {
483 
484 	pci_disable_busmaster(pdev->dev.bsddev);
485 	return (0);
486 }
487 
488 static inline bool
489 pci_is_root_bus(struct pci_bus *pbus)
490 {
491 
492 	return (pbus->self == NULL);
493 }
494 
495 static inline struct pci_dev *
496 pci_upstream_bridge(struct pci_dev *pdev)
497 {
498 
499 	if (pci_is_root_bus(pdev->bus))
500 		return (NULL);
501 
502 	/*
503 	 * If we do not have a (proper) "upstream bridge" set, e.g., we point
504 	 * to ourselves, try to handle this case on the fly like we do
505 	 * for pcie_find_root_port().
506 	 */
507 	if (pdev == pdev->bus->self) {
508 		device_t bridge;
509 
510 		bridge = device_get_parent(pdev->dev.bsddev);
511 		if (bridge == NULL)
512 			goto done;
513 		bridge = device_get_parent(bridge);
514 		if (bridge == NULL)
515 			goto done;
516 		if (device_get_devclass(device_get_parent(bridge)) !=
517 		    devclass_find("pci"))
518 			goto done;
519 
520 		/*
521 		 * "bridge" is a PCI-to-PCI bridge.  Create a Linux pci_dev
522 		 * for it so it can be returned.
523 		 */
524 		pdev->bus->self = lkpinew_pci_dev(bridge);
525 	}
526 done:
527 	return (pdev->bus->self);
528 }
529 
530 static inline struct pci_devres *
531 lkpi_pci_devres_find(struct pci_dev *pdev)
532 {
533 
534 	if (!pdev->managed)
535 		return (NULL);
536 
537 	return (lkpi_pci_devres_get_alloc(pdev));
538 }
539 
540 static inline void
541 pci_release_region(struct pci_dev *pdev, int bar)
542 {
543 	struct resource_list_entry *rle;
544 	struct pci_devres *dr;
545 	struct pci_mmio_region *mmio, *p;
546 
547 	if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL)
548 		return;
549 
550 	/*
551 	 * As we implicitly track the requests we also need to clear them on
552 	 * release.  Do clear before resource release.
553 	 */
554 	dr = lkpi_pci_devres_find(pdev);
555 	if (dr != NULL) {
556 		KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d"
557 		    " region_table res %p != rel->res %p\n", __func__, pdev,
558 		    bar, dr->region_table[bar], rle->res));
559 		dr->region_table[bar] = NULL;
560 		dr->region_mask &= ~(1 << bar);
561 	}
562 
563 	TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) {
564 		if (rle->res != (void *)rman_get_bushandle(mmio->res))
565 			continue;
566 		TAILQ_REMOVE(&pdev->mmio, mmio, next);
567 		free(mmio, M_DEVBUF);
568 	}
569 
570 	bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res);
571 }
572 
573 static inline void
574 pci_release_regions(struct pci_dev *pdev)
575 {
576 	int i;
577 
578 	for (i = 0; i <= PCIR_MAX_BAR_0; i++)
579 		pci_release_region(pdev, i);
580 }
581 
582 static inline int
583 pci_request_regions(struct pci_dev *pdev, const char *res_name)
584 {
585 	int error;
586 	int i;
587 
588 	for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
589 		error = pci_request_region(pdev, i, res_name);
590 		if (error && error != -ENODEV) {
591 			pci_release_regions(pdev);
592 			return (error);
593 		}
594 	}
595 	return (0);
596 }
597 
598 static inline void
599 lkpi_pci_disable_msix(struct pci_dev *pdev)
600 {
601 
602 	pci_release_msi(pdev->dev.bsddev);
603 
604 	/*
605 	 * The MSIX IRQ numbers associated with this PCI device are no
606 	 * longer valid and might be re-assigned. Make sure
607 	 * linux_pci_find_irq_dev() does no longer see them by
608 	 * resetting their references to zero:
609 	 */
610 	pdev->dev.irq_start = 0;
611 	pdev->dev.irq_end = 0;
612 	pdev->msix_enabled = false;
613 }
614 /* Only for consistency. No conflict on that one. */
615 #define	pci_disable_msix(pdev)		lkpi_pci_disable_msix(pdev)
616 
617 static inline void
618 lkpi_pci_disable_msi(struct pci_dev *pdev)
619 {
620 
621 	pci_release_msi(pdev->dev.bsddev);
622 
623 	pdev->dev.irq_start = 0;
624 	pdev->dev.irq_end = 0;
625 	pdev->irq = pdev->dev.irq;
626 	pdev->msi_enabled = false;
627 }
628 #define	pci_disable_msi(pdev)		lkpi_pci_disable_msi(pdev)
629 #define	pci_free_irq_vectors(pdev)	lkpi_pci_disable_msi(pdev)
630 
631 unsigned long	pci_resource_start(struct pci_dev *pdev, int bar);
632 unsigned long	pci_resource_len(struct pci_dev *pdev, int bar);
633 
634 static inline bus_addr_t
635 pci_bus_address(struct pci_dev *pdev, int bar)
636 {
637 
638 	return (pci_resource_start(pdev, bar));
639 }
640 
641 #define	PCI_CAP_ID_EXP	PCIY_EXPRESS
642 #define	PCI_CAP_ID_PCIX	PCIY_PCIX
643 #define PCI_CAP_ID_AGP  PCIY_AGP
644 #define PCI_CAP_ID_PM   PCIY_PMG
645 
646 #define PCI_EXP_DEVCTL		PCIER_DEVICE_CTL
647 #define PCI_EXP_DEVCTL_PAYLOAD	PCIEM_CTL_MAX_PAYLOAD
648 #define PCI_EXP_DEVCTL_READRQ	PCIEM_CTL_MAX_READ_REQUEST
649 #define PCI_EXP_LNKCTL		PCIER_LINK_CTL
650 #define PCI_EXP_LNKSTA		PCIER_LINK_STA
651 
652 static inline int
653 pci_find_capability(struct pci_dev *pdev, int capid)
654 {
655 	int reg;
656 
657 	if (pci_find_cap(pdev->dev.bsddev, capid, &reg))
658 		return (0);
659 	return (reg);
660 }
661 
662 static inline int pci_pcie_cap(struct pci_dev *dev)
663 {
664 	return pci_find_capability(dev, PCI_CAP_ID_EXP);
665 }
666 
667 static inline int
668 pci_find_ext_capability(struct pci_dev *pdev, int capid)
669 {
670 	int reg;
671 
672 	if (pci_find_extcap(pdev->dev.bsddev, capid, &reg))
673 		return (0);
674 	return (reg);
675 }
676 
677 #define	PCIM_PCAP_PME_SHIFT	11
678 static __inline bool
679 pci_pme_capable(struct pci_dev *pdev, uint32_t flag)
680 {
681 	struct pci_devinfo *dinfo;
682 	pcicfgregs *cfg;
683 
684 	if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT))
685 		return (false);
686 
687 	dinfo = device_get_ivars(pdev->dev.bsddev);
688 	cfg = &dinfo->cfg;
689 
690 	if (cfg->pp.pp_cap == 0)
691 		return (false);
692 
693 	if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0)
694 		return (true);
695 
696 	return (false);
697 }
698 
699 static inline int
700 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags)
701 {
702 
703 	if (!pci_enable_aspm)
704 		return (-EPERM);
705 
706 	return (-ENXIO);
707 }
708 
709 static inline int
710 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val)
711 {
712 
713 	*val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);
714 	return (0);
715 }
716 
717 static inline int
718 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val)
719 {
720 
721 	*val = (u16)pci_read_config(pdev->dev.bsddev, where, 2);
722 	return (0);
723 }
724 
725 static inline int
726 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val)
727 {
728 
729 	*val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
730 	return (0);
731 }
732 
733 static inline int
734 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val)
735 {
736 
737 	pci_write_config(pdev->dev.bsddev, where, val, 1);
738 	return (0);
739 }
740 
741 static inline int
742 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val)
743 {
744 
745 	pci_write_config(pdev->dev.bsddev, where, val, 2);
746 	return (0);
747 }
748 
749 static inline int
750 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val)
751 {
752 
753 	pci_write_config(pdev->dev.bsddev, where, val, 4);
754 	return (0);
755 }
756 
757 int	linux_pci_register_driver(struct pci_driver *pdrv);
758 int	linux_pci_register_drm_driver(struct pci_driver *pdrv);
759 void	linux_pci_unregister_driver(struct pci_driver *pdrv);
760 void	linux_pci_unregister_drm_driver(struct pci_driver *pdrv);
761 
762 #define	pci_register_driver(pdrv)	linux_pci_register_driver(pdrv)
763 #define	pci_unregister_driver(pdrv)	linux_pci_unregister_driver(pdrv)
764 
765 struct msix_entry {
766 	int entry;
767 	int vector;
768 };
769 
770 /*
771  * Enable msix, positive errors indicate actual number of available
772  * vectors.  Negative errors are failures.
773  *
774  * NB: define added to prevent this definition of pci_enable_msix from
775  * clashing with the native FreeBSD version.
776  */
777 #define	pci_enable_msix(...) \
778   linux_pci_enable_msix(__VA_ARGS__)
779 
780 static inline int
781 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq)
782 {
783 	struct resource_list_entry *rle;
784 	int error;
785 	int avail;
786 	int i;
787 
788 	avail = pci_msix_count(pdev->dev.bsddev);
789 	if (avail < nreq) {
790 		if (avail == 0)
791 			return -EINVAL;
792 		return avail;
793 	}
794 	avail = nreq;
795 	if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0)
796 		return error;
797 	/*
798 	 * Handle case where "pci_alloc_msix()" may allocate less
799 	 * interrupts than available and return with no error:
800 	 */
801 	if (avail < nreq) {
802 		pci_release_msi(pdev->dev.bsddev);
803 		return avail;
804 	}
805 	rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false);
806 	pdev->dev.irq_start = rle->start;
807 	pdev->dev.irq_end = rle->start + avail;
808 	for (i = 0; i < nreq; i++)
809 		entries[i].vector = pdev->dev.irq_start + i;
810 	pdev->msix_enabled = true;
811 	return (0);
812 }
813 
814 #define	pci_enable_msix_range(...) \
815   linux_pci_enable_msix_range(__VA_ARGS__)
816 
817 static inline int
818 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
819     int minvec, int maxvec)
820 {
821 	int nvec = maxvec;
822 	int rc;
823 
824 	if (maxvec < minvec)
825 		return (-ERANGE);
826 
827 	do {
828 		rc = pci_enable_msix(dev, entries, nvec);
829 		if (rc < 0) {
830 			return (rc);
831 		} else if (rc > 0) {
832 			if (rc < minvec)
833 				return (-ENOSPC);
834 			nvec = rc;
835 		}
836 	} while (rc);
837 	return (nvec);
838 }
839 
840 #define	pci_enable_msi(pdev) \
841   linux_pci_enable_msi(pdev)
842 
843 static inline int
844 pci_enable_msi(struct pci_dev *pdev)
845 {
846 	struct resource_list_entry *rle;
847 	int error;
848 	int avail;
849 
850 	avail = pci_msi_count(pdev->dev.bsddev);
851 	if (avail < 1)
852 		return -EINVAL;
853 
854 	avail = 1;	/* this function only enable one MSI IRQ */
855 	if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0)
856 		return error;
857 
858 	rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false);
859 	pdev->dev.irq_start = rle->start;
860 	pdev->dev.irq_end = rle->start + avail;
861 	pdev->irq = rle->start;
862 	pdev->msi_enabled = true;
863 	return (0);
864 }
865 
866 static inline int
867 pci_channel_offline(struct pci_dev *pdev)
868 {
869 
870 	return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID);
871 }
872 
873 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
874 {
875 	return -ENODEV;
876 }
877 
878 static inline void pci_disable_sriov(struct pci_dev *dev)
879 {
880 }
881 
882 static inline void *
883 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size)
884 {
885 	struct resource *res;
886 
887 	res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size);
888 	if (res == NULL)
889 		return (NULL);
890 	/* This is a FreeBSD extension so we can use bus_*(). */
891 	if (pdev->want_iomap_res)
892 		return (res);
893 	return ((void *)rman_get_bushandle(res));
894 }
895 
896 static inline void
897 pci_iounmap(struct pci_dev *pdev, void *res)
898 {
899 	struct pci_mmio_region *mmio, *p;
900 
901 	TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) {
902 		if (res != (void *)rman_get_bushandle(mmio->res))
903 			continue;
904 		bus_release_resource(pdev->dev.bsddev,
905 		    mmio->type, mmio->rid, mmio->res);
906 		TAILQ_REMOVE(&pdev->mmio, mmio, next);
907 		free(mmio, M_DEVBUF);
908 		return;
909 	}
910 }
911 
912 static inline void
913 lkpi_pci_save_state(struct pci_dev *pdev)
914 {
915 
916 	pci_save_state(pdev->dev.bsddev);
917 }
918 
919 static inline void
920 lkpi_pci_restore_state(struct pci_dev *pdev)
921 {
922 
923 	pci_restore_state(pdev->dev.bsddev);
924 }
925 
926 #define pci_save_state(dev)	lkpi_pci_save_state(dev)
927 #define pci_restore_state(dev)	lkpi_pci_restore_state(dev)
928 
929 #define DEFINE_PCI_DEVICE_TABLE(_table) \
930 	const struct pci_device_id _table[] __devinitdata
931 
932 /* XXX This should not be necessary. */
933 #define	pcix_set_mmrbc(d, v)	0
934 #define	pcix_get_max_mmrbc(d)	0
935 #define	pcie_set_readrq(d, v)	pci_set_max_read_req((d)->dev.bsddev, (v))
936 
937 #define	PCI_DMA_BIDIRECTIONAL	0
938 #define	PCI_DMA_TODEVICE	1
939 #define	PCI_DMA_FROMDEVICE	2
940 #define	PCI_DMA_NONE		3
941 
942 #define	pci_pool		dma_pool
943 #define	pci_pool_destroy(...)	dma_pool_destroy(__VA_ARGS__)
944 #define	pci_pool_alloc(...)	dma_pool_alloc(__VA_ARGS__)
945 #define	pci_pool_free(...)	dma_pool_free(__VA_ARGS__)
946 #define	pci_pool_create(_name, _pdev, _size, _align, _alloc)		\
947 	    dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc)
948 #define	pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle)		\
949 	    dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev,	\
950 		_size, _vaddr, _dma_handle)
951 #define	pci_map_sg(_hwdev, _sg, _nents, _dir)				\
952 	    dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev),	\
953 		_sg, _nents, (enum dma_data_direction)_dir)
954 #define	pci_map_single(_hwdev, _ptr, _size, _dir)			\
955 	    dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev),	\
956 		(_ptr), (_size), (enum dma_data_direction)_dir)
957 #define	pci_unmap_single(_hwdev, _addr, _size, _dir)			\
958 	    dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev,	\
959 		_addr, _size, (enum dma_data_direction)_dir)
960 #define	pci_unmap_sg(_hwdev, _sg, _nents, _dir)				\
961 	    dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev,	\
962 		_sg, _nents, (enum dma_data_direction)_dir)
963 #define	pci_map_page(_hwdev, _page, _offset, _size, _dir)		\
964 	    dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\
965 		_offset, _size, (enum dma_data_direction)_dir)
966 #define	pci_unmap_page(_hwdev, _dma_address, _size, _dir)		\
967 	    dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev,	\
968 		_dma_address, _size, (enum dma_data_direction)_dir)
969 #define	pci_set_dma_mask(_pdev, mask)	dma_set_mask(&(_pdev)->dev, (mask))
970 #define	pci_dma_mapping_error(_pdev, _dma_addr)				\
971 	    dma_mapping_error(&(_pdev)->dev, _dma_addr)
972 #define	pci_set_consistent_dma_mask(_pdev, _mask)			\
973 	    dma_set_coherent_mask(&(_pdev)->dev, (_mask))
974 #define	DECLARE_PCI_UNMAP_ADDR(x)	DEFINE_DMA_UNMAP_ADDR(x);
975 #define	DECLARE_PCI_UNMAP_LEN(x)	DEFINE_DMA_UNMAP_LEN(x);
976 #define	pci_unmap_addr		dma_unmap_addr
977 #define	pci_unmap_addr_set	dma_unmap_addr_set
978 #define	pci_unmap_len		dma_unmap_len
979 #define	pci_unmap_len_set	dma_unmap_len_set
980 
981 typedef unsigned int __bitwise pci_channel_state_t;
982 typedef unsigned int __bitwise pci_ers_result_t;
983 
984 enum pci_channel_state {
985 	pci_channel_io_normal = 1,
986 	pci_channel_io_frozen = 2,
987 	pci_channel_io_perm_failure = 3,
988 };
989 
990 enum pci_ers_result {
991 	PCI_ERS_RESULT_NONE = 1,
992 	PCI_ERS_RESULT_CAN_RECOVER = 2,
993 	PCI_ERS_RESULT_NEED_RESET = 3,
994 	PCI_ERS_RESULT_DISCONNECT = 4,
995 	PCI_ERS_RESULT_RECOVERED = 5,
996 };
997 
998 /* PCI bus error event callbacks */
999 struct pci_error_handlers {
1000 	pci_ers_result_t (*error_detected)(struct pci_dev *dev,
1001 	    enum pci_channel_state error);
1002 	pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
1003 	pci_ers_result_t (*link_reset)(struct pci_dev *dev);
1004 	pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
1005 	void (*resume)(struct pci_dev *dev);
1006 };
1007 
1008 /* FreeBSD does not support SRIOV - yet */
1009 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
1010 {
1011 	return dev;
1012 }
1013 
1014 static inline bool pci_is_pcie(struct pci_dev *dev)
1015 {
1016 	return !!pci_pcie_cap(dev);
1017 }
1018 
1019 static inline u16 pcie_flags_reg(struct pci_dev *dev)
1020 {
1021 	int pos;
1022 	u16 reg16;
1023 
1024 	pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
1025 	if (!pos)
1026 		return 0;
1027 
1028 	pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &reg16);
1029 
1030 	return reg16;
1031 }
1032 
1033 static inline int pci_pcie_type(struct pci_dev *dev)
1034 {
1035 	return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1036 }
1037 
1038 static inline int pcie_cap_version(struct pci_dev *dev)
1039 {
1040 	return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS;
1041 }
1042 
1043 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev)
1044 {
1045 	int type = pci_pcie_type(dev);
1046 
1047 	return pcie_cap_version(dev) > 1 ||
1048 	       type == PCI_EXP_TYPE_ROOT_PORT ||
1049 	       type == PCI_EXP_TYPE_ENDPOINT ||
1050 	       type == PCI_EXP_TYPE_LEG_END;
1051 }
1052 
1053 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
1054 {
1055 		return true;
1056 }
1057 
1058 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev)
1059 {
1060 	int type = pci_pcie_type(dev);
1061 
1062 	return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
1063 	    (type == PCI_EXP_TYPE_DOWNSTREAM &&
1064 	    pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT);
1065 }
1066 
1067 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev)
1068 {
1069 	int type = pci_pcie_type(dev);
1070 
1071 	return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
1072 	    type == PCI_EXP_TYPE_RC_EC;
1073 }
1074 
1075 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
1076 {
1077 	if (!pci_is_pcie(dev))
1078 		return false;
1079 
1080 	switch (pos) {
1081 	case PCI_EXP_FLAGS_TYPE:
1082 		return true;
1083 	case PCI_EXP_DEVCAP:
1084 	case PCI_EXP_DEVCTL:
1085 	case PCI_EXP_DEVSTA:
1086 		return pcie_cap_has_devctl(dev);
1087 	case PCI_EXP_LNKCAP:
1088 	case PCI_EXP_LNKCTL:
1089 	case PCI_EXP_LNKSTA:
1090 		return pcie_cap_has_lnkctl(dev);
1091 	case PCI_EXP_SLTCAP:
1092 	case PCI_EXP_SLTCTL:
1093 	case PCI_EXP_SLTSTA:
1094 		return pcie_cap_has_sltctl(dev);
1095 	case PCI_EXP_RTCTL:
1096 	case PCI_EXP_RTCAP:
1097 	case PCI_EXP_RTSTA:
1098 		return pcie_cap_has_rtctl(dev);
1099 	case PCI_EXP_DEVCAP2:
1100 	case PCI_EXP_DEVCTL2:
1101 	case PCI_EXP_LNKCAP2:
1102 	case PCI_EXP_LNKCTL2:
1103 	case PCI_EXP_LNKSTA2:
1104 		return pcie_cap_version(dev) > 1;
1105 	default:
1106 		return false;
1107 	}
1108 }
1109 
1110 static inline int
1111 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
1112 {
1113 	if (pos & 3)
1114 		return -EINVAL;
1115 
1116 	if (!pcie_capability_reg_implemented(dev, pos))
1117 		return -EINVAL;
1118 
1119 	return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
1120 }
1121 
1122 static inline int
1123 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
1124 {
1125 	if (pos & 3)
1126 		return -EINVAL;
1127 
1128 	if (!pcie_capability_reg_implemented(dev, pos))
1129 		return -EINVAL;
1130 
1131 	return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
1132 }
1133 
1134 static inline int
1135 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
1136 {
1137 	if (pos & 1)
1138 		return -EINVAL;
1139 
1140 	if (!pcie_capability_reg_implemented(dev, pos))
1141 		return 0;
1142 
1143 	return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
1144 }
1145 
1146 static inline int
1147 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val)
1148 {
1149 	int error;
1150 	uint16_t v;
1151 
1152 	error = pcie_capability_read_word(dev, pos, &v);
1153 	if (error != 0)
1154 		return (error);
1155 
1156 	v |= val;
1157 
1158 	error = pcie_capability_write_word(dev, pos, v);
1159 	return (error);
1160 }
1161 
1162 static inline int pcie_get_minimum_link(struct pci_dev *dev,
1163     enum pci_bus_speed *speed, enum pcie_link_width *width)
1164 {
1165 	*speed = PCI_SPEED_UNKNOWN;
1166 	*width = PCIE_LNK_WIDTH_UNKNOWN;
1167 	return (0);
1168 }
1169 
1170 static inline int
1171 pci_num_vf(struct pci_dev *dev)
1172 {
1173 	return (0);
1174 }
1175 
1176 static inline enum pci_bus_speed
1177 pcie_get_speed_cap(struct pci_dev *dev)
1178 {
1179 	device_t root;
1180 	uint32_t lnkcap, lnkcap2;
1181 	int error, pos;
1182 
1183 	root = device_get_parent(dev->dev.bsddev);
1184 	if (root == NULL)
1185 		return (PCI_SPEED_UNKNOWN);
1186 	root = device_get_parent(root);
1187 	if (root == NULL)
1188 		return (PCI_SPEED_UNKNOWN);
1189 	root = device_get_parent(root);
1190 	if (root == NULL)
1191 		return (PCI_SPEED_UNKNOWN);
1192 
1193 	if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA ||
1194 	    pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS)
1195 		return (PCI_SPEED_UNKNOWN);
1196 
1197 	if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0)
1198 		return (PCI_SPEED_UNKNOWN);
1199 
1200 	lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4);
1201 
1202 	if (lnkcap2) {	/* PCIe r3.0-compliant */
1203 		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
1204 			return (PCIE_SPEED_2_5GT);
1205 		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
1206 			return (PCIE_SPEED_5_0GT);
1207 		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
1208 			return (PCIE_SPEED_8_0GT);
1209 		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
1210 			return (PCIE_SPEED_16_0GT);
1211 	} else {	/* pre-r3.0 */
1212 		lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4);
1213 		if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
1214 			return (PCIE_SPEED_2_5GT);
1215 		if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
1216 			return (PCIE_SPEED_5_0GT);
1217 		if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
1218 			return (PCIE_SPEED_8_0GT);
1219 		if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
1220 			return (PCIE_SPEED_16_0GT);
1221 	}
1222 	return (PCI_SPEED_UNKNOWN);
1223 }
1224 
1225 static inline enum pcie_link_width
1226 pcie_get_width_cap(struct pci_dev *dev)
1227 {
1228 	uint32_t lnkcap;
1229 
1230 	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
1231 	if (lnkcap)
1232 		return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4);
1233 
1234 	return (PCIE_LNK_WIDTH_UNKNOWN);
1235 }
1236 
1237 static inline int
1238 pcie_get_mps(struct pci_dev *dev)
1239 {
1240 	return (pci_get_max_payload(dev->dev.bsddev));
1241 }
1242 
1243 static inline uint32_t
1244 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)
1245 {
1246 
1247 	switch(spd) {
1248 	case PCIE_SPEED_16_0GT:
1249 		return (16000 * 128 / 130);
1250 	case PCIE_SPEED_8_0GT:
1251 		return (8000 * 128 / 130);
1252 	case PCIE_SPEED_5_0GT:
1253 		return (5000 * 8 / 10);
1254 	case PCIE_SPEED_2_5GT:
1255 		return (2500 * 8 / 10);
1256 	default:
1257 		return (0);
1258 	}
1259 }
1260 
1261 static inline uint32_t
1262 pcie_bandwidth_available(struct pci_dev *pdev,
1263     struct pci_dev **limiting,
1264     enum pci_bus_speed *speed,
1265     enum pcie_link_width *width)
1266 {
1267 	enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev);
1268 	enum pcie_link_width nwidth = pcie_get_width_cap(pdev);
1269 
1270 	if (speed)
1271 		*speed = nspeed;
1272 	if (width)
1273 		*width = nwidth;
1274 
1275 	return (nwidth * PCIE_SPEED2MBS_ENC(nspeed));
1276 }
1277 
1278 static inline struct pci_dev *
1279 pcie_find_root_port(struct pci_dev *pdev)
1280 {
1281 	device_t root;
1282 
1283 	if (pdev->root != NULL)
1284 		return (pdev->root);
1285 
1286 	root = pci_find_pcie_root_port(pdev->dev.bsddev);
1287 	if (root == NULL)
1288 		return (NULL);
1289 
1290 	pdev->root = lkpinew_pci_dev(root);
1291 	return (pdev->root);
1292 }
1293 
1294 /* This is needed when people rip out the device "HotPlug". */
1295 static inline void
1296 pci_lock_rescan_remove(void)
1297 {
1298 }
1299 
1300 static inline void
1301 pci_unlock_rescan_remove(void)
1302 {
1303 }
1304 
1305 static __inline void
1306 pci_stop_and_remove_bus_device(struct pci_dev *pdev)
1307 {
1308 }
1309 
1310 /*
1311  * The following functions can be used to attach/detach the LinuxKPI's
1312  * PCI device runtime. The pci_driver and pci_device_id pointer is
1313  * allowed to be NULL. Other pointers must be all valid.
1314  * The pci_dev structure should be zero-initialized before passed
1315  * to the linux_pci_attach_device function.
1316  */
1317 extern int linux_pci_attach_device(device_t, struct pci_driver *,
1318     const struct pci_device_id *, struct pci_dev *);
1319 extern int linux_pci_detach_device(struct pci_dev *);
1320 
1321 static inline int
1322 pci_dev_present(const struct pci_device_id *cur)
1323 {
1324 	while (cur != NULL && (cur->vendor || cur->device)) {
1325 		if (pci_find_device(cur->vendor, cur->device) != NULL) {
1326 			return (1);
1327 		}
1328 		cur++;
1329 	}
1330 	return (0);
1331 }
1332 
1333 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain,
1334     unsigned int bus, unsigned int devfn);
1335 #define	pci_get_domain_bus_and_slot(domain, bus, devfn)	\
1336 	lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn)
1337 
1338 static inline int
1339 pci_domain_nr(struct pci_bus *pbus)
1340 {
1341 
1342 	return (pbus->domain);
1343 }
1344 
1345 static inline int
1346 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn,
1347                     int pos, uint32_t *val, int len)
1348 {
1349 
1350 	*val = pci_read_config(bus->self->dev.bsddev, pos, len);
1351 	return (0);
1352 }
1353 
1354 static inline int
1355 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val)
1356 {
1357 	uint32_t tmp;
1358 	int ret;
1359 
1360 	ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2);
1361 	*val = (u16)tmp;
1362 	return (ret);
1363 }
1364 
1365 static inline int
1366 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val)
1367 {
1368 	uint32_t tmp;
1369 	int ret;
1370 
1371 	ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1);
1372 	*val = (u8)tmp;
1373 	return (ret);
1374 }
1375 
1376 static inline int
1377 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos,
1378     uint32_t val, int size)
1379 {
1380 
1381 	pci_write_config(bus->self->dev.bsddev, pos, val, size);
1382 	return (0);
1383 }
1384 
1385 static inline int
1386 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos,
1387     uint8_t val)
1388 {
1389 	return (pci_bus_write_config(bus, devfn, pos, val, 1));
1390 }
1391 
1392 static inline int
1393 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos,
1394     uint16_t val)
1395 {
1396 	return (pci_bus_write_config(bus, devfn, pos, val, 2));
1397 }
1398 
1399 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from);
1400 #define	pci_get_class(class, from)	lkpi_pci_get_class(class, from)
1401 
1402 /* -------------------------------------------------------------------------- */
1403 
1404 static inline int
1405 pcim_enable_device(struct pci_dev *pdev)
1406 {
1407 	struct pci_devres *dr;
1408 	int error;
1409 
1410 	/* Here we cannot run through the pdev->managed check. */
1411 	dr = lkpi_pci_devres_get_alloc(pdev);
1412 	if (dr == NULL)
1413 		return (-ENOMEM);
1414 
1415 	/* If resources were enabled before do not do it again. */
1416 	if (dr->enable_io)
1417 		return (0);
1418 
1419 	error = pci_enable_device(pdev);
1420 	if (error == 0)
1421 		dr->enable_io = true;
1422 
1423 	/* This device is not managed. */
1424 	pdev->managed = true;
1425 
1426 	return (error);
1427 }
1428 
1429 static inline void __iomem **
1430 pcim_iomap_table(struct pci_dev *pdev)
1431 {
1432 	struct pcim_iomap_devres *dr;
1433 
1434 	dr = lkpi_pcim_iomap_devres_find(pdev);
1435 	if (dr == NULL)
1436 		return (NULL);
1437 
1438 	/*
1439 	 * If the driver has manually set a flag to be able to request the
1440 	 * resource to use bus_read/write_<n>, return the shadow table.
1441 	 */
1442 	if (pdev->want_iomap_res)
1443 		return ((void **)dr->res_table);
1444 
1445 	/* This is the Linux default. */
1446 	return (dr->mmio_table);
1447 }
1448 
1449 static inline int
1450 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name)
1451 {
1452 	struct pcim_iomap_devres *dr;
1453 	void *res;
1454 	uint32_t mappings, requests, req_mask;
1455 	int bar, error;
1456 
1457 	dr = lkpi_pcim_iomap_devres_find(pdev);
1458 	if (dr == NULL)
1459 		return (-ENOMEM);
1460 
1461 	/* Request all the BARs ("regions") we do not iomap. */
1462 	req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask;
1463 	for (bar = requests = 0; requests != req_mask; bar++) {
1464 		if ((req_mask & (1 << bar)) == 0)
1465 			continue;
1466 		error = pci_request_region(pdev, bar, name);
1467 		if (error != 0 && error != -ENODEV)
1468 			goto err;
1469 		requests |= (1 << bar);
1470 	}
1471 
1472 	/* Now iomap all the requested (by "mask") ones. */
1473 	for (bar = mappings = 0; mappings != mask; bar++) {
1474 		if ((mask & (1 << bar)) == 0)
1475 			continue;
1476 
1477 		/* Request double is not allowed. */
1478 		if (dr->mmio_table[bar] != NULL) {
1479 			device_printf(pdev->dev.bsddev, "%s: bar %d %p\n",
1480 			     __func__, bar, dr->mmio_table[bar]);
1481 			goto err;
1482 		}
1483 
1484 		res = _lkpi_pci_iomap(pdev, bar, 0);
1485 		if (res == NULL)
1486 			goto err;
1487 		dr->mmio_table[bar] = (void *)rman_get_bushandle(res);
1488 		dr->res_table[bar] = res;
1489 
1490 		mappings |= (1 << bar);
1491 	}
1492 
1493 	return (0);
1494 
1495 err:
1496 	for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) {
1497 		if ((mappings & (1 << bar)) != 0) {
1498 			res = dr->mmio_table[bar];
1499 			if (res == NULL)
1500 				continue;
1501 			pci_iounmap(pdev, res);
1502 		} else if ((requests & (1 << bar)) != 0) {
1503 			pci_release_region(pdev, bar);
1504 		}
1505 	}
1506 
1507 	return (-EINVAL);
1508 }
1509 
1510 /* This is a FreeBSD extension so we can use bus_*(). */
1511 static inline void
1512 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev)
1513 {
1514 	pdev->want_iomap_res = true;
1515 }
1516 
1517 #endif	/* _LINUXKPI_LINUX_PCI_H_ */
1518