1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/pciio.h> 41 #include <sys/rman.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pci_private.h> 45 46 #include <machine/resource.h> 47 48 #include <linux/list.h> 49 #include <linux/dmapool.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/compiler.h> 52 #include <linux/errno.h> 53 #include <asm/atomic.h> 54 #include <linux/device.h> 55 56 struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class_mask; 62 uintptr_t driver_data; 63 }; 64 65 #define MODULE_DEVICE_TABLE(bus, table) 66 #define PCI_ANY_ID (-1) 67 #define PCI_VENDOR_ID_APPLE 0x106b 68 #define PCI_VENDOR_ID_ASUSTEK 0x1043 69 #define PCI_VENDOR_ID_ATI 0x1002 70 #define PCI_VENDOR_ID_DELL 0x1028 71 #define PCI_VENDOR_ID_HP 0x103c 72 #define PCI_VENDOR_ID_IBM 0x1014 73 #define PCI_VENDOR_ID_INTEL 0x8086 74 #define PCI_VENDOR_ID_MELLANOX 0x15b3 75 #define PCI_VENDOR_ID_SERVERWORKS 0x1166 76 #define PCI_VENDOR_ID_SONY 0x104d 77 #define PCI_VENDOR_ID_TOPSPIN 0x1867 78 #define PCI_VENDOR_ID_VIA 0x1106 79 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 80 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 81 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 82 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 83 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 84 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 85 86 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 87 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 88 #define PCI_FUNC(devfn) ((devfn) & 0x07) 89 90 #define PCI_VDEVICE(_vendor, _device) \ 91 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 92 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 93 #define PCI_DEVICE(_vendor, _device) \ 94 .vendor = (_vendor), .device = (_device), \ 95 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 96 97 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 98 99 #define PCI_VENDOR_ID PCIR_DEVVENDOR 100 #define PCI_COMMAND PCIR_COMMAND 101 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 102 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 103 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 104 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 105 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 106 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 107 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 108 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 109 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 110 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 111 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 112 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 113 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 114 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 115 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 116 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 117 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 118 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 119 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 120 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 121 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 122 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 123 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 124 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 125 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 126 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 127 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 128 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 129 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 130 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 131 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 132 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 133 134 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 135 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 136 #define PCI_EXP_DEVSTA_TRPND 0x0020 137 138 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 139 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 140 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 141 142 enum pci_bus_speed { 143 PCI_SPEED_UNKNOWN = -1, 144 PCIE_SPEED_2_5GT, 145 PCIE_SPEED_5_0GT, 146 PCIE_SPEED_8_0GT, 147 }; 148 149 enum pcie_link_width { 150 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 151 }; 152 153 typedef int pci_power_t; 154 155 #define PCI_D0 PCI_POWERSTATE_D0 156 #define PCI_D1 PCI_POWERSTATE_D1 157 #define PCI_D2 PCI_POWERSTATE_D2 158 #define PCI_D3hot PCI_POWERSTATE_D3 159 #define PCI_D3cold 4 160 161 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 162 163 struct pci_dev; 164 165 struct pci_driver { 166 struct list_head links; 167 char *name; 168 const struct pci_device_id *id_table; 169 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 170 void (*remove)(struct pci_dev *dev); 171 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 172 int (*resume) (struct pci_dev *dev); /* Device woken up */ 173 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 174 driver_t driver; 175 devclass_t bsdclass; 176 const struct pci_error_handlers *err_handler; 177 }; 178 179 extern struct list_head pci_drivers; 180 extern struct list_head pci_devices; 181 extern spinlock_t pci_lock; 182 183 #define __devexit_p(x) x 184 185 struct pci_dev { 186 struct device dev; 187 struct list_head links; 188 struct pci_driver *pdrv; 189 uint64_t dma_mask; 190 uint16_t device; 191 uint16_t vendor; 192 unsigned int irq; 193 unsigned int devfn; 194 u8 revision; 195 }; 196 197 static inline struct resource_list_entry * 198 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 199 { 200 struct pci_devinfo *dinfo; 201 struct resource_list *rl; 202 203 dinfo = device_get_ivars(pdev->dev.bsddev); 204 rl = &dinfo->resources; 205 return resource_list_find(rl, type, rid); 206 } 207 208 static inline struct resource_list_entry * 209 linux_pci_get_bar(struct pci_dev *pdev, int bar) 210 { 211 struct resource_list_entry *rle; 212 213 bar = PCIR_BAR(bar); 214 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 215 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 216 return (rle); 217 } 218 219 static inline struct device * 220 linux_pci_find_irq_dev(unsigned int irq) 221 { 222 struct pci_dev *pdev; 223 224 spin_lock(&pci_lock); 225 list_for_each_entry(pdev, &pci_devices, links) { 226 if (irq == pdev->dev.irq) 227 break; 228 if (irq >= pdev->dev.msix && irq < pdev->dev.msix_max) 229 break; 230 } 231 spin_unlock(&pci_lock); 232 if (pdev) 233 return &pdev->dev; 234 return (NULL); 235 } 236 237 static inline unsigned long 238 pci_resource_start(struct pci_dev *pdev, int bar) 239 { 240 struct resource_list_entry *rle; 241 242 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 243 return (0); 244 return rle->start; 245 } 246 247 static inline unsigned long 248 pci_resource_len(struct pci_dev *pdev, int bar) 249 { 250 struct resource_list_entry *rle; 251 252 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 253 return (0); 254 return rle->count; 255 } 256 257 static inline int 258 pci_resource_type(struct pci_dev *pdev, int bar) 259 { 260 struct pci_map *pm; 261 262 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 263 if (!pm) 264 return (-1); 265 266 if (PCI_BAR_IO(pm->pm_value)) 267 return (SYS_RES_IOPORT); 268 else 269 return (SYS_RES_MEMORY); 270 } 271 272 /* 273 * All drivers just seem to want to inspect the type not flags. 274 */ 275 static inline int 276 pci_resource_flags(struct pci_dev *pdev, int bar) 277 { 278 int type; 279 280 type = pci_resource_type(pdev, bar); 281 if (type < 0) 282 return (0); 283 return (1 << type); 284 } 285 286 static inline const char * 287 pci_name(struct pci_dev *d) 288 { 289 290 return device_get_desc(d->dev.bsddev); 291 } 292 293 static inline void * 294 pci_get_drvdata(struct pci_dev *pdev) 295 { 296 297 return dev_get_drvdata(&pdev->dev); 298 } 299 300 static inline void 301 pci_set_drvdata(struct pci_dev *pdev, void *data) 302 { 303 304 dev_set_drvdata(&pdev->dev, data); 305 } 306 307 static inline int 308 pci_enable_device(struct pci_dev *pdev) 309 { 310 311 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 312 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 313 return (0); 314 } 315 316 static inline void 317 pci_disable_device(struct pci_dev *pdev) 318 { 319 } 320 321 static inline int 322 pci_set_master(struct pci_dev *pdev) 323 { 324 325 pci_enable_busmaster(pdev->dev.bsddev); 326 return (0); 327 } 328 329 static inline int 330 pci_set_power_state(struct pci_dev *pdev, int state) 331 { 332 333 pci_set_powerstate(pdev->dev.bsddev, state); 334 return (0); 335 } 336 337 static inline int 338 pci_clear_master(struct pci_dev *pdev) 339 { 340 341 pci_disable_busmaster(pdev->dev.bsddev); 342 return (0); 343 } 344 345 static inline int 346 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 347 { 348 int rid; 349 int type; 350 351 type = pci_resource_type(pdev, bar); 352 if (type < 0) 353 return (-ENODEV); 354 rid = PCIR_BAR(bar); 355 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 356 RF_ACTIVE) == NULL) 357 return (-EINVAL); 358 return (0); 359 } 360 361 static inline void 362 pci_release_region(struct pci_dev *pdev, int bar) 363 { 364 struct resource_list_entry *rle; 365 366 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 367 return; 368 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 369 } 370 371 static inline void 372 pci_release_regions(struct pci_dev *pdev) 373 { 374 int i; 375 376 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 377 pci_release_region(pdev, i); 378 } 379 380 static inline int 381 pci_request_regions(struct pci_dev *pdev, const char *res_name) 382 { 383 int error; 384 int i; 385 386 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 387 error = pci_request_region(pdev, i, res_name); 388 if (error && error != -ENODEV) { 389 pci_release_regions(pdev); 390 return (error); 391 } 392 } 393 return (0); 394 } 395 396 static inline void 397 pci_disable_msix(struct pci_dev *pdev) 398 { 399 400 pci_release_msi(pdev->dev.bsddev); 401 } 402 403 static inline bus_addr_t 404 pci_bus_address(struct pci_dev *pdev, int bar) 405 { 406 407 return (pci_resource_start(pdev, bar)); 408 } 409 410 #define PCI_CAP_ID_EXP PCIY_EXPRESS 411 #define PCI_CAP_ID_PCIX PCIY_PCIX 412 #define PCI_CAP_ID_AGP PCIY_AGP 413 #define PCI_CAP_ID_PM PCIY_PMG 414 415 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 416 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 417 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 418 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 419 #define PCI_EXP_LNKSTA PCIER_LINK_STA 420 421 static inline int 422 pci_find_capability(struct pci_dev *pdev, int capid) 423 { 424 int reg; 425 426 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 427 return (0); 428 return (reg); 429 } 430 431 static inline int pci_pcie_cap(struct pci_dev *dev) 432 { 433 return pci_find_capability(dev, PCI_CAP_ID_EXP); 434 } 435 436 437 static inline int 438 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 439 { 440 441 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 442 return (0); 443 } 444 445 static inline int 446 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 447 { 448 449 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 450 return (0); 451 } 452 453 static inline int 454 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 455 { 456 457 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 458 return (0); 459 } 460 461 static inline int 462 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 463 { 464 465 pci_write_config(pdev->dev.bsddev, where, val, 1); 466 return (0); 467 } 468 469 static inline int 470 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 471 { 472 473 pci_write_config(pdev->dev.bsddev, where, val, 2); 474 return (0); 475 } 476 477 static inline int 478 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 479 { 480 481 pci_write_config(pdev->dev.bsddev, where, val, 4); 482 return (0); 483 } 484 485 extern int pci_register_driver(struct pci_driver *pdrv); 486 extern void pci_unregister_driver(struct pci_driver *pdrv); 487 488 struct msix_entry { 489 int entry; 490 int vector; 491 }; 492 493 /* 494 * Enable msix, positive errors indicate actual number of available 495 * vectors. Negative errors are failures. 496 * 497 * NB: define added to prevent this definition of pci_enable_msix from 498 * clashing with the native FreeBSD version. 499 */ 500 #define pci_enable_msix linux_pci_enable_msix 501 static inline int 502 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 503 { 504 struct resource_list_entry *rle; 505 int error; 506 int avail; 507 int i; 508 509 avail = pci_msix_count(pdev->dev.bsddev); 510 if (avail < nreq) { 511 if (avail == 0) 512 return -EINVAL; 513 return avail; 514 } 515 avail = nreq; 516 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 517 return error; 518 /* 519 * Handle case where "pci_alloc_msix()" may allocate less 520 * interrupts than available and return with no error: 521 */ 522 if (avail < nreq) { 523 pci_release_msi(pdev->dev.bsddev); 524 return avail; 525 } 526 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 527 pdev->dev.msix = rle->start; 528 pdev->dev.msix_max = rle->start + avail; 529 for (i = 0; i < nreq; i++) 530 entries[i].vector = pdev->dev.msix + i; 531 return (0); 532 } 533 534 #define pci_enable_msix_range linux_pci_enable_msix_range 535 static inline int 536 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 537 int minvec, int maxvec) 538 { 539 int nvec = maxvec; 540 int rc; 541 542 if (maxvec < minvec) 543 return (-ERANGE); 544 545 do { 546 rc = pci_enable_msix(dev, entries, nvec); 547 if (rc < 0) { 548 return (rc); 549 } else if (rc > 0) { 550 if (rc < minvec) 551 return (-ENOSPC); 552 nvec = rc; 553 } 554 } while (rc); 555 return (nvec); 556 } 557 558 static inline int pci_channel_offline(struct pci_dev *pdev) 559 { 560 return false; 561 } 562 563 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 564 { 565 return -ENODEV; 566 } 567 static inline void pci_disable_sriov(struct pci_dev *dev) 568 { 569 } 570 571 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 572 const struct pci_device_id _table[] __devinitdata 573 574 575 /* XXX This should not be necessary. */ 576 #define pcix_set_mmrbc(d, v) 0 577 #define pcix_get_max_mmrbc(d) 0 578 #define pcie_set_readrq(d, v) 0 579 580 #define PCI_DMA_BIDIRECTIONAL 0 581 #define PCI_DMA_TODEVICE 1 582 #define PCI_DMA_FROMDEVICE 2 583 #define PCI_DMA_NONE 3 584 585 #define pci_pool dma_pool 586 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 587 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 588 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 589 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 590 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 591 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 592 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 593 _size, _vaddr, _dma_handle) 594 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 595 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 596 _sg, _nents, (enum dma_data_direction)_dir) 597 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 598 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 599 (_ptr), (_size), (enum dma_data_direction)_dir) 600 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 601 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 602 _addr, _size, (enum dma_data_direction)_dir) 603 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 604 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 605 _sg, _nents, (enum dma_data_direction)_dir) 606 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 607 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 608 _offset, _size, (enum dma_data_direction)_dir) 609 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 610 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 611 _dma_address, _size, (enum dma_data_direction)_dir) 612 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 613 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 614 dma_mapping_error(&(_pdev)->dev, _dma_addr) 615 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 616 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 617 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 618 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 619 #define pci_unmap_addr dma_unmap_addr 620 #define pci_unmap_addr_set dma_unmap_addr_set 621 #define pci_unmap_len dma_unmap_len 622 #define pci_unmap_len_set dma_unmap_len_set 623 624 typedef unsigned int __bitwise pci_channel_state_t; 625 typedef unsigned int __bitwise pci_ers_result_t; 626 627 enum pci_channel_state { 628 pci_channel_io_normal = 1, 629 pci_channel_io_frozen = 2, 630 pci_channel_io_perm_failure = 3, 631 }; 632 633 enum pci_ers_result { 634 PCI_ERS_RESULT_NONE = 1, 635 PCI_ERS_RESULT_CAN_RECOVER = 2, 636 PCI_ERS_RESULT_NEED_RESET = 3, 637 PCI_ERS_RESULT_DISCONNECT = 4, 638 PCI_ERS_RESULT_RECOVERED = 5, 639 }; 640 641 642 /* PCI bus error event callbacks */ 643 struct pci_error_handlers { 644 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 645 enum pci_channel_state error); 646 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 647 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 648 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 649 void (*resume)(struct pci_dev *dev); 650 }; 651 652 /* FreeBSD does not support SRIOV - yet */ 653 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 654 { 655 return dev; 656 } 657 658 static inline bool pci_is_pcie(struct pci_dev *dev) 659 { 660 return !!pci_pcie_cap(dev); 661 } 662 663 static inline u16 pcie_flags_reg(struct pci_dev *dev) 664 { 665 int pos; 666 u16 reg16; 667 668 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 669 if (!pos) 670 return 0; 671 672 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 673 674 return reg16; 675 } 676 677 678 static inline int pci_pcie_type(struct pci_dev *dev) 679 { 680 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 681 } 682 683 static inline int pcie_cap_version(struct pci_dev *dev) 684 { 685 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 686 } 687 688 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 689 { 690 int type = pci_pcie_type(dev); 691 692 return pcie_cap_version(dev) > 1 || 693 type == PCI_EXP_TYPE_ROOT_PORT || 694 type == PCI_EXP_TYPE_ENDPOINT || 695 type == PCI_EXP_TYPE_LEG_END; 696 } 697 698 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 699 { 700 return true; 701 } 702 703 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 704 { 705 int type = pci_pcie_type(dev); 706 707 return pcie_cap_version(dev) > 1 || 708 type == PCI_EXP_TYPE_ROOT_PORT || 709 (type == PCI_EXP_TYPE_DOWNSTREAM && 710 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 711 } 712 713 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 714 { 715 int type = pci_pcie_type(dev); 716 717 return pcie_cap_version(dev) > 1 || 718 type == PCI_EXP_TYPE_ROOT_PORT || 719 type == PCI_EXP_TYPE_RC_EC; 720 } 721 722 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 723 { 724 if (!pci_is_pcie(dev)) 725 return false; 726 727 switch (pos) { 728 case PCI_EXP_FLAGS_TYPE: 729 return true; 730 case PCI_EXP_DEVCAP: 731 case PCI_EXP_DEVCTL: 732 case PCI_EXP_DEVSTA: 733 return pcie_cap_has_devctl(dev); 734 case PCI_EXP_LNKCAP: 735 case PCI_EXP_LNKCTL: 736 case PCI_EXP_LNKSTA: 737 return pcie_cap_has_lnkctl(dev); 738 case PCI_EXP_SLTCAP: 739 case PCI_EXP_SLTCTL: 740 case PCI_EXP_SLTSTA: 741 return pcie_cap_has_sltctl(dev); 742 case PCI_EXP_RTCTL: 743 case PCI_EXP_RTCAP: 744 case PCI_EXP_RTSTA: 745 return pcie_cap_has_rtctl(dev); 746 case PCI_EXP_DEVCAP2: 747 case PCI_EXP_DEVCTL2: 748 case PCI_EXP_LNKCAP2: 749 case PCI_EXP_LNKCTL2: 750 case PCI_EXP_LNKSTA2: 751 return pcie_cap_version(dev) > 1; 752 default: 753 return false; 754 } 755 } 756 757 static inline int 758 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 759 { 760 if (pos & 3) 761 return -EINVAL; 762 763 if (!pcie_capability_reg_implemented(dev, pos)) 764 return -EINVAL; 765 766 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 767 } 768 769 static inline int 770 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 771 { 772 if (pos & 3) 773 return -EINVAL; 774 775 if (!pcie_capability_reg_implemented(dev, pos)) 776 return -EINVAL; 777 778 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 779 } 780 781 static inline int 782 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 783 { 784 if (pos & 1) 785 return -EINVAL; 786 787 if (!pcie_capability_reg_implemented(dev, pos)) 788 return 0; 789 790 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 791 } 792 793 static inline int pcie_get_minimum_link(struct pci_dev *dev, 794 enum pci_bus_speed *speed, enum pcie_link_width *width) 795 { 796 *speed = PCI_SPEED_UNKNOWN; 797 *width = PCIE_LNK_WIDTH_UNKNOWN; 798 return (0); 799 } 800 801 static inline int 802 pci_num_vf(struct pci_dev *dev) 803 { 804 return (0); 805 } 806 807 #endif /* _LINUX_PCI_H_ */ 808