1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/nv.h> 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <asm/memtype.h> 61 #include <linux/device.h> 62 #include <linux/pci_ids.h> 63 #include <linux/pm.h> 64 65 struct pci_device_id { 66 uint32_t vendor; 67 uint32_t device; 68 uint32_t subvendor; 69 uint32_t subdevice; 70 uint32_t class; 71 uint32_t class_mask; 72 uintptr_t driver_data; 73 }; 74 75 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 76 #define MODULE_DEVICE_TABLE(_bus, _table) \ 77 \ 78 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 79 DEVMETHOD_END \ 80 }; \ 81 \ 82 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 83 "lkpi_" #_bus #_table, \ 84 _ ## _bus ## _ ## _table ## _methods, \ 85 0 \ 86 }; \ 87 \ 88 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 89 0, 0); \ 90 \ 91 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 92 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 93 94 #define PCI_ANY_ID -1U 95 96 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 97 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 98 #define PCI_FUNC(devfn) ((devfn) & 0x07) 99 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 100 101 #define PCI_VDEVICE(_vendor, _device) \ 102 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 103 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 104 #define PCI_DEVICE(_vendor, _device) \ 105 .vendor = (_vendor), .device = (_device), \ 106 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 107 108 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 109 110 #define PCI_STD_NUM_BARS 6 111 #define PCI_VENDOR_ID PCIR_VENDOR 112 #define PCI_DEVICE_ID PCIR_DEVICE 113 #define PCI_COMMAND PCIR_COMMAND 114 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 115 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 116 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 117 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 118 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 119 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 120 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 121 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 122 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 123 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 124 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 125 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 126 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 127 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 128 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 129 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 130 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 131 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 132 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 133 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 134 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 135 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 136 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 137 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 138 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 139 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 140 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 141 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 142 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 143 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 144 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 145 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 146 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 147 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 148 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 149 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 150 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 151 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 152 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 153 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 154 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 155 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 156 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 157 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 158 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 159 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 160 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 161 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 162 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 163 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 164 #define PCI_EXP_LNKCTL2_TLS 0x000f 165 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 166 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 167 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 168 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 169 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 170 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 171 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 172 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 173 174 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 175 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 176 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 177 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 178 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 179 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 180 181 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 182 #define PCI_EXP_DEVSTA_TRPND 0x0020 183 184 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 185 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 186 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 187 188 enum pci_bus_speed { 189 PCI_SPEED_UNKNOWN = -1, 190 PCIE_SPEED_2_5GT, 191 PCIE_SPEED_5_0GT, 192 PCIE_SPEED_8_0GT, 193 PCIE_SPEED_16_0GT, 194 PCIE_SPEED_32_0GT, 195 PCIE_SPEED_64_0GT, 196 }; 197 198 enum pcie_link_width { 199 PCIE_LNK_WIDTH_RESRV = 0x00, 200 PCIE_LNK_X1 = 0x01, 201 PCIE_LNK_X2 = 0x02, 202 PCIE_LNK_X4 = 0x04, 203 PCIE_LNK_X8 = 0x08, 204 PCIE_LNK_X12 = 0x0c, 205 PCIE_LNK_X16 = 0x10, 206 PCIE_LNK_X32 = 0x20, 207 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 208 }; 209 210 #define PCIE_LINK_STATE_L0S 0x00000001 211 #define PCIE_LINK_STATE_L1 0x00000002 212 #define PCIE_LINK_STATE_CLKPM 0x00000004 213 214 typedef int pci_power_t; 215 216 #define PCI_D0 PCI_POWERSTATE_D0 217 #define PCI_D1 PCI_POWERSTATE_D1 218 #define PCI_D2 PCI_POWERSTATE_D2 219 #define PCI_D3hot PCI_POWERSTATE_D3 220 #define PCI_D3cold 4 221 222 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 223 224 extern const char *pci_power_names[6]; 225 226 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 227 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 228 229 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 230 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 231 232 #define PCI_L1SS_CTL1 0x8 233 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 234 235 #define PCI_IRQ_LEGACY 0x01 236 #define PCI_IRQ_MSI 0x02 237 #define PCI_IRQ_MSIX 0x04 238 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 239 240 struct pci_dev; 241 242 struct pci_driver { 243 struct list_head node; 244 char *name; 245 const struct pci_device_id *id_table; 246 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 247 void (*remove)(struct pci_dev *dev); 248 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 249 int (*resume) (struct pci_dev *dev); /* Device woken up */ 250 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 251 driver_t bsddriver; 252 devclass_t bsdclass; 253 struct device_driver driver; 254 const struct pci_error_handlers *err_handler; 255 bool isdrm; 256 int bsd_probe_return; 257 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 258 const nvlist_t *pf_config); 259 void (*bsd_iov_uninit)(device_t dev); 260 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 261 const nvlist_t *vf_config); 262 }; 263 264 struct pci_bus { 265 struct pci_dev *self; 266 /* struct pci_bus *parent */ 267 int domain; 268 int number; 269 }; 270 271 extern struct list_head pci_drivers; 272 extern struct list_head pci_devices; 273 extern spinlock_t pci_lock; 274 275 #define __devexit_p(x) x 276 277 #define module_pci_driver(_driver) \ 278 \ 279 static inline int \ 280 _pci_init(void) \ 281 { \ 282 \ 283 return (linux_pci_register_driver(&_driver)); \ 284 } \ 285 \ 286 static inline void \ 287 _pci_exit(void) \ 288 { \ 289 \ 290 linux_pci_unregister_driver(&_driver); \ 291 } \ 292 \ 293 module_init(_pci_init); \ 294 module_exit(_pci_exit) 295 296 struct msi_msg { 297 uint32_t data; 298 }; 299 300 struct pci_msi_desc { 301 struct { 302 bool is_64; 303 } msi_attrib; 304 }; 305 306 struct msi_desc { 307 struct msi_msg msg; 308 struct pci_msi_desc pci; 309 }; 310 311 /* 312 * If we find drivers accessing this from multiple KPIs we may have to 313 * refcount objects of this structure. 314 */ 315 struct pci_mmio_region { 316 TAILQ_ENTRY(pci_mmio_region) next; 317 struct resource *res; 318 int rid; 319 int type; 320 }; 321 322 struct pci_dev { 323 struct device dev; 324 struct list_head links; 325 struct pci_driver *pdrv; 326 struct pci_bus *bus; 327 struct pci_dev *root; 328 pci_power_t current_state; 329 uint16_t device; 330 uint16_t vendor; 331 uint16_t subsystem_vendor; 332 uint16_t subsystem_device; 333 unsigned int irq; 334 unsigned int devfn; 335 uint32_t class; 336 uint8_t revision; 337 uint8_t msi_cap; 338 uint8_t msix_cap; 339 bool managed; /* devres "pcim_*(). */ 340 bool want_iomap_res; 341 bool msi_enabled; 342 bool msix_enabled; 343 phys_addr_t rom; 344 size_t romlen; 345 struct msi_desc **msi_desc; 346 char *path_name; 347 348 TAILQ_HEAD(, pci_mmio_region) mmio; 349 }; 350 351 /* We need some meta-struct to keep track of these for devres. */ 352 struct pci_devres { 353 bool enable_io; 354 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 355 uint8_t region_mask; 356 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 357 }; 358 struct pcim_iomap_devres { 359 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 360 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 361 }; 362 363 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 364 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 365 unsigned int flags); 366 bool pci_device_is_present(struct pci_dev *pdev); 367 368 /* Internal helper function(s). */ 369 struct pci_dev *lkpinew_pci_dev(device_t); 370 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev); 371 void lkpi_pci_devres_release(struct device *, void *); 372 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size); 373 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev); 374 void lkpi_pcim_iomap_table_release(struct device *, void *); 375 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 376 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 377 378 static inline bool 379 dev_is_pci(struct device *dev) 380 { 381 382 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 383 } 384 385 static inline int 386 pci_resource_type(struct pci_dev *pdev, int bar) 387 { 388 struct pci_map *pm; 389 390 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 391 if (!pm) 392 return (-1); 393 394 if (PCI_BAR_IO(pm->pm_value)) 395 return (SYS_RES_IOPORT); 396 else 397 return (SYS_RES_MEMORY); 398 } 399 400 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 401 struct resource_list *rl, int type, int rid); 402 403 static inline struct resource_list_entry * 404 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 405 { 406 struct pci_devinfo *dinfo; 407 struct resource_list *rl; 408 struct resource_list_entry *rle; 409 410 dinfo = device_get_ivars(pdev->dev.bsddev); 411 rl = &dinfo->resources; 412 rle = resource_list_find(rl, type, rid); 413 /* Reserve resources for this BAR if needed. */ 414 if (rle == NULL && reserve_bar) 415 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 416 return (rle); 417 } 418 419 static inline struct resource_list_entry * 420 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 421 { 422 int type; 423 424 type = pci_resource_type(pdev, bar); 425 if (type < 0) 426 return (NULL); 427 bar = PCIR_BAR(bar); 428 return (linux_pci_get_rle(pdev, type, bar, reserve)); 429 } 430 431 static inline struct device * 432 linux_pci_find_irq_dev(unsigned int irq) 433 { 434 struct pci_dev *pdev; 435 struct device *found; 436 437 found = NULL; 438 spin_lock(&pci_lock); 439 list_for_each_entry(pdev, &pci_devices, links) { 440 if (irq == pdev->dev.irq || 441 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 442 found = &pdev->dev; 443 break; 444 } 445 } 446 spin_unlock(&pci_lock); 447 return (found); 448 } 449 450 /* 451 * All drivers just seem to want to inspect the type not flags. 452 */ 453 static inline int 454 pci_resource_flags(struct pci_dev *pdev, int bar) 455 { 456 int type; 457 458 type = pci_resource_type(pdev, bar); 459 if (type < 0) 460 return (0); 461 return (1 << type); 462 } 463 464 static inline const char * 465 pci_name(struct pci_dev *d) 466 { 467 return d->path_name; 468 } 469 470 static inline void * 471 pci_get_drvdata(struct pci_dev *pdev) 472 { 473 474 return dev_get_drvdata(&pdev->dev); 475 } 476 477 static inline void 478 pci_set_drvdata(struct pci_dev *pdev, void *data) 479 { 480 481 dev_set_drvdata(&pdev->dev, data); 482 } 483 484 static inline struct pci_dev * 485 pci_dev_get(struct pci_dev *pdev) 486 { 487 488 if (pdev != NULL) 489 get_device(&pdev->dev); 490 return (pdev); 491 } 492 493 static __inline void 494 pci_dev_put(struct pci_dev *pdev) 495 { 496 497 if (pdev != NULL) 498 put_device(&pdev->dev); 499 } 500 501 static inline int 502 pci_enable_device(struct pci_dev *pdev) 503 { 504 505 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 506 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 507 return (0); 508 } 509 510 static inline void 511 pci_disable_device(struct pci_dev *pdev) 512 { 513 514 pci_disable_busmaster(pdev->dev.bsddev); 515 } 516 517 static inline int 518 pci_set_master(struct pci_dev *pdev) 519 { 520 521 pci_enable_busmaster(pdev->dev.bsddev); 522 return (0); 523 } 524 525 static inline int 526 pci_set_power_state(struct pci_dev *pdev, int state) 527 { 528 529 pci_set_powerstate(pdev->dev.bsddev, state); 530 return (0); 531 } 532 533 static inline int 534 pci_clear_master(struct pci_dev *pdev) 535 { 536 537 pci_disable_busmaster(pdev->dev.bsddev); 538 return (0); 539 } 540 541 static inline bool 542 pci_is_root_bus(struct pci_bus *pbus) 543 { 544 545 return (pbus->self == NULL); 546 } 547 548 static inline struct pci_dev * 549 pci_upstream_bridge(struct pci_dev *pdev) 550 { 551 552 if (pci_is_root_bus(pdev->bus)) 553 return (NULL); 554 555 /* 556 * If we do not have a (proper) "upstream bridge" set, e.g., we point 557 * to ourselves, try to handle this case on the fly like we do 558 * for pcie_find_root_port(). 559 */ 560 if (pdev == pdev->bus->self) { 561 device_t bridge; 562 563 bridge = device_get_parent(pdev->dev.bsddev); 564 if (bridge == NULL) 565 goto done; 566 bridge = device_get_parent(bridge); 567 if (bridge == NULL) 568 goto done; 569 if (device_get_devclass(device_get_parent(bridge)) != 570 devclass_find("pci")) 571 goto done; 572 573 /* 574 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 575 * for it so it can be returned. 576 */ 577 pdev->bus->self = lkpinew_pci_dev(bridge); 578 } 579 done: 580 return (pdev->bus->self); 581 } 582 583 static inline struct pci_devres * 584 lkpi_pci_devres_find(struct pci_dev *pdev) 585 { 586 587 if (!pdev->managed) 588 return (NULL); 589 590 return (lkpi_pci_devres_get_alloc(pdev)); 591 } 592 593 static inline void 594 pci_release_region(struct pci_dev *pdev, int bar) 595 { 596 struct resource_list_entry *rle; 597 struct pci_devres *dr; 598 struct pci_mmio_region *mmio, *p; 599 600 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 601 return; 602 603 /* 604 * As we implicitly track the requests we also need to clear them on 605 * release. Do clear before resource release. 606 */ 607 dr = lkpi_pci_devres_find(pdev); 608 if (dr != NULL) { 609 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 610 " region_table res %p != rel->res %p\n", __func__, pdev, 611 bar, dr->region_table[bar], rle->res)); 612 dr->region_table[bar] = NULL; 613 dr->region_mask &= ~(1 << bar); 614 } 615 616 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 617 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 618 continue; 619 TAILQ_REMOVE(&pdev->mmio, mmio, next); 620 free(mmio, M_DEVBUF); 621 } 622 623 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 624 } 625 626 static inline void 627 pci_release_regions(struct pci_dev *pdev) 628 { 629 int i; 630 631 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 632 pci_release_region(pdev, i); 633 } 634 635 static inline int 636 pci_request_regions(struct pci_dev *pdev, const char *res_name) 637 { 638 int error; 639 int i; 640 641 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 642 error = pci_request_region(pdev, i, res_name); 643 if (error && error != -ENODEV) { 644 pci_release_regions(pdev); 645 return (error); 646 } 647 } 648 return (0); 649 } 650 651 static inline void 652 lkpi_pci_disable_msix(struct pci_dev *pdev) 653 { 654 655 pci_release_msi(pdev->dev.bsddev); 656 657 /* 658 * The MSIX IRQ numbers associated with this PCI device are no 659 * longer valid and might be re-assigned. Make sure 660 * linux_pci_find_irq_dev() does no longer see them by 661 * resetting their references to zero: 662 */ 663 pdev->dev.irq_start = 0; 664 pdev->dev.irq_end = 0; 665 pdev->msix_enabled = false; 666 } 667 /* Only for consistency. No conflict on that one. */ 668 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 669 670 static inline void 671 lkpi_pci_disable_msi(struct pci_dev *pdev) 672 { 673 674 pci_release_msi(pdev->dev.bsddev); 675 676 pdev->dev.irq_start = 0; 677 pdev->dev.irq_end = 0; 678 pdev->irq = pdev->dev.irq; 679 pdev->msi_enabled = false; 680 } 681 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 682 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 683 684 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 685 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 686 687 static inline bus_addr_t 688 pci_bus_address(struct pci_dev *pdev, int bar) 689 { 690 691 return (pci_resource_start(pdev, bar)); 692 } 693 694 #define PCI_CAP_ID_EXP PCIY_EXPRESS 695 #define PCI_CAP_ID_PCIX PCIY_PCIX 696 #define PCI_CAP_ID_AGP PCIY_AGP 697 #define PCI_CAP_ID_PM PCIY_PMG 698 699 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 700 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 701 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 702 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 703 #define PCI_EXP_LNKSTA PCIER_LINK_STA 704 705 static inline int 706 pci_find_capability(struct pci_dev *pdev, int capid) 707 { 708 int reg; 709 710 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 711 return (0); 712 return (reg); 713 } 714 715 static inline int pci_pcie_cap(struct pci_dev *dev) 716 { 717 return pci_find_capability(dev, PCI_CAP_ID_EXP); 718 } 719 720 static inline int 721 pci_find_ext_capability(struct pci_dev *pdev, int capid) 722 { 723 int reg; 724 725 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 726 return (0); 727 return (reg); 728 } 729 730 #define PCIM_PCAP_PME_SHIFT 11 731 static __inline bool 732 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 733 { 734 struct pci_devinfo *dinfo; 735 pcicfgregs *cfg; 736 737 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 738 return (false); 739 740 dinfo = device_get_ivars(pdev->dev.bsddev); 741 cfg = &dinfo->cfg; 742 743 if (cfg->pp.pp_cap == 0) 744 return (false); 745 746 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 747 return (true); 748 749 return (false); 750 } 751 752 static inline int 753 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 754 { 755 756 if (!pci_enable_aspm) 757 return (-EPERM); 758 759 return (-ENXIO); 760 } 761 762 static inline int 763 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 764 { 765 766 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 767 return (0); 768 } 769 770 static inline int 771 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 772 { 773 774 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 775 return (0); 776 } 777 778 static inline int 779 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 780 { 781 782 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 783 return (0); 784 } 785 786 static inline int 787 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 788 { 789 790 pci_write_config(pdev->dev.bsddev, where, val, 1); 791 return (0); 792 } 793 794 static inline int 795 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 796 { 797 798 pci_write_config(pdev->dev.bsddev, where, val, 2); 799 return (0); 800 } 801 802 static inline int 803 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 804 { 805 806 pci_write_config(pdev->dev.bsddev, where, val, 4); 807 return (0); 808 } 809 810 int linux_pci_register_driver(struct pci_driver *pdrv); 811 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 812 void linux_pci_unregister_driver(struct pci_driver *pdrv); 813 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 814 815 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 816 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 817 818 struct msix_entry { 819 int entry; 820 int vector; 821 }; 822 823 /* 824 * Enable msix, positive errors indicate actual number of available 825 * vectors. Negative errors are failures. 826 * 827 * NB: define added to prevent this definition of pci_enable_msix from 828 * clashing with the native FreeBSD version. 829 */ 830 #define pci_enable_msix(...) \ 831 linux_pci_enable_msix(__VA_ARGS__) 832 833 static inline int 834 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 835 { 836 struct resource_list_entry *rle; 837 int error; 838 int avail; 839 int i; 840 841 avail = pci_msix_count(pdev->dev.bsddev); 842 if (avail < nreq) { 843 if (avail == 0) 844 return -EINVAL; 845 return avail; 846 } 847 avail = nreq; 848 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 849 return error; 850 /* 851 * Handle case where "pci_alloc_msix()" may allocate less 852 * interrupts than available and return with no error: 853 */ 854 if (avail < nreq) { 855 pci_release_msi(pdev->dev.bsddev); 856 return avail; 857 } 858 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 859 pdev->dev.irq_start = rle->start; 860 pdev->dev.irq_end = rle->start + avail; 861 for (i = 0; i < nreq; i++) 862 entries[i].vector = pdev->dev.irq_start + i; 863 pdev->msix_enabled = true; 864 return (0); 865 } 866 867 #define pci_enable_msix_range(...) \ 868 linux_pci_enable_msix_range(__VA_ARGS__) 869 870 static inline int 871 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 872 int minvec, int maxvec) 873 { 874 int nvec = maxvec; 875 int rc; 876 877 if (maxvec < minvec) 878 return (-ERANGE); 879 880 do { 881 rc = pci_enable_msix(dev, entries, nvec); 882 if (rc < 0) { 883 return (rc); 884 } else if (rc > 0) { 885 if (rc < minvec) 886 return (-ENOSPC); 887 nvec = rc; 888 } 889 } while (rc); 890 return (nvec); 891 } 892 893 #define pci_enable_msi(pdev) \ 894 linux_pci_enable_msi(pdev) 895 896 static inline int 897 _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec) 898 { 899 struct resource_list_entry *rle; 900 int error; 901 int nvec; 902 903 if (maxvec < minvec) 904 return (-EINVAL); 905 906 nvec = pci_msi_count(pdev->dev.bsddev); 907 if (nvec < 1 || nvec < minvec) 908 return (-ENOSPC); 909 910 nvec = min(nvec, maxvec); 911 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &nvec)) != 0) 912 return error; 913 914 /* Native PCI might only ever ask for 32 vectors. */ 915 if (nvec < minvec) { 916 pci_release_msi(pdev->dev.bsddev); 917 return (-ENOSPC); 918 } 919 920 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 921 pdev->dev.irq_start = rle->start; 922 pdev->dev.irq_end = rle->start + nvec; 923 pdev->irq = rle->start; 924 pdev->msi_enabled = true; 925 return (0); 926 } 927 928 static inline int 929 pci_enable_msi(struct pci_dev *pdev) 930 { 931 932 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 933 } 934 935 static inline int 936 pci_channel_offline(struct pci_dev *pdev) 937 { 938 939 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 940 } 941 942 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 943 { 944 return -ENODEV; 945 } 946 947 static inline void pci_disable_sriov(struct pci_dev *dev) 948 { 949 } 950 951 static inline void * 952 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 953 { 954 struct resource *res; 955 956 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 957 if (res == NULL) 958 return (NULL); 959 /* This is a FreeBSD extension so we can use bus_*(). */ 960 if (pdev->want_iomap_res) 961 return (res); 962 return ((void *)rman_get_bushandle(res)); 963 } 964 965 static inline void 966 pci_iounmap(struct pci_dev *pdev, void *res) 967 { 968 struct pci_mmio_region *mmio, *p; 969 970 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 971 if (res != (void *)rman_get_bushandle(mmio->res)) 972 continue; 973 bus_release_resource(pdev->dev.bsddev, 974 mmio->type, mmio->rid, mmio->res); 975 TAILQ_REMOVE(&pdev->mmio, mmio, next); 976 free(mmio, M_DEVBUF); 977 return; 978 } 979 } 980 981 static inline void 982 lkpi_pci_save_state(struct pci_dev *pdev) 983 { 984 985 pci_save_state(pdev->dev.bsddev); 986 } 987 988 static inline void 989 lkpi_pci_restore_state(struct pci_dev *pdev) 990 { 991 992 pci_restore_state(pdev->dev.bsddev); 993 } 994 995 #define pci_save_state(dev) lkpi_pci_save_state(dev) 996 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 997 998 static inline int 999 pci_reset_function(struct pci_dev *pdev) 1000 { 1001 1002 return (-ENOSYS); 1003 } 1004 1005 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 1006 const struct pci_device_id _table[] __devinitdata 1007 1008 /* XXX This should not be necessary. */ 1009 #define pcix_set_mmrbc(d, v) 0 1010 #define pcix_get_max_mmrbc(d) 0 1011 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 1012 1013 #define PCI_DMA_BIDIRECTIONAL 0 1014 #define PCI_DMA_TODEVICE 1 1015 #define PCI_DMA_FROMDEVICE 2 1016 #define PCI_DMA_NONE 3 1017 1018 #define pci_pool dma_pool 1019 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 1020 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 1021 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 1022 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 1023 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 1024 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 1025 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1026 _size, _vaddr, _dma_handle) 1027 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 1028 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1029 _sg, _nents, (enum dma_data_direction)_dir) 1030 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 1031 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1032 (_ptr), (_size), (enum dma_data_direction)_dir) 1033 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 1034 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1035 _addr, _size, (enum dma_data_direction)_dir) 1036 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 1037 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1038 _sg, _nents, (enum dma_data_direction)_dir) 1039 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 1040 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 1041 _offset, _size, (enum dma_data_direction)_dir) 1042 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 1043 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1044 _dma_address, _size, (enum dma_data_direction)_dir) 1045 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1046 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1047 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1048 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1049 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1050 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1051 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1052 #define pci_unmap_addr dma_unmap_addr 1053 #define pci_unmap_addr_set dma_unmap_addr_set 1054 #define pci_unmap_len dma_unmap_len 1055 #define pci_unmap_len_set dma_unmap_len_set 1056 1057 typedef unsigned int __bitwise pci_channel_state_t; 1058 typedef unsigned int __bitwise pci_ers_result_t; 1059 1060 enum pci_channel_state { 1061 pci_channel_io_normal = 1, 1062 pci_channel_io_frozen = 2, 1063 pci_channel_io_perm_failure = 3, 1064 }; 1065 1066 enum pci_ers_result { 1067 PCI_ERS_RESULT_NONE = 1, 1068 PCI_ERS_RESULT_CAN_RECOVER = 2, 1069 PCI_ERS_RESULT_NEED_RESET = 3, 1070 PCI_ERS_RESULT_DISCONNECT = 4, 1071 PCI_ERS_RESULT_RECOVERED = 5, 1072 }; 1073 1074 /* PCI bus error event callbacks */ 1075 struct pci_error_handlers { 1076 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1077 enum pci_channel_state error); 1078 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1079 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1080 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1081 void (*resume)(struct pci_dev *dev); 1082 }; 1083 1084 /* FreeBSD does not support SRIOV - yet */ 1085 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1086 { 1087 return dev; 1088 } 1089 1090 static inline bool pci_is_pcie(struct pci_dev *dev) 1091 { 1092 return !!pci_pcie_cap(dev); 1093 } 1094 1095 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1096 { 1097 int pos; 1098 u16 reg16; 1099 1100 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1101 if (!pos) 1102 return 0; 1103 1104 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1105 1106 return reg16; 1107 } 1108 1109 static inline int pci_pcie_type(struct pci_dev *dev) 1110 { 1111 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1112 } 1113 1114 static inline int pcie_cap_version(struct pci_dev *dev) 1115 { 1116 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1117 } 1118 1119 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1120 { 1121 int type = pci_pcie_type(dev); 1122 1123 return pcie_cap_version(dev) > 1 || 1124 type == PCI_EXP_TYPE_ROOT_PORT || 1125 type == PCI_EXP_TYPE_ENDPOINT || 1126 type == PCI_EXP_TYPE_LEG_END; 1127 } 1128 1129 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1130 { 1131 return true; 1132 } 1133 1134 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1135 { 1136 int type = pci_pcie_type(dev); 1137 1138 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1139 (type == PCI_EXP_TYPE_DOWNSTREAM && 1140 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1141 } 1142 1143 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1144 { 1145 int type = pci_pcie_type(dev); 1146 1147 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1148 type == PCI_EXP_TYPE_RC_EC; 1149 } 1150 1151 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1152 { 1153 if (!pci_is_pcie(dev)) 1154 return false; 1155 1156 switch (pos) { 1157 case PCI_EXP_FLAGS_TYPE: 1158 return true; 1159 case PCI_EXP_DEVCAP: 1160 case PCI_EXP_DEVCTL: 1161 case PCI_EXP_DEVSTA: 1162 return pcie_cap_has_devctl(dev); 1163 case PCI_EXP_LNKCAP: 1164 case PCI_EXP_LNKCTL: 1165 case PCI_EXP_LNKSTA: 1166 return pcie_cap_has_lnkctl(dev); 1167 case PCI_EXP_SLTCAP: 1168 case PCI_EXP_SLTCTL: 1169 case PCI_EXP_SLTSTA: 1170 return pcie_cap_has_sltctl(dev); 1171 case PCI_EXP_RTCTL: 1172 case PCI_EXP_RTCAP: 1173 case PCI_EXP_RTSTA: 1174 return pcie_cap_has_rtctl(dev); 1175 case PCI_EXP_DEVCAP2: 1176 case PCI_EXP_DEVCTL2: 1177 case PCI_EXP_LNKCAP2: 1178 case PCI_EXP_LNKCTL2: 1179 case PCI_EXP_LNKSTA2: 1180 return pcie_cap_version(dev) > 1; 1181 default: 1182 return false; 1183 } 1184 } 1185 1186 static inline int 1187 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1188 { 1189 *dst = 0; 1190 if (pos & 3) 1191 return -EINVAL; 1192 1193 if (!pcie_capability_reg_implemented(dev, pos)) 1194 return -EINVAL; 1195 1196 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1197 } 1198 1199 static inline int 1200 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1201 { 1202 *dst = 0; 1203 if (pos & 3) 1204 return -EINVAL; 1205 1206 if (!pcie_capability_reg_implemented(dev, pos)) 1207 return -EINVAL; 1208 1209 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1210 } 1211 1212 static inline int 1213 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1214 { 1215 if (pos & 1) 1216 return -EINVAL; 1217 1218 if (!pcie_capability_reg_implemented(dev, pos)) 1219 return 0; 1220 1221 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1222 } 1223 1224 static inline int 1225 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1226 { 1227 int error; 1228 uint16_t v; 1229 1230 error = pcie_capability_read_word(dev, pos, &v); 1231 if (error != 0) 1232 return (error); 1233 1234 v |= val; 1235 1236 error = pcie_capability_write_word(dev, pos, v); 1237 return (error); 1238 } 1239 1240 static inline int 1241 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1242 { 1243 int error; 1244 uint16_t v; 1245 1246 error = pcie_capability_read_word(dev, pos, &v); 1247 if (error != 0) 1248 return (error); 1249 1250 v &= ~val; 1251 1252 error = pcie_capability_write_word(dev, pos, v); 1253 return (error); 1254 } 1255 1256 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1257 enum pci_bus_speed *speed, enum pcie_link_width *width) 1258 { 1259 *speed = PCI_SPEED_UNKNOWN; 1260 *width = PCIE_LNK_WIDTH_UNKNOWN; 1261 return (0); 1262 } 1263 1264 static inline int 1265 pci_num_vf(struct pci_dev *dev) 1266 { 1267 return (0); 1268 } 1269 1270 static inline enum pci_bus_speed 1271 pcie_get_speed_cap(struct pci_dev *dev) 1272 { 1273 device_t root; 1274 uint32_t lnkcap, lnkcap2; 1275 int error, pos; 1276 1277 root = device_get_parent(dev->dev.bsddev); 1278 if (root == NULL) 1279 return (PCI_SPEED_UNKNOWN); 1280 root = device_get_parent(root); 1281 if (root == NULL) 1282 return (PCI_SPEED_UNKNOWN); 1283 root = device_get_parent(root); 1284 if (root == NULL) 1285 return (PCI_SPEED_UNKNOWN); 1286 1287 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1288 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1289 return (PCI_SPEED_UNKNOWN); 1290 1291 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1292 return (PCI_SPEED_UNKNOWN); 1293 1294 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1295 1296 if (lnkcap2) { /* PCIe r3.0-compliant */ 1297 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1298 return (PCIE_SPEED_2_5GT); 1299 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1300 return (PCIE_SPEED_5_0GT); 1301 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1302 return (PCIE_SPEED_8_0GT); 1303 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1304 return (PCIE_SPEED_16_0GT); 1305 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1306 return (PCIE_SPEED_32_0GT); 1307 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1308 return (PCIE_SPEED_64_0GT); 1309 } else { /* pre-r3.0 */ 1310 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1311 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1312 return (PCIE_SPEED_2_5GT); 1313 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1314 return (PCIE_SPEED_5_0GT); 1315 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1316 return (PCIE_SPEED_8_0GT); 1317 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1318 return (PCIE_SPEED_16_0GT); 1319 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1320 return (PCIE_SPEED_32_0GT); 1321 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1322 return (PCIE_SPEED_64_0GT); 1323 } 1324 return (PCI_SPEED_UNKNOWN); 1325 } 1326 1327 static inline enum pcie_link_width 1328 pcie_get_width_cap(struct pci_dev *dev) 1329 { 1330 uint32_t lnkcap; 1331 1332 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1333 if (lnkcap) 1334 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1335 1336 return (PCIE_LNK_WIDTH_UNKNOWN); 1337 } 1338 1339 static inline int 1340 pcie_get_mps(struct pci_dev *dev) 1341 { 1342 return (pci_get_max_payload(dev->dev.bsddev)); 1343 } 1344 1345 static inline uint32_t 1346 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1347 { 1348 1349 switch(spd) { 1350 case PCIE_SPEED_64_0GT: 1351 return (64000 * 128 / 130); 1352 case PCIE_SPEED_32_0GT: 1353 return (32000 * 128 / 130); 1354 case PCIE_SPEED_16_0GT: 1355 return (16000 * 128 / 130); 1356 case PCIE_SPEED_8_0GT: 1357 return (8000 * 128 / 130); 1358 case PCIE_SPEED_5_0GT: 1359 return (5000 * 8 / 10); 1360 case PCIE_SPEED_2_5GT: 1361 return (2500 * 8 / 10); 1362 default: 1363 return (0); 1364 } 1365 } 1366 1367 static inline uint32_t 1368 pcie_bandwidth_available(struct pci_dev *pdev, 1369 struct pci_dev **limiting, 1370 enum pci_bus_speed *speed, 1371 enum pcie_link_width *width) 1372 { 1373 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1374 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1375 1376 if (speed) 1377 *speed = nspeed; 1378 if (width) 1379 *width = nwidth; 1380 1381 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1382 } 1383 1384 static inline bool 1385 pcie_aspm_enabled(struct pci_dev *pdev) 1386 { 1387 return (false); 1388 } 1389 1390 static inline struct pci_dev * 1391 pcie_find_root_port(struct pci_dev *pdev) 1392 { 1393 device_t root; 1394 1395 if (pdev->root != NULL) 1396 return (pdev->root); 1397 1398 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1399 if (root == NULL) 1400 return (NULL); 1401 1402 pdev->root = lkpinew_pci_dev(root); 1403 return (pdev->root); 1404 } 1405 1406 /* This is needed when people rip out the device "HotPlug". */ 1407 static inline void 1408 pci_lock_rescan_remove(void) 1409 { 1410 } 1411 1412 static inline void 1413 pci_unlock_rescan_remove(void) 1414 { 1415 } 1416 1417 static __inline void 1418 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1419 { 1420 } 1421 1422 static inline int 1423 pci_rescan_bus(struct pci_bus *pbus) 1424 { 1425 device_t *devlist, parent; 1426 int devcount, error; 1427 1428 if (!device_is_attached(pbus->self->dev.bsddev)) 1429 return (0); 1430 /* pci_rescan_method() will work on the pcib (parent). */ 1431 error = BUS_RESCAN(pbus->self->dev.bsddev); 1432 if (error != 0) 1433 return (0); 1434 1435 parent = device_get_parent(pbus->self->dev.bsddev); 1436 error = device_get_children(parent, &devlist, &devcount); 1437 if (error != 0) 1438 return (0); 1439 if (devcount != 0) 1440 free(devlist, M_TEMP); 1441 1442 return (devcount); 1443 } 1444 1445 /* 1446 * The following functions can be used to attach/detach the LinuxKPI's 1447 * PCI device runtime. The pci_driver and pci_device_id pointer is 1448 * allowed to be NULL. Other pointers must be all valid. 1449 * The pci_dev structure should be zero-initialized before passed 1450 * to the linux_pci_attach_device function. 1451 */ 1452 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1453 const struct pci_device_id *, struct pci_dev *); 1454 extern int linux_pci_detach_device(struct pci_dev *); 1455 1456 static inline int 1457 pci_dev_present(const struct pci_device_id *cur) 1458 { 1459 while (cur != NULL && (cur->vendor || cur->device)) { 1460 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1461 return (1); 1462 } 1463 cur++; 1464 } 1465 return (0); 1466 } 1467 1468 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1469 unsigned int bus, unsigned int devfn); 1470 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1471 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1472 1473 static inline int 1474 pci_domain_nr(struct pci_bus *pbus) 1475 { 1476 1477 return (pbus->domain); 1478 } 1479 1480 static inline int 1481 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1482 int pos, uint32_t *val, int len) 1483 { 1484 1485 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1486 return (0); 1487 } 1488 1489 static inline int 1490 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1491 { 1492 uint32_t tmp; 1493 int ret; 1494 1495 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1496 *val = (u16)tmp; 1497 return (ret); 1498 } 1499 1500 static inline int 1501 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1502 { 1503 uint32_t tmp; 1504 int ret; 1505 1506 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1507 *val = (u8)tmp; 1508 return (ret); 1509 } 1510 1511 static inline int 1512 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1513 uint32_t val, int size) 1514 { 1515 1516 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1517 return (0); 1518 } 1519 1520 static inline int 1521 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1522 uint8_t val) 1523 { 1524 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1525 } 1526 1527 static inline int 1528 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1529 uint16_t val) 1530 { 1531 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1532 } 1533 1534 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1535 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1536 1537 /* -------------------------------------------------------------------------- */ 1538 1539 static inline int 1540 pcim_enable_device(struct pci_dev *pdev) 1541 { 1542 struct pci_devres *dr; 1543 int error; 1544 1545 /* Here we cannot run through the pdev->managed check. */ 1546 dr = lkpi_pci_devres_get_alloc(pdev); 1547 if (dr == NULL) 1548 return (-ENOMEM); 1549 1550 /* If resources were enabled before do not do it again. */ 1551 if (dr->enable_io) 1552 return (0); 1553 1554 error = pci_enable_device(pdev); 1555 if (error == 0) 1556 dr->enable_io = true; 1557 1558 /* This device is not managed. */ 1559 pdev->managed = true; 1560 1561 return (error); 1562 } 1563 1564 static inline void __iomem ** 1565 pcim_iomap_table(struct pci_dev *pdev) 1566 { 1567 struct pcim_iomap_devres *dr; 1568 1569 dr = lkpi_pcim_iomap_devres_find(pdev); 1570 if (dr == NULL) 1571 return (NULL); 1572 1573 /* 1574 * If the driver has manually set a flag to be able to request the 1575 * resource to use bus_read/write_<n>, return the shadow table. 1576 */ 1577 if (pdev->want_iomap_res) 1578 return ((void **)dr->res_table); 1579 1580 /* This is the Linux default. */ 1581 return (dr->mmio_table); 1582 } 1583 1584 static inline int 1585 pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, const char *name) 1586 { 1587 struct pcim_iomap_devres *dr; 1588 void *res; 1589 uint32_t mappings; 1590 int bar; 1591 1592 dr = lkpi_pcim_iomap_devres_find(pdev); 1593 if (dr == NULL) 1594 return (-ENOMEM); 1595 1596 /* Now iomap all the requested (by "mask") ones. */ 1597 for (bar = mappings = 0; mappings != mask; bar++) { 1598 if ((mask & (1 << bar)) == 0) 1599 continue; 1600 1601 /* Request double is not allowed. */ 1602 if (dr->mmio_table[bar] != NULL) { 1603 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1604 __func__, bar, dr->mmio_table[bar]); 1605 goto err; 1606 } 1607 1608 res = _lkpi_pci_iomap(pdev, bar, 0); 1609 if (res == NULL) 1610 goto err; 1611 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1612 dr->res_table[bar] = res; 1613 1614 mappings |= (1 << bar); 1615 } 1616 1617 return (0); 1618 err: 1619 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1620 if ((mappings & (1 << bar)) != 0) { 1621 res = dr->mmio_table[bar]; 1622 if (res == NULL) 1623 continue; 1624 pci_iounmap(pdev, res); 1625 } 1626 } 1627 1628 return (-EINVAL); 1629 } 1630 1631 static inline int 1632 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1633 { 1634 uint32_t requests, req_mask; 1635 int bar, error; 1636 1637 /* Request all the BARs ("regions") we do not iomap. */ 1638 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1639 for (bar = requests = 0; requests != req_mask; bar++) { 1640 if ((req_mask & (1 << bar)) == 0) 1641 continue; 1642 error = pci_request_region(pdev, bar, name); 1643 if (error != 0 && error != -ENODEV) 1644 goto err; 1645 requests |= (1 << bar); 1646 } 1647 1648 error = pcim_iomap_regions(pdev, mask, name); 1649 if (error != 0) 1650 goto err; 1651 1652 return (0); 1653 1654 err: 1655 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1656 if ((requests & (1 << bar)) != 0) 1657 pci_release_region(pdev, bar); 1658 } 1659 1660 return (-EINVAL); 1661 } 1662 1663 /* 1664 * We cannot simply re-define pci_get_device() as we would normally do 1665 * and then hide it in linux_pci.c as too many semi-native drivers still 1666 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1667 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1668 */ 1669 static inline struct pci_dev * 1670 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1671 { 1672 1673 return (lkpi_pci_get_device(vendor, device, odev)); 1674 } 1675 1676 /* This is a FreeBSD extension so we can use bus_*(). */ 1677 static inline void 1678 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1679 { 1680 pdev->want_iomap_res = true; 1681 } 1682 1683 static inline bool 1684 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1685 { 1686 1687 return (false); 1688 } 1689 1690 static inline void * 1691 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1692 { 1693 1694 return (NULL); 1695 } 1696 1697 static inline void 1698 pci_ignore_hotplug(struct pci_dev *pdev) 1699 { 1700 } 1701 1702 static inline const char * 1703 pci_power_name(pci_power_t state) 1704 { 1705 int pstate = state + 1; 1706 1707 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1708 return (pci_power_names[pstate]); 1709 else 1710 return (pci_power_names[0]); 1711 } 1712 1713 static inline int 1714 pcie_get_readrq(struct pci_dev *dev) 1715 { 1716 u16 ctl; 1717 1718 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1719 return (-EINVAL); 1720 1721 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1722 } 1723 1724 static inline bool 1725 pci_is_enabled(struct pci_dev *pdev) 1726 { 1727 1728 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1729 PCIM_CMD_BUSMASTEREN) != 0); 1730 } 1731 1732 static inline int 1733 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1734 { 1735 1736 return (0); 1737 } 1738 1739 static inline int 1740 pci_assign_resource(struct pci_dev *pdev, int bar) 1741 { 1742 1743 return (0); 1744 } 1745 1746 static inline int 1747 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1748 { 1749 1750 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1751 if (vector != 0) 1752 return (-EINVAL); 1753 return (pdev->irq); 1754 } 1755 1756 if (pdev->msix_enabled || pdev->msi_enabled) { 1757 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1758 return (-EINVAL); 1759 return (pdev->dev.irq_start + vector); 1760 } 1761 1762 return (-ENXIO); 1763 } 1764 1765 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1766