1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/nv.h> 41 #include <sys/pciio.h> 42 #include <sys/rman.h> 43 #include <sys/bus.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pci_private.h> 47 48 #include <machine/resource.h> 49 50 #include <linux/list.h> 51 #include <linux/dmapool.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/compiler.h> 54 #include <linux/errno.h> 55 #include <asm/atomic.h> 56 #include <linux/device.h> 57 #include <linux/pci_ids.h> 58 59 struct pci_device_id { 60 uint32_t vendor; 61 uint32_t device; 62 uint32_t subvendor; 63 uint32_t subdevice; 64 uint32_t class; 65 uint32_t class_mask; 66 uintptr_t driver_data; 67 }; 68 69 #define MODULE_DEVICE_TABLE(bus, table) 70 71 #define PCI_ANY_ID -1U 72 73 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 74 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 75 #define PCI_FUNC(devfn) ((devfn) & 0x07) 76 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 77 78 #define PCI_VDEVICE(_vendor, _device) \ 79 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 80 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 81 #define PCI_DEVICE(_vendor, _device) \ 82 .vendor = (_vendor), .device = (_device), \ 83 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 84 85 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 86 87 #define PCI_VENDOR_ID PCIR_DEVVENDOR 88 #define PCI_COMMAND PCIR_COMMAND 89 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 90 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 91 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 92 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 93 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 94 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 95 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 96 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 97 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 98 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 99 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 100 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 101 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 102 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 103 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 104 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 105 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 106 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 107 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 108 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 109 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 110 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 111 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 112 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 113 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 114 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 115 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 116 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 117 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 118 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 119 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 120 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 121 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 122 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 123 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 124 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 125 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 126 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 127 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 128 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 129 130 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 131 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 132 #define PCI_EXP_DEVSTA_TRPND 0x0020 133 134 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 135 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 136 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 137 138 enum pci_bus_speed { 139 PCI_SPEED_UNKNOWN = -1, 140 PCIE_SPEED_2_5GT, 141 PCIE_SPEED_5_0GT, 142 PCIE_SPEED_8_0GT, 143 PCIE_SPEED_16_0GT, 144 }; 145 146 enum pcie_link_width { 147 PCIE_LNK_WIDTH_RESRV = 0x00, 148 PCIE_LNK_X1 = 0x01, 149 PCIE_LNK_X2 = 0x02, 150 PCIE_LNK_X4 = 0x04, 151 PCIE_LNK_X8 = 0x08, 152 PCIE_LNK_X12 = 0x0c, 153 PCIE_LNK_X16 = 0x10, 154 PCIE_LNK_X32 = 0x20, 155 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 156 }; 157 158 #define PCIE_LINK_STATE_L0S 0x00000001 159 #define PCIE_LINK_STATE_L1 0x00000002 160 #define PCIE_LINK_STATE_CLKPM 0x00000004 161 162 typedef int pci_power_t; 163 164 #define PCI_D0 PCI_POWERSTATE_D0 165 #define PCI_D1 PCI_POWERSTATE_D1 166 #define PCI_D2 PCI_POWERSTATE_D2 167 #define PCI_D3hot PCI_POWERSTATE_D3 168 #define PCI_D3cold 4 169 170 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 171 172 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 173 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 174 175 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 176 177 struct pci_dev; 178 179 struct pci_driver { 180 struct list_head links; 181 char *name; 182 const struct pci_device_id *id_table; 183 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 184 void (*remove)(struct pci_dev *dev); 185 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 186 int (*resume) (struct pci_dev *dev); /* Device woken up */ 187 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 188 driver_t bsddriver; 189 devclass_t bsdclass; 190 struct device_driver driver; 191 const struct pci_error_handlers *err_handler; 192 bool isdrm; 193 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 194 const nvlist_t *pf_config); 195 void (*bsd_iov_uninit)(device_t dev); 196 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 197 const nvlist_t *vf_config); 198 }; 199 200 struct pci_bus { 201 struct pci_dev *self; 202 int domain; 203 int number; 204 }; 205 206 extern struct list_head pci_drivers; 207 extern struct list_head pci_devices; 208 extern spinlock_t pci_lock; 209 210 #define __devexit_p(x) x 211 212 struct pci_mmio_region { 213 TAILQ_ENTRY(pci_mmio_region) next; 214 struct resource *res; 215 int rid; 216 int type; 217 }; 218 219 struct pci_dev { 220 struct device dev; 221 struct list_head links; 222 struct pci_driver *pdrv; 223 struct pci_bus *bus; 224 uint16_t device; 225 uint16_t vendor; 226 uint16_t subsystem_vendor; 227 uint16_t subsystem_device; 228 unsigned int irq; 229 unsigned int devfn; 230 uint32_t class; 231 uint8_t revision; 232 bool msi_enabled; 233 234 TAILQ_HEAD(, pci_mmio_region) mmio; 235 }; 236 237 static inline struct resource_list_entry * 238 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 239 { 240 struct pci_devinfo *dinfo; 241 struct resource_list *rl; 242 243 dinfo = device_get_ivars(pdev->dev.bsddev); 244 rl = &dinfo->resources; 245 return resource_list_find(rl, type, rid); 246 } 247 248 static inline struct resource_list_entry * 249 linux_pci_get_bar(struct pci_dev *pdev, int bar) 250 { 251 struct resource_list_entry *rle; 252 253 bar = PCIR_BAR(bar); 254 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 255 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 256 return (rle); 257 } 258 259 static inline struct device * 260 linux_pci_find_irq_dev(unsigned int irq) 261 { 262 struct pci_dev *pdev; 263 struct device *found; 264 265 found = NULL; 266 spin_lock(&pci_lock); 267 list_for_each_entry(pdev, &pci_devices, links) { 268 if (irq == pdev->dev.irq || 269 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 270 found = &pdev->dev; 271 break; 272 } 273 } 274 spin_unlock(&pci_lock); 275 return (found); 276 } 277 278 static inline int 279 pci_resource_type(struct pci_dev *pdev, int bar) 280 { 281 struct pci_map *pm; 282 283 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 284 if (!pm) 285 return (-1); 286 287 if (PCI_BAR_IO(pm->pm_value)) 288 return (SYS_RES_IOPORT); 289 else 290 return (SYS_RES_MEMORY); 291 } 292 293 /* 294 * All drivers just seem to want to inspect the type not flags. 295 */ 296 static inline int 297 pci_resource_flags(struct pci_dev *pdev, int bar) 298 { 299 int type; 300 301 type = pci_resource_type(pdev, bar); 302 if (type < 0) 303 return (0); 304 return (1 << type); 305 } 306 307 static inline const char * 308 pci_name(struct pci_dev *d) 309 { 310 311 return device_get_desc(d->dev.bsddev); 312 } 313 314 static inline void * 315 pci_get_drvdata(struct pci_dev *pdev) 316 { 317 318 return dev_get_drvdata(&pdev->dev); 319 } 320 321 static inline void 322 pci_set_drvdata(struct pci_dev *pdev, void *data) 323 { 324 325 dev_set_drvdata(&pdev->dev, data); 326 } 327 328 static __inline void 329 pci_dev_put(struct pci_dev *pdev) 330 { 331 332 if (pdev != NULL) 333 put_device(&pdev->dev); 334 } 335 336 static inline int 337 pci_enable_device(struct pci_dev *pdev) 338 { 339 340 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 341 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 342 return (0); 343 } 344 345 static inline void 346 pci_disable_device(struct pci_dev *pdev) 347 { 348 349 pci_disable_busmaster(pdev->dev.bsddev); 350 } 351 352 static inline int 353 pci_set_master(struct pci_dev *pdev) 354 { 355 356 pci_enable_busmaster(pdev->dev.bsddev); 357 return (0); 358 } 359 360 static inline int 361 pci_set_power_state(struct pci_dev *pdev, int state) 362 { 363 364 pci_set_powerstate(pdev->dev.bsddev, state); 365 return (0); 366 } 367 368 static inline int 369 pci_clear_master(struct pci_dev *pdev) 370 { 371 372 pci_disable_busmaster(pdev->dev.bsddev); 373 return (0); 374 } 375 376 static inline int 377 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 378 { 379 int rid; 380 int type; 381 382 type = pci_resource_type(pdev, bar); 383 if (type < 0) 384 return (-ENODEV); 385 rid = PCIR_BAR(bar); 386 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 387 RF_ACTIVE) == NULL) 388 return (-EINVAL); 389 return (0); 390 } 391 392 static inline void 393 pci_release_region(struct pci_dev *pdev, int bar) 394 { 395 struct resource_list_entry *rle; 396 397 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 398 return; 399 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 400 } 401 402 static inline void 403 pci_release_regions(struct pci_dev *pdev) 404 { 405 int i; 406 407 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 408 pci_release_region(pdev, i); 409 } 410 411 static inline int 412 pci_request_regions(struct pci_dev *pdev, const char *res_name) 413 { 414 int error; 415 int i; 416 417 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 418 error = pci_request_region(pdev, i, res_name); 419 if (error && error != -ENODEV) { 420 pci_release_regions(pdev); 421 return (error); 422 } 423 } 424 return (0); 425 } 426 427 static inline void 428 pci_disable_msix(struct pci_dev *pdev) 429 { 430 431 pci_release_msi(pdev->dev.bsddev); 432 433 /* 434 * The MSIX IRQ numbers associated with this PCI device are no 435 * longer valid and might be re-assigned. Make sure 436 * linux_pci_find_irq_dev() does no longer see them by 437 * resetting their references to zero: 438 */ 439 pdev->dev.irq_start = 0; 440 pdev->dev.irq_end = 0; 441 } 442 443 #define pci_disable_msi(pdev) \ 444 linux_pci_disable_msi(pdev) 445 446 static inline void 447 linux_pci_disable_msi(struct pci_dev *pdev) 448 { 449 450 pci_release_msi(pdev->dev.bsddev); 451 452 pdev->dev.irq_start = 0; 453 pdev->dev.irq_end = 0; 454 pdev->irq = pdev->dev.irq; 455 pdev->msi_enabled = false; 456 } 457 458 #define pci_free_irq_vectors(pdev) \ 459 linux_pci_disable_msi(pdev) 460 461 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 462 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 463 464 static inline bus_addr_t 465 pci_bus_address(struct pci_dev *pdev, int bar) 466 { 467 468 return (pci_resource_start(pdev, bar)); 469 } 470 471 #define PCI_CAP_ID_EXP PCIY_EXPRESS 472 #define PCI_CAP_ID_PCIX PCIY_PCIX 473 #define PCI_CAP_ID_AGP PCIY_AGP 474 #define PCI_CAP_ID_PM PCIY_PMG 475 476 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 477 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 478 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 479 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 480 #define PCI_EXP_LNKSTA PCIER_LINK_STA 481 482 static inline int 483 pci_find_capability(struct pci_dev *pdev, int capid) 484 { 485 int reg; 486 487 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 488 return (0); 489 return (reg); 490 } 491 492 static inline int pci_pcie_cap(struct pci_dev *dev) 493 { 494 return pci_find_capability(dev, PCI_CAP_ID_EXP); 495 } 496 497 static inline int 498 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 499 { 500 501 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 502 return (0); 503 } 504 505 static inline int 506 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 507 { 508 509 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 510 return (0); 511 } 512 513 static inline int 514 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 515 { 516 517 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 518 return (0); 519 } 520 521 static inline int 522 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 523 { 524 525 pci_write_config(pdev->dev.bsddev, where, val, 1); 526 return (0); 527 } 528 529 static inline int 530 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 531 { 532 533 pci_write_config(pdev->dev.bsddev, where, val, 2); 534 return (0); 535 } 536 537 static inline int 538 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 539 { 540 541 pci_write_config(pdev->dev.bsddev, where, val, 4); 542 return (0); 543 } 544 545 int linux_pci_register_driver(struct pci_driver *pdrv); 546 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 547 void linux_pci_unregister_driver(struct pci_driver *pdrv); 548 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 549 550 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 551 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 552 553 struct msix_entry { 554 int entry; 555 int vector; 556 }; 557 558 /* 559 * Enable msix, positive errors indicate actual number of available 560 * vectors. Negative errors are failures. 561 * 562 * NB: define added to prevent this definition of pci_enable_msix from 563 * clashing with the native FreeBSD version. 564 */ 565 #define pci_enable_msix(...) \ 566 linux_pci_enable_msix(__VA_ARGS__) 567 568 static inline int 569 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 570 { 571 struct resource_list_entry *rle; 572 int error; 573 int avail; 574 int i; 575 576 avail = pci_msix_count(pdev->dev.bsddev); 577 if (avail < nreq) { 578 if (avail == 0) 579 return -EINVAL; 580 return avail; 581 } 582 avail = nreq; 583 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 584 return error; 585 /* 586 * Handle case where "pci_alloc_msix()" may allocate less 587 * interrupts than available and return with no error: 588 */ 589 if (avail < nreq) { 590 pci_release_msi(pdev->dev.bsddev); 591 return avail; 592 } 593 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 594 pdev->dev.irq_start = rle->start; 595 pdev->dev.irq_end = rle->start + avail; 596 for (i = 0; i < nreq; i++) 597 entries[i].vector = pdev->dev.irq_start + i; 598 return (0); 599 } 600 601 #define pci_enable_msix_range(...) \ 602 linux_pci_enable_msix_range(__VA_ARGS__) 603 604 static inline int 605 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 606 int minvec, int maxvec) 607 { 608 int nvec = maxvec; 609 int rc; 610 611 if (maxvec < minvec) 612 return (-ERANGE); 613 614 do { 615 rc = pci_enable_msix(dev, entries, nvec); 616 if (rc < 0) { 617 return (rc); 618 } else if (rc > 0) { 619 if (rc < minvec) 620 return (-ENOSPC); 621 nvec = rc; 622 } 623 } while (rc); 624 return (nvec); 625 } 626 627 #define pci_enable_msi(pdev) \ 628 linux_pci_enable_msi(pdev) 629 630 static inline int 631 pci_enable_msi(struct pci_dev *pdev) 632 { 633 struct resource_list_entry *rle; 634 int error; 635 int avail; 636 637 avail = pci_msi_count(pdev->dev.bsddev); 638 if (avail < 1) 639 return -EINVAL; 640 641 avail = 1; /* this function only enable one MSI IRQ */ 642 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 643 return error; 644 645 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 646 pdev->dev.irq_start = rle->start; 647 pdev->dev.irq_end = rle->start + avail; 648 pdev->irq = rle->start; 649 pdev->msi_enabled = true; 650 return (0); 651 } 652 653 static inline int 654 pci_channel_offline(struct pci_dev *pdev) 655 { 656 657 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 658 } 659 660 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 661 { 662 return -ENODEV; 663 } 664 static inline void pci_disable_sriov(struct pci_dev *dev) 665 { 666 } 667 668 static inline void * 669 pci_iomap(struct pci_dev *dev, int mmio_bar, int mmio_size __unused) 670 { 671 struct pci_mmio_region *mmio; 672 673 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 674 mmio->rid = PCIR_BAR(mmio_bar); 675 mmio->type = pci_resource_type(dev, mmio_bar); 676 mmio->res = bus_alloc_resource_any(dev->dev.bsddev, mmio->type, 677 &mmio->rid, RF_ACTIVE); 678 if (mmio->res == NULL) { 679 free(mmio, M_DEVBUF); 680 return (NULL); 681 } 682 TAILQ_INSERT_TAIL(&dev->mmio, mmio, next); 683 684 return ((void *)rman_get_bushandle(mmio->res)); 685 } 686 687 static inline void 688 pci_iounmap(struct pci_dev *dev, void *res) 689 { 690 struct pci_mmio_region *mmio, *p; 691 692 TAILQ_FOREACH_SAFE(mmio, &dev->mmio, next, p) { 693 if (res != (void *)rman_get_bushandle(mmio->res)) 694 continue; 695 bus_release_resource(dev->dev.bsddev, 696 mmio->type, mmio->rid, mmio->res); 697 TAILQ_REMOVE(&dev->mmio, mmio, next); 698 free(mmio, M_DEVBUF); 699 return; 700 } 701 } 702 703 static inline void 704 lkpi_pci_save_state(struct pci_dev *pdev) 705 { 706 707 pci_save_state(pdev->dev.bsddev); 708 } 709 710 static inline void 711 lkpi_pci_restore_state(struct pci_dev *pdev) 712 { 713 714 pci_restore_state(pdev->dev.bsddev); 715 } 716 717 #define pci_save_state(dev) lkpi_pci_save_state(dev) 718 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 719 720 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 721 const struct pci_device_id _table[] __devinitdata 722 723 /* XXX This should not be necessary. */ 724 #define pcix_set_mmrbc(d, v) 0 725 #define pcix_get_max_mmrbc(d) 0 726 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 727 728 #define PCI_DMA_BIDIRECTIONAL 0 729 #define PCI_DMA_TODEVICE 1 730 #define PCI_DMA_FROMDEVICE 2 731 #define PCI_DMA_NONE 3 732 733 #define pci_pool dma_pool 734 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 735 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 736 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 737 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 738 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 739 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 740 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 741 _size, _vaddr, _dma_handle) 742 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 743 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 744 _sg, _nents, (enum dma_data_direction)_dir) 745 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 746 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 747 (_ptr), (_size), (enum dma_data_direction)_dir) 748 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 749 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 750 _addr, _size, (enum dma_data_direction)_dir) 751 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 752 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 753 _sg, _nents, (enum dma_data_direction)_dir) 754 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 755 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 756 _offset, _size, (enum dma_data_direction)_dir) 757 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 758 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 759 _dma_address, _size, (enum dma_data_direction)_dir) 760 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 761 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 762 dma_mapping_error(&(_pdev)->dev, _dma_addr) 763 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 764 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 765 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 766 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 767 #define pci_unmap_addr dma_unmap_addr 768 #define pci_unmap_addr_set dma_unmap_addr_set 769 #define pci_unmap_len dma_unmap_len 770 #define pci_unmap_len_set dma_unmap_len_set 771 772 typedef unsigned int __bitwise pci_channel_state_t; 773 typedef unsigned int __bitwise pci_ers_result_t; 774 775 enum pci_channel_state { 776 pci_channel_io_normal = 1, 777 pci_channel_io_frozen = 2, 778 pci_channel_io_perm_failure = 3, 779 }; 780 781 enum pci_ers_result { 782 PCI_ERS_RESULT_NONE = 1, 783 PCI_ERS_RESULT_CAN_RECOVER = 2, 784 PCI_ERS_RESULT_NEED_RESET = 3, 785 PCI_ERS_RESULT_DISCONNECT = 4, 786 PCI_ERS_RESULT_RECOVERED = 5, 787 }; 788 789 /* PCI bus error event callbacks */ 790 struct pci_error_handlers { 791 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 792 enum pci_channel_state error); 793 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 794 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 795 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 796 void (*resume)(struct pci_dev *dev); 797 }; 798 799 /* FreeBSD does not support SRIOV - yet */ 800 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 801 { 802 return dev; 803 } 804 805 static inline bool pci_is_pcie(struct pci_dev *dev) 806 { 807 return !!pci_pcie_cap(dev); 808 } 809 810 static inline u16 pcie_flags_reg(struct pci_dev *dev) 811 { 812 int pos; 813 u16 reg16; 814 815 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 816 if (!pos) 817 return 0; 818 819 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 820 821 return reg16; 822 } 823 824 static inline int pci_pcie_type(struct pci_dev *dev) 825 { 826 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 827 } 828 829 static inline int pcie_cap_version(struct pci_dev *dev) 830 { 831 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 832 } 833 834 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 835 { 836 int type = pci_pcie_type(dev); 837 838 return pcie_cap_version(dev) > 1 || 839 type == PCI_EXP_TYPE_ROOT_PORT || 840 type == PCI_EXP_TYPE_ENDPOINT || 841 type == PCI_EXP_TYPE_LEG_END; 842 } 843 844 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 845 { 846 return true; 847 } 848 849 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 850 { 851 int type = pci_pcie_type(dev); 852 853 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 854 (type == PCI_EXP_TYPE_DOWNSTREAM && 855 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 856 } 857 858 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 859 { 860 int type = pci_pcie_type(dev); 861 862 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 863 type == PCI_EXP_TYPE_RC_EC; 864 } 865 866 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 867 { 868 if (!pci_is_pcie(dev)) 869 return false; 870 871 switch (pos) { 872 case PCI_EXP_FLAGS_TYPE: 873 return true; 874 case PCI_EXP_DEVCAP: 875 case PCI_EXP_DEVCTL: 876 case PCI_EXP_DEVSTA: 877 return pcie_cap_has_devctl(dev); 878 case PCI_EXP_LNKCAP: 879 case PCI_EXP_LNKCTL: 880 case PCI_EXP_LNKSTA: 881 return pcie_cap_has_lnkctl(dev); 882 case PCI_EXP_SLTCAP: 883 case PCI_EXP_SLTCTL: 884 case PCI_EXP_SLTSTA: 885 return pcie_cap_has_sltctl(dev); 886 case PCI_EXP_RTCTL: 887 case PCI_EXP_RTCAP: 888 case PCI_EXP_RTSTA: 889 return pcie_cap_has_rtctl(dev); 890 case PCI_EXP_DEVCAP2: 891 case PCI_EXP_DEVCTL2: 892 case PCI_EXP_LNKCAP2: 893 case PCI_EXP_LNKCTL2: 894 case PCI_EXP_LNKSTA2: 895 return pcie_cap_version(dev) > 1; 896 default: 897 return false; 898 } 899 } 900 901 static inline int 902 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 903 { 904 if (pos & 3) 905 return -EINVAL; 906 907 if (!pcie_capability_reg_implemented(dev, pos)) 908 return -EINVAL; 909 910 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 911 } 912 913 static inline int 914 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 915 { 916 if (pos & 3) 917 return -EINVAL; 918 919 if (!pcie_capability_reg_implemented(dev, pos)) 920 return -EINVAL; 921 922 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 923 } 924 925 static inline int 926 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 927 { 928 if (pos & 1) 929 return -EINVAL; 930 931 if (!pcie_capability_reg_implemented(dev, pos)) 932 return 0; 933 934 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 935 } 936 937 static inline int pcie_get_minimum_link(struct pci_dev *dev, 938 enum pci_bus_speed *speed, enum pcie_link_width *width) 939 { 940 *speed = PCI_SPEED_UNKNOWN; 941 *width = PCIE_LNK_WIDTH_UNKNOWN; 942 return (0); 943 } 944 945 static inline int 946 pci_num_vf(struct pci_dev *dev) 947 { 948 return (0); 949 } 950 951 static inline enum pci_bus_speed 952 pcie_get_speed_cap(struct pci_dev *dev) 953 { 954 device_t root; 955 uint32_t lnkcap, lnkcap2; 956 int error, pos; 957 958 root = device_get_parent(dev->dev.bsddev); 959 if (root == NULL) 960 return (PCI_SPEED_UNKNOWN); 961 root = device_get_parent(root); 962 if (root == NULL) 963 return (PCI_SPEED_UNKNOWN); 964 root = device_get_parent(root); 965 if (root == NULL) 966 return (PCI_SPEED_UNKNOWN); 967 968 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 969 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 970 return (PCI_SPEED_UNKNOWN); 971 972 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 973 return (PCI_SPEED_UNKNOWN); 974 975 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 976 977 if (lnkcap2) { /* PCIe r3.0-compliant */ 978 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 979 return (PCIE_SPEED_2_5GT); 980 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 981 return (PCIE_SPEED_5_0GT); 982 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 983 return (PCIE_SPEED_8_0GT); 984 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 985 return (PCIE_SPEED_16_0GT); 986 } else { /* pre-r3.0 */ 987 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 988 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 989 return (PCIE_SPEED_2_5GT); 990 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 991 return (PCIE_SPEED_5_0GT); 992 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 993 return (PCIE_SPEED_8_0GT); 994 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 995 return (PCIE_SPEED_16_0GT); 996 } 997 return (PCI_SPEED_UNKNOWN); 998 } 999 1000 static inline enum pcie_link_width 1001 pcie_get_width_cap(struct pci_dev *dev) 1002 { 1003 uint32_t lnkcap; 1004 1005 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1006 if (lnkcap) 1007 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1008 1009 return (PCIE_LNK_WIDTH_UNKNOWN); 1010 } 1011 1012 static inline int 1013 pcie_get_mps(struct pci_dev *dev) 1014 { 1015 return (pci_get_max_payload(dev->dev.bsddev)); 1016 } 1017 1018 static inline uint32_t 1019 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1020 { 1021 1022 switch(spd) { 1023 case PCIE_SPEED_16_0GT: 1024 return (16000 * 128 / 130); 1025 case PCIE_SPEED_8_0GT: 1026 return (8000 * 128 / 130); 1027 case PCIE_SPEED_5_0GT: 1028 return (5000 * 8 / 10); 1029 case PCIE_SPEED_2_5GT: 1030 return (2500 * 8 / 10); 1031 default: 1032 return (0); 1033 } 1034 } 1035 1036 static inline uint32_t 1037 pcie_bandwidth_available(struct pci_dev *pdev, 1038 struct pci_dev **limiting, 1039 enum pci_bus_speed *speed, 1040 enum pcie_link_width *width) 1041 { 1042 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1043 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1044 1045 if (speed) 1046 *speed = nspeed; 1047 if (width) 1048 *width = nwidth; 1049 1050 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1051 } 1052 1053 /* 1054 * The following functions can be used to attach/detach the LinuxKPI's 1055 * PCI device runtime. The pci_driver and pci_device_id pointer is 1056 * allowed to be NULL. Other pointers must be all valid. 1057 * The pci_dev structure should be zero-initialized before passed 1058 * to the linux_pci_attach_device function. 1059 */ 1060 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1061 const struct pci_device_id *, struct pci_dev *); 1062 extern int linux_pci_detach_device(struct pci_dev *); 1063 1064 static inline int 1065 pci_dev_present(const struct pci_device_id *cur) 1066 { 1067 while (cur != NULL && (cur->vendor || cur->device)) { 1068 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1069 return (1); 1070 } 1071 cur++; 1072 } 1073 return (0); 1074 } 1075 1076 static inline bool 1077 pci_is_root_bus(struct pci_bus *pbus) 1078 { 1079 1080 return (pbus->self == NULL); 1081 } 1082 1083 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1084 unsigned int bus, unsigned int devfn); 1085 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1086 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1087 1088 static inline int 1089 pci_domain_nr(struct pci_bus *pbus) 1090 { 1091 1092 return (pbus->domain); 1093 } 1094 1095 static inline int 1096 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1097 int pos, uint32_t *val, int len) 1098 { 1099 1100 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1101 return (0); 1102 } 1103 1104 static inline int 1105 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1106 { 1107 uint32_t tmp; 1108 int ret; 1109 1110 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1111 *val = (u16)tmp; 1112 return (ret); 1113 } 1114 1115 static inline int 1116 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1117 { 1118 uint32_t tmp; 1119 int ret; 1120 1121 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1122 *val = (u8)tmp; 1123 return (ret); 1124 } 1125 1126 static inline int 1127 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1128 uint32_t val, int size) 1129 { 1130 1131 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1132 return (0); 1133 } 1134 1135 static inline int 1136 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1137 uint8_t val) 1138 { 1139 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1140 } 1141 1142 static inline int 1143 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1144 uint16_t val) 1145 { 1146 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1147 } 1148 1149 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1150 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1151 1152 #endif /* _LINUX_PCI_H_ */ 1153