1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUX_PCI_H_ 36 #define _LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <sys/rman.h> 47 #include <sys/bus.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 #define MODULE_DEVICE_TABLE(bus, table) 74 75 #define PCI_ANY_ID -1U 76 77 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 78 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 79 #define PCI_FUNC(devfn) ((devfn) & 0x07) 80 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 81 82 #define PCI_VDEVICE(_vendor, _device) \ 83 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 84 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 85 #define PCI_DEVICE(_vendor, _device) \ 86 .vendor = (_vendor), .device = (_device), \ 87 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 88 89 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 90 91 #define PCI_VENDOR_ID PCIR_DEVVENDOR 92 #define PCI_COMMAND PCIR_COMMAND 93 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 94 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 95 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 96 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 97 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 98 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 99 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 100 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 101 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 102 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 103 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 104 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 105 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 106 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 107 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 108 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 109 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 110 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 111 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 112 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 113 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 114 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 115 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 116 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 117 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 118 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 119 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 120 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 121 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 122 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 123 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 124 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 125 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 126 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 127 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 128 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 129 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 130 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 131 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 132 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 133 #define PCI_EXP_LNKCTL2_TLS 0x000f 134 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 135 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 136 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 137 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 138 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 139 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 140 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 141 142 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 143 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 144 #define PCI_EXP_DEVSTA_TRPND 0x0020 145 146 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 147 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 148 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 149 150 enum pci_bus_speed { 151 PCI_SPEED_UNKNOWN = -1, 152 PCIE_SPEED_2_5GT, 153 PCIE_SPEED_5_0GT, 154 PCIE_SPEED_8_0GT, 155 PCIE_SPEED_16_0GT, 156 }; 157 158 enum pcie_link_width { 159 PCIE_LNK_WIDTH_RESRV = 0x00, 160 PCIE_LNK_X1 = 0x01, 161 PCIE_LNK_X2 = 0x02, 162 PCIE_LNK_X4 = 0x04, 163 PCIE_LNK_X8 = 0x08, 164 PCIE_LNK_X12 = 0x0c, 165 PCIE_LNK_X16 = 0x10, 166 PCIE_LNK_X32 = 0x20, 167 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 168 }; 169 170 #define PCIE_LINK_STATE_L0S 0x00000001 171 #define PCIE_LINK_STATE_L1 0x00000002 172 #define PCIE_LINK_STATE_CLKPM 0x00000004 173 174 typedef int pci_power_t; 175 176 #define PCI_D0 PCI_POWERSTATE_D0 177 #define PCI_D1 PCI_POWERSTATE_D1 178 #define PCI_D2 PCI_POWERSTATE_D2 179 #define PCI_D3hot PCI_POWERSTATE_D3 180 #define PCI_D3cold 4 181 182 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 183 184 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 185 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 186 187 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 188 189 #define PCI_IRQ_LEGACY 0x01 190 #define PCI_IRQ_MSI 0x02 191 #define PCI_IRQ_MSIX 0x04 192 193 struct pci_dev; 194 195 struct pci_driver { 196 struct list_head links; 197 char *name; 198 const struct pci_device_id *id_table; 199 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 200 void (*remove)(struct pci_dev *dev); 201 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 202 int (*resume) (struct pci_dev *dev); /* Device woken up */ 203 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 204 driver_t bsddriver; 205 devclass_t bsdclass; 206 struct device_driver driver; 207 const struct pci_error_handlers *err_handler; 208 bool isdrm; 209 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 210 const nvlist_t *pf_config); 211 void (*bsd_iov_uninit)(device_t dev); 212 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 213 const nvlist_t *vf_config); 214 }; 215 216 struct pci_bus { 217 struct pci_dev *self; 218 int domain; 219 int number; 220 }; 221 222 extern struct list_head pci_drivers; 223 extern struct list_head pci_devices; 224 extern spinlock_t pci_lock; 225 226 #define __devexit_p(x) x 227 228 #define module_pci_driver(_driver) \ 229 \ 230 static inline int \ 231 _pci_init(void) \ 232 { \ 233 \ 234 return (linux_pci_register_driver(&_driver)); \ 235 } \ 236 \ 237 static inline void \ 238 _pci_exit(void) \ 239 { \ 240 \ 241 linux_pci_unregister_driver(&_driver); \ 242 } \ 243 \ 244 module_init(_pci_init); \ 245 module_exit(_pci_exit) 246 247 /* 248 * If we find drivers accessing this from multiple KPIs we may have to 249 * refcount objects of this structure. 250 */ 251 struct pci_mmio_region { 252 TAILQ_ENTRY(pci_mmio_region) next; 253 struct resource *res; 254 int rid; 255 int type; 256 }; 257 258 struct pci_dev { 259 struct device dev; 260 struct list_head links; 261 struct pci_driver *pdrv; 262 struct pci_bus *bus; 263 struct pci_dev *root; 264 uint16_t device; 265 uint16_t vendor; 266 uint16_t subsystem_vendor; 267 uint16_t subsystem_device; 268 unsigned int irq; 269 unsigned int devfn; 270 uint32_t class; 271 uint8_t revision; 272 bool managed; /* devres "pcim_*(). */ 273 bool want_iomap_res; 274 bool msi_enabled; 275 bool msix_enabled; 276 phys_addr_t rom; 277 size_t romlen; 278 279 TAILQ_HEAD(, pci_mmio_region) mmio; 280 }; 281 282 /* We need some meta-struct to keep track of these for devres. */ 283 struct pci_devres { 284 bool enable_io; 285 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 286 uint8_t region_mask; 287 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 288 }; 289 struct pcim_iomap_devres { 290 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 291 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 292 }; 293 294 /* Internal helper function(s). */ 295 struct pci_dev *lkpinew_pci_dev(device_t); 296 void lkpi_pci_devres_release(struct device *, void *); 297 void lkpi_pcim_iomap_table_release(struct device *, void *); 298 299 static inline int 300 pci_resource_type(struct pci_dev *pdev, int bar) 301 { 302 struct pci_map *pm; 303 304 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 305 if (!pm) 306 return (-1); 307 308 if (PCI_BAR_IO(pm->pm_value)) 309 return (SYS_RES_IOPORT); 310 else 311 return (SYS_RES_MEMORY); 312 } 313 314 static inline struct resource_list_entry * 315 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 316 { 317 struct pci_devinfo *dinfo; 318 struct resource_list *rl; 319 320 dinfo = device_get_ivars(pdev->dev.bsddev); 321 rl = &dinfo->resources; 322 return resource_list_find(rl, type, rid); 323 } 324 325 static inline struct resource_list_entry * 326 linux_pci_get_bar(struct pci_dev *pdev, int bar) 327 { 328 int type; 329 330 type = pci_resource_type(pdev, bar); 331 if (type < 0) 332 return (NULL); 333 bar = PCIR_BAR(bar); 334 return (linux_pci_get_rle(pdev, type, bar)); 335 } 336 337 static inline struct device * 338 linux_pci_find_irq_dev(unsigned int irq) 339 { 340 struct pci_dev *pdev; 341 struct device *found; 342 343 found = NULL; 344 spin_lock(&pci_lock); 345 list_for_each_entry(pdev, &pci_devices, links) { 346 if (irq == pdev->dev.irq || 347 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 348 found = &pdev->dev; 349 break; 350 } 351 } 352 spin_unlock(&pci_lock); 353 return (found); 354 } 355 356 /* 357 * All drivers just seem to want to inspect the type not flags. 358 */ 359 static inline int 360 pci_resource_flags(struct pci_dev *pdev, int bar) 361 { 362 int type; 363 364 type = pci_resource_type(pdev, bar); 365 if (type < 0) 366 return (0); 367 return (1 << type); 368 } 369 370 static inline const char * 371 pci_name(struct pci_dev *d) 372 { 373 374 return device_get_desc(d->dev.bsddev); 375 } 376 377 static inline void * 378 pci_get_drvdata(struct pci_dev *pdev) 379 { 380 381 return dev_get_drvdata(&pdev->dev); 382 } 383 384 static inline void 385 pci_set_drvdata(struct pci_dev *pdev, void *data) 386 { 387 388 dev_set_drvdata(&pdev->dev, data); 389 } 390 391 static inline struct pci_dev * 392 pci_dev_get(struct pci_dev *pdev) 393 { 394 395 if (pdev != NULL) 396 get_device(&pdev->dev); 397 return (pdev); 398 } 399 400 static __inline void 401 pci_dev_put(struct pci_dev *pdev) 402 { 403 404 if (pdev != NULL) 405 put_device(&pdev->dev); 406 } 407 408 static inline int 409 pci_enable_device(struct pci_dev *pdev) 410 { 411 412 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 413 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 414 return (0); 415 } 416 417 static inline void 418 pci_disable_device(struct pci_dev *pdev) 419 { 420 421 pci_disable_busmaster(pdev->dev.bsddev); 422 } 423 424 static inline int 425 pci_set_master(struct pci_dev *pdev) 426 { 427 428 pci_enable_busmaster(pdev->dev.bsddev); 429 return (0); 430 } 431 432 static inline int 433 pci_set_power_state(struct pci_dev *pdev, int state) 434 { 435 436 pci_set_powerstate(pdev->dev.bsddev, state); 437 return (0); 438 } 439 440 static inline int 441 pci_clear_master(struct pci_dev *pdev) 442 { 443 444 pci_disable_busmaster(pdev->dev.bsddev); 445 return (0); 446 } 447 448 static inline struct pci_devres * 449 lkpi_pci_devres_get_alloc(struct pci_dev *pdev) 450 { 451 struct pci_devres *dr; 452 453 dr = lkpi_devres_find(&pdev->dev, lkpi_pci_devres_release, NULL, NULL); 454 if (dr == NULL) { 455 dr = lkpi_devres_alloc(lkpi_pci_devres_release, sizeof(*dr), 456 GFP_KERNEL | __GFP_ZERO); 457 if (dr != NULL) 458 lkpi_devres_add(&pdev->dev, dr); 459 } 460 461 return (dr); 462 } 463 static inline struct pci_devres * 464 lkpi_pci_devres_find(struct pci_dev *pdev) 465 { 466 467 if (!pdev->managed) 468 return (NULL); 469 470 return (lkpi_pci_devres_get_alloc(pdev)); 471 } 472 473 static inline int 474 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 475 { 476 struct resource *res; 477 struct pci_devres *dr; 478 struct pci_mmio_region *mmio; 479 int rid; 480 int type; 481 482 type = pci_resource_type(pdev, bar); 483 if (type < 0) 484 return (-ENODEV); 485 rid = PCIR_BAR(bar); 486 res = bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 487 RF_ACTIVE|RF_SHAREABLE); 488 if (res == NULL) { 489 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 490 "bar %d type %d rid %d\n", 491 __func__, bar, type, PCIR_BAR(bar)); 492 return (-ENODEV); 493 } 494 495 /* 496 * It seems there is an implicit devres tracking on these if the device 497 * is managed; otherwise the resources are not automatiaclly freed on 498 * FreeBSD/LinuxKPI tough they should be/are expected to be by Linux 499 * drivers. 500 */ 501 dr = lkpi_pci_devres_find(pdev); 502 if (dr != NULL) { 503 dr->region_mask |= (1 << bar); 504 dr->region_table[bar] = res; 505 } 506 507 /* Even if the device is not managed we need to track it for iomap. */ 508 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 509 mmio->rid = PCIR_BAR(bar); 510 mmio->type = type; 511 mmio->res = res; 512 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 513 514 return (0); 515 } 516 517 static inline void 518 pci_release_region(struct pci_dev *pdev, int bar) 519 { 520 struct resource_list_entry *rle; 521 struct pci_devres *dr; 522 struct pci_mmio_region *mmio, *p; 523 524 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 525 return; 526 527 /* 528 * As we implicitly track the requests we also need to clear them on 529 * release. Do clear before resource release. 530 */ 531 dr = lkpi_pci_devres_find(pdev); 532 if (dr != NULL) { 533 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 534 " region_table res %p != rel->res %p\n", __func__, pdev, 535 bar, dr->region_table[bar], rle->res)); 536 dr->region_table[bar] = NULL; 537 dr->region_mask &= ~(1 << bar); 538 } 539 540 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 541 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 542 continue; 543 TAILQ_REMOVE(&pdev->mmio, mmio, next); 544 free(mmio, M_DEVBUF); 545 } 546 547 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 548 } 549 550 static inline void 551 pci_release_regions(struct pci_dev *pdev) 552 { 553 int i; 554 555 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 556 pci_release_region(pdev, i); 557 } 558 559 static inline int 560 pci_request_regions(struct pci_dev *pdev, const char *res_name) 561 { 562 int error; 563 int i; 564 565 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 566 error = pci_request_region(pdev, i, res_name); 567 if (error && error != -ENODEV) { 568 pci_release_regions(pdev); 569 return (error); 570 } 571 } 572 return (0); 573 } 574 575 static inline void 576 lkpi_pci_disable_msix(struct pci_dev *pdev) 577 { 578 579 pci_release_msi(pdev->dev.bsddev); 580 581 /* 582 * The MSIX IRQ numbers associated with this PCI device are no 583 * longer valid and might be re-assigned. Make sure 584 * linux_pci_find_irq_dev() does no longer see them by 585 * resetting their references to zero: 586 */ 587 pdev->dev.irq_start = 0; 588 pdev->dev.irq_end = 0; 589 pdev->msix_enabled = false; 590 } 591 /* Only for consistency. No conflict on that one. */ 592 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 593 594 static inline void 595 lkpi_pci_disable_msi(struct pci_dev *pdev) 596 { 597 598 pci_release_msi(pdev->dev.bsddev); 599 600 pdev->dev.irq_start = 0; 601 pdev->dev.irq_end = 0; 602 pdev->irq = pdev->dev.irq; 603 pdev->msi_enabled = false; 604 } 605 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 606 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 607 608 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 609 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 610 611 static inline bus_addr_t 612 pci_bus_address(struct pci_dev *pdev, int bar) 613 { 614 615 return (pci_resource_start(pdev, bar)); 616 } 617 618 #define PCI_CAP_ID_EXP PCIY_EXPRESS 619 #define PCI_CAP_ID_PCIX PCIY_PCIX 620 #define PCI_CAP_ID_AGP PCIY_AGP 621 #define PCI_CAP_ID_PM PCIY_PMG 622 623 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 624 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 625 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 626 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 627 #define PCI_EXP_LNKSTA PCIER_LINK_STA 628 629 static inline int 630 pci_find_capability(struct pci_dev *pdev, int capid) 631 { 632 int reg; 633 634 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 635 return (0); 636 return (reg); 637 } 638 639 static inline int pci_pcie_cap(struct pci_dev *dev) 640 { 641 return pci_find_capability(dev, PCI_CAP_ID_EXP); 642 } 643 644 static inline int 645 pci_find_ext_capability(struct pci_dev *pdev, int capid) 646 { 647 int reg; 648 649 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 650 return (0); 651 return (reg); 652 } 653 654 #define PCIM_PCAP_PME_SHIFT 11 655 static __inline bool 656 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 657 { 658 struct pci_devinfo *dinfo; 659 pcicfgregs *cfg; 660 661 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 662 return (false); 663 664 dinfo = device_get_ivars(pdev->dev.bsddev); 665 cfg = &dinfo->cfg; 666 667 if (cfg->pp.pp_cap == 0) 668 return (false); 669 670 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 671 return (true); 672 673 return (false); 674 } 675 676 static inline int 677 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 678 { 679 680 if (!pci_enable_aspm) 681 return (-EPERM); 682 683 return (-ENXIO); 684 } 685 686 static inline int 687 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 688 { 689 690 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 691 return (0); 692 } 693 694 static inline int 695 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 696 { 697 698 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 699 return (0); 700 } 701 702 static inline int 703 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 704 { 705 706 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 707 return (0); 708 } 709 710 static inline int 711 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 712 { 713 714 pci_write_config(pdev->dev.bsddev, where, val, 1); 715 return (0); 716 } 717 718 static inline int 719 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 720 { 721 722 pci_write_config(pdev->dev.bsddev, where, val, 2); 723 return (0); 724 } 725 726 static inline int 727 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 728 { 729 730 pci_write_config(pdev->dev.bsddev, where, val, 4); 731 return (0); 732 } 733 734 int linux_pci_register_driver(struct pci_driver *pdrv); 735 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 736 void linux_pci_unregister_driver(struct pci_driver *pdrv); 737 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 738 739 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 740 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 741 742 struct msix_entry { 743 int entry; 744 int vector; 745 }; 746 747 /* 748 * Enable msix, positive errors indicate actual number of available 749 * vectors. Negative errors are failures. 750 * 751 * NB: define added to prevent this definition of pci_enable_msix from 752 * clashing with the native FreeBSD version. 753 */ 754 #define pci_enable_msix(...) \ 755 linux_pci_enable_msix(__VA_ARGS__) 756 757 static inline int 758 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 759 { 760 struct resource_list_entry *rle; 761 int error; 762 int avail; 763 int i; 764 765 avail = pci_msix_count(pdev->dev.bsddev); 766 if (avail < nreq) { 767 if (avail == 0) 768 return -EINVAL; 769 return avail; 770 } 771 avail = nreq; 772 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 773 return error; 774 /* 775 * Handle case where "pci_alloc_msix()" may allocate less 776 * interrupts than available and return with no error: 777 */ 778 if (avail < nreq) { 779 pci_release_msi(pdev->dev.bsddev); 780 return avail; 781 } 782 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 783 pdev->dev.irq_start = rle->start; 784 pdev->dev.irq_end = rle->start + avail; 785 for (i = 0; i < nreq; i++) 786 entries[i].vector = pdev->dev.irq_start + i; 787 pdev->msix_enabled = true; 788 return (0); 789 } 790 791 #define pci_enable_msix_range(...) \ 792 linux_pci_enable_msix_range(__VA_ARGS__) 793 794 static inline int 795 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 796 int minvec, int maxvec) 797 { 798 int nvec = maxvec; 799 int rc; 800 801 if (maxvec < minvec) 802 return (-ERANGE); 803 804 do { 805 rc = pci_enable_msix(dev, entries, nvec); 806 if (rc < 0) { 807 return (rc); 808 } else if (rc > 0) { 809 if (rc < minvec) 810 return (-ENOSPC); 811 nvec = rc; 812 } 813 } while (rc); 814 return (nvec); 815 } 816 817 #define pci_enable_msi(pdev) \ 818 linux_pci_enable_msi(pdev) 819 820 static inline int 821 pci_enable_msi(struct pci_dev *pdev) 822 { 823 struct resource_list_entry *rle; 824 int error; 825 int avail; 826 827 avail = pci_msi_count(pdev->dev.bsddev); 828 if (avail < 1) 829 return -EINVAL; 830 831 avail = 1; /* this function only enable one MSI IRQ */ 832 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 833 return error; 834 835 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 836 pdev->dev.irq_start = rle->start; 837 pdev->dev.irq_end = rle->start + avail; 838 pdev->irq = rle->start; 839 pdev->msi_enabled = true; 840 return (0); 841 } 842 843 static inline int 844 pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 845 unsigned int flags) 846 { 847 int error; 848 849 if (flags & PCI_IRQ_MSIX) { 850 struct msix_entry *entries; 851 int i; 852 853 entries = kcalloc(maxv, sizeof(*entries), GFP_KERNEL); 854 if (entries == NULL) { 855 error = -ENOMEM; 856 goto out; 857 } 858 for (i = 0; i < maxv; ++i) 859 entries[i].entry = i; 860 error = pci_enable_msix(pdev, entries, maxv); 861 out: 862 kfree(entries); 863 if (error == 0 && pdev->msix_enabled) 864 return (pdev->dev.irq_end - pdev->dev.irq_start); 865 } 866 if (flags & PCI_IRQ_MSI) { 867 error = pci_enable_msi(pdev); 868 if (error == 0 && pdev->msi_enabled) 869 return (pdev->dev.irq_end - pdev->dev.irq_start); 870 } 871 if (flags & PCI_IRQ_LEGACY) { 872 if (pdev->irq) 873 return (1); 874 } 875 876 return (-EINVAL); 877 } 878 879 static inline int 880 pci_channel_offline(struct pci_dev *pdev) 881 { 882 883 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 884 } 885 886 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 887 { 888 return -ENODEV; 889 } 890 static inline void pci_disable_sriov(struct pci_dev *dev) 891 { 892 } 893 894 static inline struct resource * 895 _lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size __unused) 896 { 897 struct pci_mmio_region *mmio, *p; 898 int type; 899 900 type = pci_resource_type(pdev, bar); 901 if (type < 0) { 902 device_printf(pdev->dev.bsddev, "%s: bar %d type %d\n", 903 __func__, bar, type); 904 return (NULL); 905 } 906 907 /* 908 * Check for duplicate mappings. 909 * This can happen if a driver calls pci_request_region() first. 910 */ 911 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 912 if (mmio->type == type && mmio->rid == PCIR_BAR(bar)) { 913 return (mmio->res); 914 } 915 } 916 917 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 918 mmio->rid = PCIR_BAR(bar); 919 mmio->type = type; 920 mmio->res = bus_alloc_resource_any(pdev->dev.bsddev, mmio->type, 921 &mmio->rid, RF_ACTIVE|RF_SHAREABLE); 922 if (mmio->res == NULL) { 923 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 924 "bar %d type %d rid %d\n", 925 __func__, bar, type, PCIR_BAR(bar)); 926 free(mmio, M_DEVBUF); 927 return (NULL); 928 } 929 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 930 931 return (mmio->res); 932 } 933 934 static inline void * 935 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 936 { 937 struct resource *res; 938 939 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 940 if (res == NULL) 941 return (NULL); 942 /* This is a FreeBSD extension so we can use bus_*(). */ 943 if (pdev->want_iomap_res) 944 return (res); 945 return ((void *)rman_get_bushandle(res)); 946 } 947 948 static inline void 949 pci_iounmap(struct pci_dev *pdev, void *res) 950 { 951 struct pci_mmio_region *mmio, *p; 952 953 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 954 if (res != (void *)rman_get_bushandle(mmio->res)) 955 continue; 956 bus_release_resource(pdev->dev.bsddev, 957 mmio->type, mmio->rid, mmio->res); 958 TAILQ_REMOVE(&pdev->mmio, mmio, next); 959 free(mmio, M_DEVBUF); 960 return; 961 } 962 } 963 964 static inline void 965 lkpi_pci_save_state(struct pci_dev *pdev) 966 { 967 968 pci_save_state(pdev->dev.bsddev); 969 } 970 971 static inline void 972 lkpi_pci_restore_state(struct pci_dev *pdev) 973 { 974 975 pci_restore_state(pdev->dev.bsddev); 976 } 977 978 #define pci_save_state(dev) lkpi_pci_save_state(dev) 979 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 980 981 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 982 const struct pci_device_id _table[] __devinitdata 983 984 /* XXX This should not be necessary. */ 985 #define pcix_set_mmrbc(d, v) 0 986 #define pcix_get_max_mmrbc(d) 0 987 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 988 989 #define PCI_DMA_BIDIRECTIONAL 0 990 #define PCI_DMA_TODEVICE 1 991 #define PCI_DMA_FROMDEVICE 2 992 #define PCI_DMA_NONE 3 993 994 #define pci_pool dma_pool 995 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 996 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 997 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 998 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 999 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 1000 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 1001 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1002 _size, _vaddr, _dma_handle) 1003 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 1004 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1005 _sg, _nents, (enum dma_data_direction)_dir) 1006 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 1007 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1008 (_ptr), (_size), (enum dma_data_direction)_dir) 1009 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 1010 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1011 _addr, _size, (enum dma_data_direction)_dir) 1012 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 1013 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1014 _sg, _nents, (enum dma_data_direction)_dir) 1015 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 1016 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 1017 _offset, _size, (enum dma_data_direction)_dir) 1018 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 1019 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1020 _dma_address, _size, (enum dma_data_direction)_dir) 1021 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1022 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1023 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1024 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1025 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1026 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1027 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1028 #define pci_unmap_addr dma_unmap_addr 1029 #define pci_unmap_addr_set dma_unmap_addr_set 1030 #define pci_unmap_len dma_unmap_len 1031 #define pci_unmap_len_set dma_unmap_len_set 1032 1033 typedef unsigned int __bitwise pci_channel_state_t; 1034 typedef unsigned int __bitwise pci_ers_result_t; 1035 1036 enum pci_channel_state { 1037 pci_channel_io_normal = 1, 1038 pci_channel_io_frozen = 2, 1039 pci_channel_io_perm_failure = 3, 1040 }; 1041 1042 enum pci_ers_result { 1043 PCI_ERS_RESULT_NONE = 1, 1044 PCI_ERS_RESULT_CAN_RECOVER = 2, 1045 PCI_ERS_RESULT_NEED_RESET = 3, 1046 PCI_ERS_RESULT_DISCONNECT = 4, 1047 PCI_ERS_RESULT_RECOVERED = 5, 1048 }; 1049 1050 /* PCI bus error event callbacks */ 1051 struct pci_error_handlers { 1052 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1053 enum pci_channel_state error); 1054 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1055 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1056 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1057 void (*resume)(struct pci_dev *dev); 1058 }; 1059 1060 /* FreeBSD does not support SRIOV - yet */ 1061 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1062 { 1063 return dev; 1064 } 1065 1066 static inline bool pci_is_pcie(struct pci_dev *dev) 1067 { 1068 return !!pci_pcie_cap(dev); 1069 } 1070 1071 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1072 { 1073 int pos; 1074 u16 reg16; 1075 1076 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1077 if (!pos) 1078 return 0; 1079 1080 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1081 1082 return reg16; 1083 } 1084 1085 static inline int pci_pcie_type(struct pci_dev *dev) 1086 { 1087 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1088 } 1089 1090 static inline int pcie_cap_version(struct pci_dev *dev) 1091 { 1092 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1093 } 1094 1095 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1096 { 1097 int type = pci_pcie_type(dev); 1098 1099 return pcie_cap_version(dev) > 1 || 1100 type == PCI_EXP_TYPE_ROOT_PORT || 1101 type == PCI_EXP_TYPE_ENDPOINT || 1102 type == PCI_EXP_TYPE_LEG_END; 1103 } 1104 1105 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1106 { 1107 return true; 1108 } 1109 1110 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1111 { 1112 int type = pci_pcie_type(dev); 1113 1114 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1115 (type == PCI_EXP_TYPE_DOWNSTREAM && 1116 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1117 } 1118 1119 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1120 { 1121 int type = pci_pcie_type(dev); 1122 1123 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1124 type == PCI_EXP_TYPE_RC_EC; 1125 } 1126 1127 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1128 { 1129 if (!pci_is_pcie(dev)) 1130 return false; 1131 1132 switch (pos) { 1133 case PCI_EXP_FLAGS_TYPE: 1134 return true; 1135 case PCI_EXP_DEVCAP: 1136 case PCI_EXP_DEVCTL: 1137 case PCI_EXP_DEVSTA: 1138 return pcie_cap_has_devctl(dev); 1139 case PCI_EXP_LNKCAP: 1140 case PCI_EXP_LNKCTL: 1141 case PCI_EXP_LNKSTA: 1142 return pcie_cap_has_lnkctl(dev); 1143 case PCI_EXP_SLTCAP: 1144 case PCI_EXP_SLTCTL: 1145 case PCI_EXP_SLTSTA: 1146 return pcie_cap_has_sltctl(dev); 1147 case PCI_EXP_RTCTL: 1148 case PCI_EXP_RTCAP: 1149 case PCI_EXP_RTSTA: 1150 return pcie_cap_has_rtctl(dev); 1151 case PCI_EXP_DEVCAP2: 1152 case PCI_EXP_DEVCTL2: 1153 case PCI_EXP_LNKCAP2: 1154 case PCI_EXP_LNKCTL2: 1155 case PCI_EXP_LNKSTA2: 1156 return pcie_cap_version(dev) > 1; 1157 default: 1158 return false; 1159 } 1160 } 1161 1162 static inline int 1163 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1164 { 1165 if (pos & 3) 1166 return -EINVAL; 1167 1168 if (!pcie_capability_reg_implemented(dev, pos)) 1169 return -EINVAL; 1170 1171 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1172 } 1173 1174 static inline int 1175 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1176 { 1177 if (pos & 3) 1178 return -EINVAL; 1179 1180 if (!pcie_capability_reg_implemented(dev, pos)) 1181 return -EINVAL; 1182 1183 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1184 } 1185 1186 static inline int 1187 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1188 { 1189 if (pos & 1) 1190 return -EINVAL; 1191 1192 if (!pcie_capability_reg_implemented(dev, pos)) 1193 return 0; 1194 1195 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1196 } 1197 1198 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1199 enum pci_bus_speed *speed, enum pcie_link_width *width) 1200 { 1201 *speed = PCI_SPEED_UNKNOWN; 1202 *width = PCIE_LNK_WIDTH_UNKNOWN; 1203 return (0); 1204 } 1205 1206 static inline int 1207 pci_num_vf(struct pci_dev *dev) 1208 { 1209 return (0); 1210 } 1211 1212 static inline enum pci_bus_speed 1213 pcie_get_speed_cap(struct pci_dev *dev) 1214 { 1215 device_t root; 1216 uint32_t lnkcap, lnkcap2; 1217 int error, pos; 1218 1219 root = device_get_parent(dev->dev.bsddev); 1220 if (root == NULL) 1221 return (PCI_SPEED_UNKNOWN); 1222 root = device_get_parent(root); 1223 if (root == NULL) 1224 return (PCI_SPEED_UNKNOWN); 1225 root = device_get_parent(root); 1226 if (root == NULL) 1227 return (PCI_SPEED_UNKNOWN); 1228 1229 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1230 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1231 return (PCI_SPEED_UNKNOWN); 1232 1233 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1234 return (PCI_SPEED_UNKNOWN); 1235 1236 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1237 1238 if (lnkcap2) { /* PCIe r3.0-compliant */ 1239 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1240 return (PCIE_SPEED_2_5GT); 1241 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1242 return (PCIE_SPEED_5_0GT); 1243 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1244 return (PCIE_SPEED_8_0GT); 1245 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1246 return (PCIE_SPEED_16_0GT); 1247 } else { /* pre-r3.0 */ 1248 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1249 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1250 return (PCIE_SPEED_2_5GT); 1251 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1252 return (PCIE_SPEED_5_0GT); 1253 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1254 return (PCIE_SPEED_8_0GT); 1255 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1256 return (PCIE_SPEED_16_0GT); 1257 } 1258 return (PCI_SPEED_UNKNOWN); 1259 } 1260 1261 static inline enum pcie_link_width 1262 pcie_get_width_cap(struct pci_dev *dev) 1263 { 1264 uint32_t lnkcap; 1265 1266 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1267 if (lnkcap) 1268 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1269 1270 return (PCIE_LNK_WIDTH_UNKNOWN); 1271 } 1272 1273 static inline int 1274 pcie_get_mps(struct pci_dev *dev) 1275 { 1276 return (pci_get_max_payload(dev->dev.bsddev)); 1277 } 1278 1279 static inline uint32_t 1280 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1281 { 1282 1283 switch(spd) { 1284 case PCIE_SPEED_16_0GT: 1285 return (16000 * 128 / 130); 1286 case PCIE_SPEED_8_0GT: 1287 return (8000 * 128 / 130); 1288 case PCIE_SPEED_5_0GT: 1289 return (5000 * 8 / 10); 1290 case PCIE_SPEED_2_5GT: 1291 return (2500 * 8 / 10); 1292 default: 1293 return (0); 1294 } 1295 } 1296 1297 static inline uint32_t 1298 pcie_bandwidth_available(struct pci_dev *pdev, 1299 struct pci_dev **limiting, 1300 enum pci_bus_speed *speed, 1301 enum pcie_link_width *width) 1302 { 1303 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1304 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1305 1306 if (speed) 1307 *speed = nspeed; 1308 if (width) 1309 *width = nwidth; 1310 1311 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1312 } 1313 1314 static inline struct pci_dev * 1315 pcie_find_root_port(struct pci_dev *pdev) 1316 { 1317 device_t root; 1318 1319 if (pdev->root != NULL) 1320 return (pdev->root); 1321 1322 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1323 if (root == NULL) 1324 return (NULL); 1325 1326 pdev->root = lkpinew_pci_dev(root); 1327 return (pdev->root); 1328 } 1329 1330 /* This is needed when people rip out the device "HotPlug". */ 1331 static inline void 1332 pci_lock_rescan_remove(void) 1333 { 1334 } 1335 1336 static inline void 1337 pci_unlock_rescan_remove(void) 1338 { 1339 } 1340 1341 static __inline void 1342 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1343 { 1344 } 1345 1346 /* 1347 * The following functions can be used to attach/detach the LinuxKPI's 1348 * PCI device runtime. The pci_driver and pci_device_id pointer is 1349 * allowed to be NULL. Other pointers must be all valid. 1350 * The pci_dev structure should be zero-initialized before passed 1351 * to the linux_pci_attach_device function. 1352 */ 1353 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1354 const struct pci_device_id *, struct pci_dev *); 1355 extern int linux_pci_detach_device(struct pci_dev *); 1356 1357 static inline int 1358 pci_dev_present(const struct pci_device_id *cur) 1359 { 1360 while (cur != NULL && (cur->vendor || cur->device)) { 1361 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1362 return (1); 1363 } 1364 cur++; 1365 } 1366 return (0); 1367 } 1368 1369 static inline bool 1370 pci_is_root_bus(struct pci_bus *pbus) 1371 { 1372 1373 return (pbus->self == NULL); 1374 } 1375 1376 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1377 unsigned int bus, unsigned int devfn); 1378 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1379 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1380 1381 static inline int 1382 pci_domain_nr(struct pci_bus *pbus) 1383 { 1384 1385 return (pbus->domain); 1386 } 1387 1388 static inline int 1389 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1390 int pos, uint32_t *val, int len) 1391 { 1392 1393 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1394 return (0); 1395 } 1396 1397 static inline int 1398 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1399 { 1400 uint32_t tmp; 1401 int ret; 1402 1403 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1404 *val = (u16)tmp; 1405 return (ret); 1406 } 1407 1408 static inline int 1409 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1410 { 1411 uint32_t tmp; 1412 int ret; 1413 1414 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1415 *val = (u8)tmp; 1416 return (ret); 1417 } 1418 1419 static inline int 1420 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1421 uint32_t val, int size) 1422 { 1423 1424 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1425 return (0); 1426 } 1427 1428 static inline int 1429 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1430 uint8_t val) 1431 { 1432 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1433 } 1434 1435 static inline int 1436 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1437 uint16_t val) 1438 { 1439 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1440 } 1441 1442 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1443 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1444 1445 /* -------------------------------------------------------------------------- */ 1446 1447 static inline int 1448 pcim_enable_device(struct pci_dev *pdev) 1449 { 1450 struct pci_devres *dr; 1451 int error; 1452 1453 /* Here we cannot run through the pdev->managed check. */ 1454 dr = lkpi_pci_devres_get_alloc(pdev); 1455 if (dr == NULL) 1456 return (-ENOMEM); 1457 1458 /* If resources were enabled before do not do it again. */ 1459 if (dr->enable_io) 1460 return (0); 1461 1462 error = pci_enable_device(pdev); 1463 if (error == 0) 1464 dr->enable_io = true; 1465 1466 /* This device is not managed. */ 1467 pdev->managed = true; 1468 1469 return (error); 1470 } 1471 1472 static inline struct pcim_iomap_devres * 1473 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev) 1474 { 1475 struct pcim_iomap_devres *dr; 1476 1477 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release, 1478 NULL, NULL); 1479 if (dr == NULL) { 1480 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release, 1481 sizeof(*dr), GFP_KERNEL | __GFP_ZERO); 1482 if (dr != NULL) 1483 lkpi_devres_add(&pdev->dev, dr); 1484 } 1485 1486 if (dr == NULL) 1487 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__); 1488 1489 return (dr); 1490 } 1491 1492 static inline void __iomem ** 1493 pcim_iomap_table(struct pci_dev *pdev) 1494 { 1495 struct pcim_iomap_devres *dr; 1496 1497 dr = lkpi_pcim_iomap_devres_find(pdev); 1498 if (dr == NULL) 1499 return (NULL); 1500 1501 /* 1502 * If the driver has manually set a flag to be able to request the 1503 * resource to use bus_read/write_<n>, return the shadow table. 1504 */ 1505 if (pdev->want_iomap_res) 1506 return ((void **)dr->res_table); 1507 1508 /* This is the Linux default. */ 1509 return (dr->mmio_table); 1510 } 1511 1512 static inline int 1513 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1514 { 1515 struct pcim_iomap_devres *dr; 1516 void *res; 1517 uint32_t mappings, requests, req_mask; 1518 int bar, error; 1519 1520 dr = lkpi_pcim_iomap_devres_find(pdev); 1521 if (dr == NULL) 1522 return (-ENOMEM); 1523 1524 /* Request all the BARs ("regions") we do not iomap. */ 1525 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1526 for (bar = requests = 0; requests != req_mask; bar++) { 1527 if ((req_mask & (1 << bar)) == 0) 1528 continue; 1529 error = pci_request_region(pdev, bar, name); 1530 if (error != 0 && error != -ENODEV) 1531 goto err; 1532 requests |= (1 << bar); 1533 } 1534 1535 /* Now iomap all the requested (by "mask") ones. */ 1536 for (bar = mappings = 0; mappings != mask; bar++) { 1537 if ((mask & (1 << bar)) == 0) 1538 continue; 1539 1540 /* Request double is not allowed. */ 1541 if (dr->mmio_table[bar] != NULL) { 1542 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1543 __func__, bar, dr->mmio_table[bar]); 1544 goto err; 1545 } 1546 1547 res = _lkpi_pci_iomap(pdev, bar, 0); 1548 if (res == NULL) 1549 goto err; 1550 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1551 dr->res_table[bar] = res; 1552 1553 mappings |= (1 << bar); 1554 } 1555 1556 return (0); 1557 1558 err: 1559 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1560 if ((mappings & (1 << bar)) != 0) { 1561 res = dr->mmio_table[bar]; 1562 if (res == NULL) 1563 continue; 1564 pci_iounmap(pdev, res); 1565 } else if ((requests & (1 << bar)) != 0) { 1566 pci_release_region(pdev, bar); 1567 } 1568 } 1569 1570 return (-EINVAL); 1571 } 1572 1573 /* This is a FreeBSD extension so we can use bus_*(). */ 1574 static inline void 1575 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1576 { 1577 pdev->want_iomap_res = true; 1578 } 1579 1580 #endif /* _LINUX_PCI_H_ */ 1581