1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/nv.h> 41 #include <sys/pciio.h> 42 #include <sys/rman.h> 43 #include <sys/bus.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pci_private.h> 47 48 #include <machine/resource.h> 49 50 #include <linux/list.h> 51 #include <linux/dmapool.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/compiler.h> 54 #include <linux/errno.h> 55 #include <asm/atomic.h> 56 #include <linux/device.h> 57 58 struct pci_device_id { 59 uint32_t vendor; 60 uint32_t device; 61 uint32_t subvendor; 62 uint32_t subdevice; 63 uint32_t class; 64 uint32_t class_mask; 65 uintptr_t driver_data; 66 }; 67 68 #define MODULE_DEVICE_TABLE(bus, table) 69 70 #define PCI_BASE_CLASS_DISPLAY 0x03 71 #define PCI_CLASS_DISPLAY_VGA 0x0300 72 #define PCI_CLASS_DISPLAY_OTHER 0x0380 73 #define PCI_BASE_CLASS_BRIDGE 0x06 74 #define PCI_CLASS_BRIDGE_ISA 0x0601 75 76 #define PCI_ANY_ID -1U 77 #define PCI_VENDOR_ID_APPLE 0x106b 78 #define PCI_VENDOR_ID_ASUSTEK 0x1043 79 #define PCI_VENDOR_ID_ATI 0x1002 80 #define PCI_VENDOR_ID_DELL 0x1028 81 #define PCI_VENDOR_ID_HP 0x103c 82 #define PCI_VENDOR_ID_IBM 0x1014 83 #define PCI_VENDOR_ID_INTEL 0x8086 84 #define PCI_VENDOR_ID_MELLANOX 0x15b3 85 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 86 #define PCI_VENDOR_ID_SERVERWORKS 0x1166 87 #define PCI_VENDOR_ID_SONY 0x104d 88 #define PCI_VENDOR_ID_TOPSPIN 0x1867 89 #define PCI_VENDOR_ID_VIA 0x1106 90 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 91 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 92 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 93 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 94 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 95 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 96 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 97 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 98 #define PCI_SUBDEVICE_ID_QEMU 0x1100 99 100 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 101 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 102 #define PCI_FUNC(devfn) ((devfn) & 0x07) 103 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 104 105 #define PCI_VDEVICE(_vendor, _device) \ 106 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 108 #define PCI_DEVICE(_vendor, _device) \ 109 .vendor = (_vendor), .device = (_device), \ 110 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 111 112 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 113 114 #define PCI_VENDOR_ID PCIR_DEVVENDOR 115 #define PCI_COMMAND PCIR_COMMAND 116 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 117 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 118 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 119 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 120 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 121 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 122 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 123 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 124 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 125 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 126 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 127 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 128 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 129 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 130 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 131 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 132 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 133 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 134 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 135 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 136 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 137 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 138 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 139 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 140 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 141 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 142 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 143 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 144 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 145 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 146 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 147 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 148 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 149 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 150 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 151 152 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 153 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 154 #define PCI_EXP_DEVSTA_TRPND 0x0020 155 156 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 157 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 158 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 159 160 enum pci_bus_speed { 161 PCI_SPEED_UNKNOWN = -1, 162 PCIE_SPEED_2_5GT, 163 PCIE_SPEED_5_0GT, 164 PCIE_SPEED_8_0GT, 165 PCIE_SPEED_16_0GT, 166 }; 167 168 enum pcie_link_width { 169 PCIE_LNK_WIDTH_RESRV = 0x00, 170 PCIE_LNK_X1 = 0x01, 171 PCIE_LNK_X2 = 0x02, 172 PCIE_LNK_X4 = 0x04, 173 PCIE_LNK_X8 = 0x08, 174 PCIE_LNK_X12 = 0x0c, 175 PCIE_LNK_X16 = 0x10, 176 PCIE_LNK_X32 = 0x20, 177 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 178 }; 179 180 typedef int pci_power_t; 181 182 #define PCI_D0 PCI_POWERSTATE_D0 183 #define PCI_D1 PCI_POWERSTATE_D1 184 #define PCI_D2 PCI_POWERSTATE_D2 185 #define PCI_D3hot PCI_POWERSTATE_D3 186 #define PCI_D3cold 4 187 188 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 189 190 struct pci_dev; 191 192 struct pci_driver { 193 struct list_head links; 194 char *name; 195 const struct pci_device_id *id_table; 196 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 197 void (*remove)(struct pci_dev *dev); 198 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 199 int (*resume) (struct pci_dev *dev); /* Device woken up */ 200 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 201 driver_t bsddriver; 202 devclass_t bsdclass; 203 struct device_driver driver; 204 const struct pci_error_handlers *err_handler; 205 bool isdrm; 206 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 207 const nvlist_t *pf_config); 208 void (*bsd_iov_uninit)(device_t dev); 209 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 210 const nvlist_t *vf_config); 211 }; 212 213 struct pci_bus { 214 struct pci_dev *self; 215 int domain; 216 int number; 217 }; 218 219 extern struct list_head pci_drivers; 220 extern struct list_head pci_devices; 221 extern spinlock_t pci_lock; 222 223 #define __devexit_p(x) x 224 225 struct pci_dev { 226 struct device dev; 227 struct list_head links; 228 struct pci_driver *pdrv; 229 struct pci_bus *bus; 230 uint16_t device; 231 uint16_t vendor; 232 uint16_t subsystem_vendor; 233 uint16_t subsystem_device; 234 unsigned int irq; 235 unsigned int devfn; 236 uint32_t class; 237 uint8_t revision; 238 bool msi_enabled; 239 }; 240 241 static inline struct resource_list_entry * 242 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 243 { 244 struct pci_devinfo *dinfo; 245 struct resource_list *rl; 246 247 dinfo = device_get_ivars(pdev->dev.bsddev); 248 rl = &dinfo->resources; 249 return resource_list_find(rl, type, rid); 250 } 251 252 static inline struct resource_list_entry * 253 linux_pci_get_bar(struct pci_dev *pdev, int bar) 254 { 255 struct resource_list_entry *rle; 256 257 bar = PCIR_BAR(bar); 258 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 259 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 260 return (rle); 261 } 262 263 static inline struct device * 264 linux_pci_find_irq_dev(unsigned int irq) 265 { 266 struct pci_dev *pdev; 267 struct device *found; 268 269 found = NULL; 270 spin_lock(&pci_lock); 271 list_for_each_entry(pdev, &pci_devices, links) { 272 if (irq == pdev->dev.irq || 273 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 274 found = &pdev->dev; 275 break; 276 } 277 } 278 spin_unlock(&pci_lock); 279 return (found); 280 } 281 282 static inline int 283 pci_resource_type(struct pci_dev *pdev, int bar) 284 { 285 struct pci_map *pm; 286 287 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 288 if (!pm) 289 return (-1); 290 291 if (PCI_BAR_IO(pm->pm_value)) 292 return (SYS_RES_IOPORT); 293 else 294 return (SYS_RES_MEMORY); 295 } 296 297 /* 298 * All drivers just seem to want to inspect the type not flags. 299 */ 300 static inline int 301 pci_resource_flags(struct pci_dev *pdev, int bar) 302 { 303 int type; 304 305 type = pci_resource_type(pdev, bar); 306 if (type < 0) 307 return (0); 308 return (1 << type); 309 } 310 311 static inline const char * 312 pci_name(struct pci_dev *d) 313 { 314 315 return device_get_desc(d->dev.bsddev); 316 } 317 318 static inline void * 319 pci_get_drvdata(struct pci_dev *pdev) 320 { 321 322 return dev_get_drvdata(&pdev->dev); 323 } 324 325 static inline void 326 pci_set_drvdata(struct pci_dev *pdev, void *data) 327 { 328 329 dev_set_drvdata(&pdev->dev, data); 330 } 331 332 static inline int 333 pci_enable_device(struct pci_dev *pdev) 334 { 335 336 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 337 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 338 return (0); 339 } 340 341 static inline void 342 pci_disable_device(struct pci_dev *pdev) 343 { 344 345 pci_disable_busmaster(pdev->dev.bsddev); 346 } 347 348 static inline int 349 pci_set_master(struct pci_dev *pdev) 350 { 351 352 pci_enable_busmaster(pdev->dev.bsddev); 353 return (0); 354 } 355 356 static inline int 357 pci_set_power_state(struct pci_dev *pdev, int state) 358 { 359 360 pci_set_powerstate(pdev->dev.bsddev, state); 361 return (0); 362 } 363 364 static inline int 365 pci_clear_master(struct pci_dev *pdev) 366 { 367 368 pci_disable_busmaster(pdev->dev.bsddev); 369 return (0); 370 } 371 372 static inline int 373 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 374 { 375 int rid; 376 int type; 377 378 type = pci_resource_type(pdev, bar); 379 if (type < 0) 380 return (-ENODEV); 381 rid = PCIR_BAR(bar); 382 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 383 RF_ACTIVE) == NULL) 384 return (-EINVAL); 385 return (0); 386 } 387 388 static inline void 389 pci_release_region(struct pci_dev *pdev, int bar) 390 { 391 struct resource_list_entry *rle; 392 393 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 394 return; 395 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 396 } 397 398 static inline void 399 pci_release_regions(struct pci_dev *pdev) 400 { 401 int i; 402 403 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 404 pci_release_region(pdev, i); 405 } 406 407 static inline int 408 pci_request_regions(struct pci_dev *pdev, const char *res_name) 409 { 410 int error; 411 int i; 412 413 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 414 error = pci_request_region(pdev, i, res_name); 415 if (error && error != -ENODEV) { 416 pci_release_regions(pdev); 417 return (error); 418 } 419 } 420 return (0); 421 } 422 423 static inline void 424 pci_disable_msix(struct pci_dev *pdev) 425 { 426 427 pci_release_msi(pdev->dev.bsddev); 428 429 /* 430 * The MSIX IRQ numbers associated with this PCI device are no 431 * longer valid and might be re-assigned. Make sure 432 * linux_pci_find_irq_dev() does no longer see them by 433 * resetting their references to zero: 434 */ 435 pdev->dev.irq_start = 0; 436 pdev->dev.irq_end = 0; 437 } 438 439 #define pci_disable_msi(pdev) \ 440 linux_pci_disable_msi(pdev) 441 442 static inline void 443 linux_pci_disable_msi(struct pci_dev *pdev) 444 { 445 446 pci_release_msi(pdev->dev.bsddev); 447 448 pdev->dev.irq_start = 0; 449 pdev->dev.irq_end = 0; 450 pdev->irq = pdev->dev.irq; 451 pdev->msi_enabled = false; 452 } 453 454 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 455 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 456 457 static inline bus_addr_t 458 pci_bus_address(struct pci_dev *pdev, int bar) 459 { 460 461 return (pci_resource_start(pdev, bar)); 462 } 463 464 #define PCI_CAP_ID_EXP PCIY_EXPRESS 465 #define PCI_CAP_ID_PCIX PCIY_PCIX 466 #define PCI_CAP_ID_AGP PCIY_AGP 467 #define PCI_CAP_ID_PM PCIY_PMG 468 469 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 470 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 471 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 472 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 473 #define PCI_EXP_LNKSTA PCIER_LINK_STA 474 475 static inline int 476 pci_find_capability(struct pci_dev *pdev, int capid) 477 { 478 int reg; 479 480 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 481 return (0); 482 return (reg); 483 } 484 485 static inline int pci_pcie_cap(struct pci_dev *dev) 486 { 487 return pci_find_capability(dev, PCI_CAP_ID_EXP); 488 } 489 490 491 static inline int 492 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 493 { 494 495 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 496 return (0); 497 } 498 499 static inline int 500 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 501 { 502 503 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 504 return (0); 505 } 506 507 static inline int 508 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 509 { 510 511 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 512 return (0); 513 } 514 515 static inline int 516 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 517 { 518 519 pci_write_config(pdev->dev.bsddev, where, val, 1); 520 return (0); 521 } 522 523 static inline int 524 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 525 { 526 527 pci_write_config(pdev->dev.bsddev, where, val, 2); 528 return (0); 529 } 530 531 static inline int 532 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 533 { 534 535 pci_write_config(pdev->dev.bsddev, where, val, 4); 536 return (0); 537 } 538 539 int linux_pci_register_driver(struct pci_driver *pdrv); 540 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 541 void linux_pci_unregister_driver(struct pci_driver *pdrv); 542 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 543 544 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 545 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 546 547 struct msix_entry { 548 int entry; 549 int vector; 550 }; 551 552 /* 553 * Enable msix, positive errors indicate actual number of available 554 * vectors. Negative errors are failures. 555 * 556 * NB: define added to prevent this definition of pci_enable_msix from 557 * clashing with the native FreeBSD version. 558 */ 559 #define pci_enable_msix(...) \ 560 linux_pci_enable_msix(__VA_ARGS__) 561 562 static inline int 563 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 564 { 565 struct resource_list_entry *rle; 566 int error; 567 int avail; 568 int i; 569 570 avail = pci_msix_count(pdev->dev.bsddev); 571 if (avail < nreq) { 572 if (avail == 0) 573 return -EINVAL; 574 return avail; 575 } 576 avail = nreq; 577 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 578 return error; 579 /* 580 * Handle case where "pci_alloc_msix()" may allocate less 581 * interrupts than available and return with no error: 582 */ 583 if (avail < nreq) { 584 pci_release_msi(pdev->dev.bsddev); 585 return avail; 586 } 587 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 588 pdev->dev.irq_start = rle->start; 589 pdev->dev.irq_end = rle->start + avail; 590 for (i = 0; i < nreq; i++) 591 entries[i].vector = pdev->dev.irq_start + i; 592 return (0); 593 } 594 595 #define pci_enable_msix_range(...) \ 596 linux_pci_enable_msix_range(__VA_ARGS__) 597 598 static inline int 599 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 600 int minvec, int maxvec) 601 { 602 int nvec = maxvec; 603 int rc; 604 605 if (maxvec < minvec) 606 return (-ERANGE); 607 608 do { 609 rc = pci_enable_msix(dev, entries, nvec); 610 if (rc < 0) { 611 return (rc); 612 } else if (rc > 0) { 613 if (rc < minvec) 614 return (-ENOSPC); 615 nvec = rc; 616 } 617 } while (rc); 618 return (nvec); 619 } 620 621 #define pci_enable_msi(pdev) \ 622 linux_pci_enable_msi(pdev) 623 624 static inline int 625 pci_enable_msi(struct pci_dev *pdev) 626 { 627 struct resource_list_entry *rle; 628 int error; 629 int avail; 630 631 avail = pci_msi_count(pdev->dev.bsddev); 632 if (avail < 1) 633 return -EINVAL; 634 635 avail = 1; /* this function only enable one MSI IRQ */ 636 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 637 return error; 638 639 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 640 pdev->dev.irq_start = rle->start; 641 pdev->dev.irq_end = rle->start + avail; 642 pdev->irq = rle->start; 643 pdev->msi_enabled = true; 644 return (0); 645 } 646 647 static inline int 648 pci_channel_offline(struct pci_dev *pdev) 649 { 650 651 return (pci_get_vendor(pdev->dev.bsddev) == PCIV_INVALID); 652 } 653 654 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 655 { 656 return -ENODEV; 657 } 658 static inline void pci_disable_sriov(struct pci_dev *dev) 659 { 660 } 661 662 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 663 const struct pci_device_id _table[] __devinitdata 664 665 666 /* XXX This should not be necessary. */ 667 #define pcix_set_mmrbc(d, v) 0 668 #define pcix_get_max_mmrbc(d) 0 669 #define pcie_set_readrq(d, v) pci_set_max_read_req(&(d)->dev, (v)) 670 671 #define PCI_DMA_BIDIRECTIONAL 0 672 #define PCI_DMA_TODEVICE 1 673 #define PCI_DMA_FROMDEVICE 2 674 #define PCI_DMA_NONE 3 675 676 #define pci_pool dma_pool 677 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 678 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 679 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 680 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 681 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 682 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 683 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 684 _size, _vaddr, _dma_handle) 685 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 686 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 687 _sg, _nents, (enum dma_data_direction)_dir) 688 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 689 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 690 (_ptr), (_size), (enum dma_data_direction)_dir) 691 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 692 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 693 _addr, _size, (enum dma_data_direction)_dir) 694 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 695 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 696 _sg, _nents, (enum dma_data_direction)_dir) 697 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 698 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 699 _offset, _size, (enum dma_data_direction)_dir) 700 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 701 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 702 _dma_address, _size, (enum dma_data_direction)_dir) 703 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 704 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 705 dma_mapping_error(&(_pdev)->dev, _dma_addr) 706 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 707 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 708 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 709 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 710 #define pci_unmap_addr dma_unmap_addr 711 #define pci_unmap_addr_set dma_unmap_addr_set 712 #define pci_unmap_len dma_unmap_len 713 #define pci_unmap_len_set dma_unmap_len_set 714 715 typedef unsigned int __bitwise pci_channel_state_t; 716 typedef unsigned int __bitwise pci_ers_result_t; 717 718 enum pci_channel_state { 719 pci_channel_io_normal = 1, 720 pci_channel_io_frozen = 2, 721 pci_channel_io_perm_failure = 3, 722 }; 723 724 enum pci_ers_result { 725 PCI_ERS_RESULT_NONE = 1, 726 PCI_ERS_RESULT_CAN_RECOVER = 2, 727 PCI_ERS_RESULT_NEED_RESET = 3, 728 PCI_ERS_RESULT_DISCONNECT = 4, 729 PCI_ERS_RESULT_RECOVERED = 5, 730 }; 731 732 733 /* PCI bus error event callbacks */ 734 struct pci_error_handlers { 735 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 736 enum pci_channel_state error); 737 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 738 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 739 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 740 void (*resume)(struct pci_dev *dev); 741 }; 742 743 /* FreeBSD does not support SRIOV - yet */ 744 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 745 { 746 return dev; 747 } 748 749 static inline bool pci_is_pcie(struct pci_dev *dev) 750 { 751 return !!pci_pcie_cap(dev); 752 } 753 754 static inline u16 pcie_flags_reg(struct pci_dev *dev) 755 { 756 int pos; 757 u16 reg16; 758 759 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 760 if (!pos) 761 return 0; 762 763 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 764 765 return reg16; 766 } 767 768 769 static inline int pci_pcie_type(struct pci_dev *dev) 770 { 771 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 772 } 773 774 static inline int pcie_cap_version(struct pci_dev *dev) 775 { 776 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 777 } 778 779 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 780 { 781 int type = pci_pcie_type(dev); 782 783 return pcie_cap_version(dev) > 1 || 784 type == PCI_EXP_TYPE_ROOT_PORT || 785 type == PCI_EXP_TYPE_ENDPOINT || 786 type == PCI_EXP_TYPE_LEG_END; 787 } 788 789 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 790 { 791 return true; 792 } 793 794 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 795 { 796 int type = pci_pcie_type(dev); 797 798 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 799 (type == PCI_EXP_TYPE_DOWNSTREAM && 800 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 801 } 802 803 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 804 { 805 int type = pci_pcie_type(dev); 806 807 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 808 type == PCI_EXP_TYPE_RC_EC; 809 } 810 811 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 812 { 813 if (!pci_is_pcie(dev)) 814 return false; 815 816 switch (pos) { 817 case PCI_EXP_FLAGS_TYPE: 818 return true; 819 case PCI_EXP_DEVCAP: 820 case PCI_EXP_DEVCTL: 821 case PCI_EXP_DEVSTA: 822 return pcie_cap_has_devctl(dev); 823 case PCI_EXP_LNKCAP: 824 case PCI_EXP_LNKCTL: 825 case PCI_EXP_LNKSTA: 826 return pcie_cap_has_lnkctl(dev); 827 case PCI_EXP_SLTCAP: 828 case PCI_EXP_SLTCTL: 829 case PCI_EXP_SLTSTA: 830 return pcie_cap_has_sltctl(dev); 831 case PCI_EXP_RTCTL: 832 case PCI_EXP_RTCAP: 833 case PCI_EXP_RTSTA: 834 return pcie_cap_has_rtctl(dev); 835 case PCI_EXP_DEVCAP2: 836 case PCI_EXP_DEVCTL2: 837 case PCI_EXP_LNKCAP2: 838 case PCI_EXP_LNKCTL2: 839 case PCI_EXP_LNKSTA2: 840 return pcie_cap_version(dev) > 1; 841 default: 842 return false; 843 } 844 } 845 846 static inline int 847 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 848 { 849 if (pos & 3) 850 return -EINVAL; 851 852 if (!pcie_capability_reg_implemented(dev, pos)) 853 return -EINVAL; 854 855 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 856 } 857 858 static inline int 859 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 860 { 861 if (pos & 3) 862 return -EINVAL; 863 864 if (!pcie_capability_reg_implemented(dev, pos)) 865 return -EINVAL; 866 867 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 868 } 869 870 static inline int 871 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 872 { 873 if (pos & 1) 874 return -EINVAL; 875 876 if (!pcie_capability_reg_implemented(dev, pos)) 877 return 0; 878 879 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 880 } 881 882 static inline int pcie_get_minimum_link(struct pci_dev *dev, 883 enum pci_bus_speed *speed, enum pcie_link_width *width) 884 { 885 *speed = PCI_SPEED_UNKNOWN; 886 *width = PCIE_LNK_WIDTH_UNKNOWN; 887 return (0); 888 } 889 890 static inline int 891 pci_num_vf(struct pci_dev *dev) 892 { 893 return (0); 894 } 895 896 static inline enum pci_bus_speed 897 pcie_get_speed_cap(struct pci_dev *dev) 898 { 899 device_t root; 900 uint32_t lnkcap, lnkcap2; 901 int error, pos; 902 903 root = device_get_parent(dev->dev.bsddev); 904 if (root == NULL) 905 return (PCI_SPEED_UNKNOWN); 906 root = device_get_parent(root); 907 if (root == NULL) 908 return (PCI_SPEED_UNKNOWN); 909 root = device_get_parent(root); 910 if (root == NULL) 911 return (PCI_SPEED_UNKNOWN); 912 913 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 914 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 915 return (PCI_SPEED_UNKNOWN); 916 917 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 918 return (PCI_SPEED_UNKNOWN); 919 920 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 921 922 if (lnkcap2) { /* PCIe r3.0-compliant */ 923 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 924 return (PCIE_SPEED_2_5GT); 925 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 926 return (PCIE_SPEED_5_0GT); 927 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 928 return (PCIE_SPEED_8_0GT); 929 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 930 return (PCIE_SPEED_16_0GT); 931 } else { /* pre-r3.0 */ 932 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 933 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 934 return (PCIE_SPEED_2_5GT); 935 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 936 return (PCIE_SPEED_5_0GT); 937 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 938 return (PCIE_SPEED_8_0GT); 939 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 940 return (PCIE_SPEED_16_0GT); 941 } 942 return (PCI_SPEED_UNKNOWN); 943 } 944 945 static inline enum pcie_link_width 946 pcie_get_width_cap(struct pci_dev *dev) 947 { 948 uint32_t lnkcap; 949 950 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 951 if (lnkcap) 952 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 953 954 return (PCIE_LNK_WIDTH_UNKNOWN); 955 } 956 957 /* 958 * The following functions can be used to attach/detach the LinuxKPI's 959 * PCI device runtime. The pci_driver and pci_device_id pointer is 960 * allowed to be NULL. Other pointers must be all valid. 961 * The pci_dev structure should be zero-initialized before passed 962 * to the linux_pci_attach_device function. 963 */ 964 extern int linux_pci_attach_device(device_t, struct pci_driver *, 965 const struct pci_device_id *, struct pci_dev *); 966 extern int linux_pci_detach_device(struct pci_dev *); 967 968 #endif /* _LINUX_PCI_H_ */ 969