1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2025 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 #include <linux/device/driver.h> 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_private.h> 49 50 #include <machine/resource.h> 51 52 #include <linux/list.h> 53 #include <linux/dmapool.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/compiler.h> 56 #include <linux/errno.h> 57 #include <asm/atomic.h> 58 #include <asm/memtype.h> 59 #include <linux/device.h> 60 #include <linux/pci_ids.h> 61 #include <linux/pm.h> 62 63 #include <linux/kernel.h> /* pr_debug */ 64 65 struct pci_device_id { 66 uint32_t vendor; 67 uint32_t device; 68 uint32_t subvendor; 69 uint32_t subdevice; 70 uint32_t class; 71 uint32_t class_mask; 72 uintptr_t driver_data; 73 }; 74 75 #define MODULE_DEVICE_TABLE_BUS_pci(_bus, _table) \ 76 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 77 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 78 79 #define PCI_ANY_ID -1U 80 81 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 82 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 83 #define PCI_FUNC(devfn) ((devfn) & 0x07) 84 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 85 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 86 87 #define PCI_VDEVICE(_vendor, _device) \ 88 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 89 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 90 #define PCI_DEVICE(_vendor, _device) \ 91 .vendor = (_vendor), .device = (_device), \ 92 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 93 94 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 95 96 #define PCI_STD_NUM_BARS 6 97 #define PCI_BASE_ADDRESS_0 PCIR_BARS 98 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 99 #define PCI_VENDOR_ID PCIR_VENDOR 100 #define PCI_DEVICE_ID PCIR_DEVICE 101 #define PCI_COMMAND PCIR_COMMAND 102 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 103 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 104 #define PCI_PRIMARY_BUS PCIR_PRIBUS_1 105 #define PCI_SECONDARY_BUS PCIR_SECBUS_1 106 #define PCI_SUBORDINATE_BUS PCIR_SUBBUS_1 107 #define PCI_SEC_LATENCY_TIMER PCIR_SECLAT_1 108 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 109 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 110 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 111 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 112 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 113 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 114 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 115 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 116 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 117 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 118 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 119 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 120 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 121 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 122 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 123 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 124 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 125 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 126 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 127 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 128 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 129 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 130 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 131 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 132 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 133 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 134 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 135 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 136 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 137 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 138 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 139 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 140 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 141 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 142 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 143 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 144 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 145 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 146 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 147 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 148 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 149 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 150 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 151 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 152 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 153 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 154 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 155 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 156 #define PCI_EXP_LNKCTL2_TLS 0x000f 157 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 158 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 159 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 160 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 161 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 162 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 163 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 164 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 165 166 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 167 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 168 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 169 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 170 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 171 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 172 173 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 174 #define PCI_EXP_DEVSTA_TRPND 0x0020 175 176 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 177 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 178 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 179 180 enum pci_bus_speed { 181 PCI_SPEED_UNKNOWN = -1, 182 PCIE_SPEED_2_5GT, 183 PCIE_SPEED_5_0GT, 184 PCIE_SPEED_8_0GT, 185 PCIE_SPEED_16_0GT, 186 PCIE_SPEED_32_0GT, 187 PCIE_SPEED_64_0GT, 188 }; 189 190 enum pcie_link_width { 191 PCIE_LNK_WIDTH_RESRV = 0x00, 192 PCIE_LNK_X1 = 0x01, 193 PCIE_LNK_X2 = 0x02, 194 PCIE_LNK_X4 = 0x04, 195 PCIE_LNK_X8 = 0x08, 196 PCIE_LNK_X12 = 0x0c, 197 PCIE_LNK_X16 = 0x10, 198 PCIE_LNK_X32 = 0x20, 199 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 200 }; 201 202 #define PCIE_LINK_STATE_L0S 0x00000001 203 #define PCIE_LINK_STATE_L1 0x00000002 204 #define PCIE_LINK_STATE_CLKPM 0x00000004 205 206 typedef int pci_power_t; 207 208 #define PCI_D0 PCI_POWERSTATE_D0 209 #define PCI_D1 PCI_POWERSTATE_D1 210 #define PCI_D2 PCI_POWERSTATE_D2 211 #define PCI_D3hot PCI_POWERSTATE_D3_HOT 212 #define PCI_D3cold PCI_POWERSTATE_D3_COLD 213 214 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 215 216 extern const char *pci_power_names[6]; 217 218 #define PCI_ERR_UNCOR_STATUS PCIR_AER_UC_STATUS 219 #define PCI_ERR_COR_STATUS PCIR_AER_COR_STATUS 220 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 221 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 222 223 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 224 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 225 226 #define PCI_L1SS_CTL1 0x8 227 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 228 229 #define PCI_IRQ_INTX 0x01 230 #define PCI_IRQ_MSI 0x02 231 #define PCI_IRQ_MSIX 0x04 232 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_INTX) 233 234 #if defined(LINUXKPI_VERSION) && (LINUXKPI_VERSION <= 61000) 235 #define PCI_IRQ_LEGACY PCI_IRQ_INTX 236 #endif 237 238 /* 239 * Linux PCI code uses `PCI_SET_ERROR_RESPONSE()` to indicate to the caller of 240 * a `pci_read_*()` function that the read failed. An example of failure is 241 * whether the device was disconnected. It is a bit weird because Linux 242 * `pci_read_*()` can return an error value, as the read value is stored in a 243 * integer passed by pointer. 244 * 245 * We don't set PCI_ERROR_RESPONSE anywhere as of this commit, but the DRM 246 * drivers started to use `PCI_POSSIBLE_ERROR()`. 247 */ 248 #define PCI_ERROR_RESPONSE (~0ULL) 249 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 250 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 251 252 struct pci_dev; 253 254 struct pci_driver { 255 struct list_head node; 256 char *name; 257 const struct pci_device_id *id_table; 258 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 259 void (*remove)(struct pci_dev *dev); 260 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 261 int (*resume) (struct pci_dev *dev); /* Device woken up */ 262 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 263 driver_t bsddriver; 264 devclass_t bsdclass; 265 struct device_driver driver; 266 const struct pci_error_handlers *err_handler; 267 bool isdrm; 268 int bsd_probe_return; 269 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 270 const nvlist_t *pf_config); 271 void (*bsd_iov_uninit)(device_t dev); 272 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 273 const nvlist_t *vf_config); 274 }; 275 276 struct pci_bus { 277 struct pci_dev *self; 278 /* struct pci_bus *parent */ 279 int domain; 280 int number; 281 }; 282 283 extern struct list_head pci_drivers; 284 extern struct list_head pci_devices; 285 extern spinlock_t pci_lock; 286 287 #define __devexit_p(x) x 288 289 #define module_pci_driver(_drv) \ 290 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver) 291 292 struct msi_msg { 293 uint32_t data; 294 }; 295 296 struct pci_msi_desc { 297 struct { 298 bool is_64; 299 } msi_attrib; 300 }; 301 302 struct msi_desc { 303 struct msi_msg msg; 304 struct pci_msi_desc pci; 305 }; 306 307 struct msix_entry { 308 int entry; 309 int vector; 310 }; 311 312 /* 313 * If we find drivers accessing this from multiple KPIs we may have to 314 * refcount objects of this structure. 315 */ 316 struct resource; 317 struct pci_mmio_region { 318 TAILQ_ENTRY(pci_mmio_region) next; 319 struct resource *res; 320 int rid; 321 int type; 322 }; 323 324 struct pci_dev { 325 struct device dev; 326 struct list_head links; 327 struct pci_driver *pdrv; 328 struct pci_bus *bus; 329 struct pci_dev *root; 330 pci_power_t current_state; 331 uint16_t device; 332 uint16_t vendor; 333 uint16_t subsystem_vendor; 334 uint16_t subsystem_device; 335 unsigned int irq; 336 unsigned int devfn; 337 uint32_t class; 338 uint8_t revision; 339 uint8_t msi_cap; 340 uint8_t msix_cap; 341 bool managed; /* devres "pcim_*(). */ 342 bool want_iomap_res; 343 bool msi_enabled; 344 bool msix_enabled; 345 phys_addr_t rom; 346 size_t romlen; 347 struct msi_desc **msi_desc; 348 char *path_name; 349 spinlock_t pcie_cap_lock; 350 351 TAILQ_HEAD(, pci_mmio_region) mmio; 352 }; 353 354 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 355 unsigned int flags); 356 bool pci_device_is_present(struct pci_dev *pdev); 357 358 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 359 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 360 void *linuxkpi_pci_iomap_range(struct pci_dev *, int, 361 unsigned long, unsigned long); 362 void *linuxkpi_pci_iomap(struct pci_dev *, int, unsigned long); 363 void *linuxkpi_pcim_iomap(struct pci_dev *, int, unsigned long); 364 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 365 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 366 const char *name); 367 int linuxkpi_pci_request_region(struct pci_dev *, int, const char *); 368 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 369 int linuxkpi_pcim_request_all_regions(struct pci_dev *, const char *); 370 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 371 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 372 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 373 int nreq); 374 375 /* Internal helper function(s). */ 376 struct pci_dev *lkpinew_pci_dev(device_t); 377 void lkpi_pci_devres_release(struct device *, void *); 378 struct pci_dev *lkpi_pci_get_device(uint32_t, uint32_t, struct pci_dev *); 379 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 380 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 381 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 382 383 #define pci_err(pdev, fmt, ...) \ 384 dev_err(&(pdev)->dev, fmt, ##__VA_ARGS__) 385 #define pci_info(pdev, fmt, ...) \ 386 dev_info(&(pdev)->dev, fmt, ##__VA_ARGS__) 387 388 static inline bool 389 dev_is_pci(struct device *dev) 390 { 391 392 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 393 } 394 395 static inline uint16_t 396 pci_dev_id(struct pci_dev *pdev) 397 { 398 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 399 } 400 401 static inline int 402 pci_resource_type(struct pci_dev *pdev, int bar) 403 { 404 struct pci_map *pm; 405 406 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 407 if (!pm) 408 return (-1); 409 410 if (PCI_BAR_IO(pm->pm_value)) 411 return (SYS_RES_IOPORT); 412 else 413 return (SYS_RES_MEMORY); 414 } 415 416 /* 417 * All drivers just seem to want to inspect the type not flags. 418 */ 419 static inline int 420 pci_resource_flags(struct pci_dev *pdev, int bar) 421 { 422 int type; 423 424 type = pci_resource_type(pdev, bar); 425 if (type < 0) 426 return (0); 427 return (1 << type); 428 } 429 430 static inline const char * 431 pci_name(struct pci_dev *d) 432 { 433 return d->path_name; 434 } 435 436 static inline void * 437 pci_get_drvdata(struct pci_dev *pdev) 438 { 439 440 return dev_get_drvdata(&pdev->dev); 441 } 442 443 static inline void 444 pci_set_drvdata(struct pci_dev *pdev, void *data) 445 { 446 447 dev_set_drvdata(&pdev->dev, data); 448 } 449 450 static inline struct pci_dev * 451 pci_dev_get(struct pci_dev *pdev) 452 { 453 454 if (pdev != NULL) 455 get_device(&pdev->dev); 456 return (pdev); 457 } 458 459 static __inline void 460 pci_dev_put(struct pci_dev *pdev) 461 { 462 463 if (pdev != NULL) 464 put_device(&pdev->dev); 465 } 466 467 static inline int 468 pci_enable_device(struct pci_dev *pdev) 469 { 470 471 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 472 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 473 return (0); 474 } 475 476 static inline void 477 pci_disable_device(struct pci_dev *pdev) 478 { 479 480 pci_disable_busmaster(pdev->dev.bsddev); 481 } 482 483 static inline int 484 pci_set_master(struct pci_dev *pdev) 485 { 486 487 pci_enable_busmaster(pdev->dev.bsddev); 488 return (0); 489 } 490 491 static inline int 492 pci_set_power_state(struct pci_dev *pdev, int state) 493 { 494 495 pci_set_powerstate(pdev->dev.bsddev, state); 496 return (0); 497 } 498 499 static inline int 500 pci_clear_master(struct pci_dev *pdev) 501 { 502 503 pci_disable_busmaster(pdev->dev.bsddev); 504 return (0); 505 } 506 507 static inline bool 508 pci_is_root_bus(struct pci_bus *pbus) 509 { 510 511 return (pbus->self == NULL); 512 } 513 514 static inline struct pci_dev * 515 pci_upstream_bridge(struct pci_dev *pdev) 516 { 517 518 if (pci_is_root_bus(pdev->bus)) 519 return (NULL); 520 521 /* 522 * If we do not have a (proper) "upstream bridge" set, e.g., we point 523 * to ourselves, try to handle this case on the fly like we do 524 * for pcie_find_root_port(). 525 */ 526 if (pdev == pdev->bus->self) { 527 device_t bridge; 528 529 /* 530 * In the case of DRM drivers, the passed device is a child of 531 * `vgapci`. We want to start the lookup from `vgapci`, so the 532 * parent of the passed `drmn`. 533 * 534 * We can use the `isdrm` flag to determine this. 535 */ 536 bridge = pdev->dev.bsddev; 537 if (pdev->pdrv != NULL && pdev->pdrv->isdrm) 538 bridge = device_get_parent(bridge); 539 if (bridge == NULL) 540 goto done; 541 542 bridge = device_get_parent(bridge); 543 if (bridge == NULL) 544 goto done; 545 bridge = device_get_parent(bridge); 546 if (bridge == NULL) 547 goto done; 548 if (device_get_devclass(device_get_parent(bridge)) != 549 devclass_find("pci")) 550 goto done; 551 552 /* 553 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 554 * for it so it can be returned. 555 */ 556 pdev->bus->self = lkpinew_pci_dev(bridge); 557 } 558 done: 559 return (pdev->bus->self); 560 } 561 562 #define pci_request_region(pdev, bar, res_name) \ 563 linuxkpi_pci_request_region(pdev, bar, res_name) 564 #define pci_release_region(pdev, bar) \ 565 linuxkpi_pci_release_region(pdev, bar) 566 #define pci_request_regions(pdev, res_name) \ 567 linuxkpi_pci_request_regions(pdev, res_name) 568 #define pci_release_regions(pdev) \ 569 linuxkpi_pci_release_regions(pdev) 570 #define pcim_request_all_regions(pdev, name) \ 571 linuxkpi_pcim_request_all_regions(pdev, name) 572 573 static inline void 574 lkpi_pci_disable_msix(struct pci_dev *pdev) 575 { 576 577 pci_release_msi(pdev->dev.bsddev); 578 579 /* 580 * The MSIX IRQ numbers associated with this PCI device are no 581 * longer valid and might be re-assigned. Make sure 582 * lkpi_pci_find_irq_dev() does no longer see them by 583 * resetting their references to zero: 584 */ 585 pdev->dev.irq_start = 0; 586 pdev->dev.irq_end = 0; 587 pdev->msix_enabled = false; 588 } 589 /* Only for consistency. No conflict on that one. */ 590 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 591 592 static inline void 593 lkpi_pci_disable_msi(struct pci_dev *pdev) 594 { 595 596 pci_release_msi(pdev->dev.bsddev); 597 598 pdev->dev.irq_start = 0; 599 pdev->dev.irq_end = 0; 600 pdev->irq = pdev->dev.irq; 601 pdev->msi_enabled = false; 602 } 603 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 604 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 605 606 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 607 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 608 609 static inline bus_addr_t 610 pci_bus_address(struct pci_dev *pdev, int bar) 611 { 612 613 return (pci_resource_start(pdev, bar)); 614 } 615 616 #define PCI_CAP_ID_EXP PCIY_EXPRESS 617 #define PCI_CAP_ID_PCIX PCIY_PCIX 618 #define PCI_CAP_ID_AGP PCIY_AGP 619 #define PCI_CAP_ID_PM PCIY_PMG 620 621 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 622 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 623 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 624 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 625 #define PCI_EXP_LNKSTA PCIER_LINK_STA 626 627 static inline int 628 pci_find_capability(struct pci_dev *pdev, int capid) 629 { 630 int reg; 631 632 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 633 return (0); 634 return (reg); 635 } 636 637 static inline int pci_pcie_cap(struct pci_dev *dev) 638 { 639 return pci_find_capability(dev, PCI_CAP_ID_EXP); 640 } 641 642 static inline int 643 pci_find_ext_capability(struct pci_dev *pdev, int capid) 644 { 645 int reg; 646 647 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 648 return (0); 649 return (reg); 650 } 651 652 #define PCIM_PCAP_PME_SHIFT 11 653 static __inline bool 654 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 655 { 656 struct pci_devinfo *dinfo; 657 pcicfgregs *cfg; 658 659 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 660 return (false); 661 662 dinfo = device_get_ivars(pdev->dev.bsddev); 663 cfg = &dinfo->cfg; 664 665 if (cfg->pp.pp_cap == 0) 666 return (false); 667 668 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 669 return (true); 670 671 return (false); 672 } 673 674 static inline int 675 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 676 { 677 678 if (!pci_enable_aspm) 679 return (-EPERM); 680 681 return (-ENXIO); 682 } 683 684 static inline int 685 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 686 { 687 688 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 689 return (0); 690 } 691 692 static inline int 693 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 694 { 695 696 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 697 return (0); 698 } 699 700 static inline int 701 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 702 { 703 704 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 705 return (0); 706 } 707 708 static inline int 709 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 710 { 711 712 pci_write_config(pdev->dev.bsddev, where, val, 1); 713 return (0); 714 } 715 716 static inline int 717 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 718 { 719 720 pci_write_config(pdev->dev.bsddev, where, val, 2); 721 return (0); 722 } 723 724 static inline int 725 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 726 { 727 728 pci_write_config(pdev->dev.bsddev, where, val, 4); 729 return (0); 730 } 731 732 int linux_pci_register_driver(struct pci_driver *pdrv); 733 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 734 void linux_pci_unregister_driver(struct pci_driver *pdrv); 735 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 736 737 #define pci_register_driver(pdrv) \ 738 linux_pci_register_driver(pdrv) 739 #define pci_unregister_driver(pdrv) \ 740 linux_pci_unregister_driver(pdrv) 741 742 /* 743 * Enable msix, positive errors indicate actual number of available 744 * vectors. Negative errors are failures. 745 * 746 * NB: define added to prevent this definition of pci_enable_msix from 747 * clashing with the native FreeBSD version. 748 */ 749 #define pci_enable_msix(...) \ 750 linuxkpi_pci_enable_msix(__VA_ARGS__) 751 752 #define pci_enable_msix_range(...) \ 753 linux_pci_enable_msix_range(__VA_ARGS__) 754 755 static inline int 756 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 757 int minvec, int maxvec) 758 { 759 int nvec = maxvec; 760 int rc; 761 762 if (maxvec < minvec) 763 return (-ERANGE); 764 765 do { 766 rc = pci_enable_msix(dev, entries, nvec); 767 if (rc < 0) { 768 return (rc); 769 } else if (rc > 0) { 770 if (rc < minvec) 771 return (-ENOSPC); 772 nvec = rc; 773 } 774 } while (rc); 775 return (nvec); 776 } 777 778 #define pci_enable_msi(pdev) \ 779 linux_pci_enable_msi(pdev) 780 781 static inline int 782 pci_enable_msi(struct pci_dev *pdev) 783 { 784 785 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 786 } 787 788 static inline int 789 pci_channel_offline(struct pci_dev *pdev) 790 { 791 792 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 793 } 794 795 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 796 { 797 return -ENODEV; 798 } 799 800 static inline void pci_disable_sriov(struct pci_dev *dev) 801 { 802 } 803 804 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \ 805 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) 806 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 807 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 808 #define pcim_iomap(pdev, bar, maxlen) \ 809 linuxkpi_pcim_iomap(pdev, bar, maxlen) 810 #define pci_iounmap(pdev, res) \ 811 linuxkpi_pci_iounmap(pdev, res) 812 813 static inline void 814 lkpi_pci_save_state(struct pci_dev *pdev) 815 { 816 817 pci_save_state(pdev->dev.bsddev); 818 } 819 820 static inline void 821 lkpi_pci_restore_state(struct pci_dev *pdev) 822 { 823 824 pci_restore_state(pdev->dev.bsddev); 825 } 826 827 #define pci_save_state(dev) lkpi_pci_save_state(dev) 828 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 829 830 static inline int 831 linuxkpi_pci_enable_wake(struct pci_dev *pdev, pci_power_t state, bool ena) 832 { 833 /* 834 * We do not currently support this in device.h either to 835 * check if the device is allowed to wake up in first place. 836 */ 837 pr_debug("%s: TODO\n", __func__); 838 return (0); 839 } 840 #define pci_enable_wake(dev, state, ena) \ 841 linuxkpi_pci_enable_wake(dev, state, ena) 842 843 static inline int 844 pci_reset_function(struct pci_dev *pdev) 845 { 846 847 return (-ENOSYS); 848 } 849 850 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 851 const struct pci_device_id _table[] __devinitdata 852 853 /* XXX This should not be necessary. */ 854 #define pcix_set_mmrbc(d, v) 0 855 #define pcix_get_max_mmrbc(d) 0 856 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 857 858 #define PCI_DMA_BIDIRECTIONAL 0 859 #define PCI_DMA_TODEVICE 1 860 #define PCI_DMA_FROMDEVICE 2 861 #define PCI_DMA_NONE 3 862 863 #define pci_pool dma_pool 864 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 865 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 866 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 867 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 868 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 869 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 870 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 871 _size, _vaddr, _dma_handle) 872 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 873 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 874 _sg, _nents, (enum dma_data_direction)_dir) 875 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 876 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 877 (_ptr), (_size), (enum dma_data_direction)_dir) 878 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 879 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 880 _addr, _size, (enum dma_data_direction)_dir) 881 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 882 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 883 _sg, _nents, (enum dma_data_direction)_dir) 884 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 885 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 886 _offset, _size, (enum dma_data_direction)_dir) 887 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 888 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 889 _dma_address, _size, (enum dma_data_direction)_dir) 890 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 891 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 892 dma_mapping_error(&(_pdev)->dev, _dma_addr) 893 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 894 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 895 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 896 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 897 #define pci_unmap_addr dma_unmap_addr 898 #define pci_unmap_addr_set dma_unmap_addr_set 899 #define pci_unmap_len dma_unmap_len 900 #define pci_unmap_len_set dma_unmap_len_set 901 902 typedef unsigned int __bitwise pci_channel_state_t; 903 typedef unsigned int __bitwise pci_ers_result_t; 904 905 enum pci_channel_state { 906 pci_channel_io_normal = 1, 907 pci_channel_io_frozen = 2, 908 pci_channel_io_perm_failure = 3, 909 }; 910 911 enum pci_ers_result { 912 PCI_ERS_RESULT_NONE = 1, 913 PCI_ERS_RESULT_CAN_RECOVER = 2, 914 PCI_ERS_RESULT_NEED_RESET = 3, 915 PCI_ERS_RESULT_DISCONNECT = 4, 916 PCI_ERS_RESULT_RECOVERED = 5, 917 }; 918 919 /* PCI bus error event callbacks */ 920 struct pci_error_handlers { 921 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 922 enum pci_channel_state error); 923 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 924 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 925 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 926 void (*resume)(struct pci_dev *dev); 927 }; 928 929 /* FreeBSD does not support SRIOV - yet */ 930 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 931 { 932 return dev; 933 } 934 935 static inline bool pci_is_pcie(struct pci_dev *dev) 936 { 937 return !!pci_pcie_cap(dev); 938 } 939 940 static inline u16 pcie_flags_reg(struct pci_dev *dev) 941 { 942 int pos; 943 u16 reg16; 944 945 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 946 if (!pos) 947 return 0; 948 949 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 950 951 return reg16; 952 } 953 954 static inline int pci_pcie_type(struct pci_dev *dev) 955 { 956 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 957 } 958 959 static inline int pcie_cap_version(struct pci_dev *dev) 960 { 961 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 962 } 963 964 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 965 { 966 int type = pci_pcie_type(dev); 967 968 return pcie_cap_version(dev) > 1 || 969 type == PCI_EXP_TYPE_ROOT_PORT || 970 type == PCI_EXP_TYPE_ENDPOINT || 971 type == PCI_EXP_TYPE_LEG_END; 972 } 973 974 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 975 { 976 return true; 977 } 978 979 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 980 { 981 int type = pci_pcie_type(dev); 982 983 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 984 (type == PCI_EXP_TYPE_DOWNSTREAM && 985 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 986 } 987 988 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 989 { 990 int type = pci_pcie_type(dev); 991 992 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 993 type == PCI_EXP_TYPE_RC_EC; 994 } 995 996 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 997 { 998 if (!pci_is_pcie(dev)) 999 return false; 1000 1001 switch (pos) { 1002 case PCI_EXP_FLAGS_TYPE: 1003 return true; 1004 case PCI_EXP_DEVCAP: 1005 case PCI_EXP_DEVCTL: 1006 case PCI_EXP_DEVSTA: 1007 return pcie_cap_has_devctl(dev); 1008 case PCI_EXP_LNKCAP: 1009 case PCI_EXP_LNKCTL: 1010 case PCI_EXP_LNKSTA: 1011 return pcie_cap_has_lnkctl(dev); 1012 case PCI_EXP_SLTCAP: 1013 case PCI_EXP_SLTCTL: 1014 case PCI_EXP_SLTSTA: 1015 return pcie_cap_has_sltctl(dev); 1016 case PCI_EXP_RTCTL: 1017 case PCI_EXP_RTCAP: 1018 case PCI_EXP_RTSTA: 1019 return pcie_cap_has_rtctl(dev); 1020 case PCI_EXP_DEVCAP2: 1021 case PCI_EXP_DEVCTL2: 1022 case PCI_EXP_LNKCAP2: 1023 case PCI_EXP_LNKCTL2: 1024 case PCI_EXP_LNKSTA2: 1025 return pcie_cap_version(dev) > 1; 1026 default: 1027 return false; 1028 } 1029 } 1030 1031 static inline int 1032 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1033 { 1034 *dst = 0; 1035 if (pos & 3) 1036 return -EINVAL; 1037 1038 if (!pcie_capability_reg_implemented(dev, pos)) 1039 return -EINVAL; 1040 1041 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1042 } 1043 1044 static inline int 1045 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1046 { 1047 *dst = 0; 1048 if (pos & 3) 1049 return -EINVAL; 1050 1051 if (!pcie_capability_reg_implemented(dev, pos)) 1052 return -EINVAL; 1053 1054 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1055 } 1056 1057 static inline int 1058 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1059 { 1060 if (pos & 1) 1061 return -EINVAL; 1062 1063 if (!pcie_capability_reg_implemented(dev, pos)) 1064 return 0; 1065 1066 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1067 } 1068 1069 static inline int 1070 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1071 uint16_t clear, uint16_t set) 1072 { 1073 int error; 1074 uint16_t v; 1075 1076 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1077 spin_lock(&dev->pcie_cap_lock); 1078 1079 error = pcie_capability_read_word(dev, pos, &v); 1080 if (error == 0) { 1081 v &= ~clear; 1082 v |= set; 1083 error = pcie_capability_write_word(dev, pos, v); 1084 } 1085 1086 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1087 spin_unlock(&dev->pcie_cap_lock); 1088 1089 return (error); 1090 } 1091 1092 static inline int 1093 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1094 { 1095 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1096 } 1097 1098 static inline int 1099 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1100 { 1101 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1102 } 1103 1104 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1105 enum pci_bus_speed *speed, enum pcie_link_width *width) 1106 { 1107 *speed = PCI_SPEED_UNKNOWN; 1108 *width = PCIE_LNK_WIDTH_UNKNOWN; 1109 return (0); 1110 } 1111 1112 static inline int 1113 pci_num_vf(struct pci_dev *dev) 1114 { 1115 return (0); 1116 } 1117 1118 static inline enum pci_bus_speed 1119 pcie_get_speed_cap(struct pci_dev *dev) 1120 { 1121 struct pci_dev *pbus; 1122 device_t root; 1123 uint32_t lnkcap, lnkcap2; 1124 int error, pos; 1125 1126 /* 1127 * We should always be called on a PCI device. 1128 * The only current consumer I could find was amdgpu which either 1129 * calls us directly on a pdev(drmn?) or with the result of 1130 * pci_upstream_bridge(). 1131 * 1132 * Treat "drmn" as special again as it is not a PCI device. 1133 */ 1134 if (dev->pdrv != NULL && dev->pdrv->isdrm) { 1135 pbus = pci_upstream_bridge(dev); 1136 if (pbus == NULL) 1137 return (PCI_SPEED_UNKNOWN); 1138 } else 1139 pbus = dev; 1140 1141 /* "root" may be misleading as it may not be that. */ 1142 root = pbus->dev.bsddev; 1143 1144 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1145 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1146 return (PCI_SPEED_UNKNOWN); 1147 1148 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1149 return (PCI_SPEED_UNKNOWN); 1150 1151 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1152 1153 if (lnkcap2) { /* PCIe r3.0-compliant */ 1154 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1155 return (PCIE_SPEED_2_5GT); 1156 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1157 return (PCIE_SPEED_5_0GT); 1158 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1159 return (PCIE_SPEED_8_0GT); 1160 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1161 return (PCIE_SPEED_16_0GT); 1162 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1163 return (PCIE_SPEED_32_0GT); 1164 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1165 return (PCIE_SPEED_64_0GT); 1166 } else { /* pre-r3.0 */ 1167 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1168 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1169 return (PCIE_SPEED_2_5GT); 1170 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1171 return (PCIE_SPEED_5_0GT); 1172 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1173 return (PCIE_SPEED_8_0GT); 1174 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1175 return (PCIE_SPEED_16_0GT); 1176 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1177 return (PCIE_SPEED_32_0GT); 1178 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1179 return (PCIE_SPEED_64_0GT); 1180 } 1181 return (PCI_SPEED_UNKNOWN); 1182 } 1183 1184 static inline enum pcie_link_width 1185 pcie_get_width_cap(struct pci_dev *dev) 1186 { 1187 uint32_t lnkcap; 1188 1189 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1190 if (lnkcap) 1191 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1192 1193 return (PCIE_LNK_WIDTH_UNKNOWN); 1194 } 1195 1196 static inline int 1197 pcie_get_mps(struct pci_dev *dev) 1198 { 1199 return (pci_get_max_payload(dev->dev.bsddev)); 1200 } 1201 1202 static inline uint32_t 1203 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1204 { 1205 1206 switch(spd) { 1207 case PCIE_SPEED_64_0GT: 1208 return (64000 * 128 / 130); 1209 case PCIE_SPEED_32_0GT: 1210 return (32000 * 128 / 130); 1211 case PCIE_SPEED_16_0GT: 1212 return (16000 * 128 / 130); 1213 case PCIE_SPEED_8_0GT: 1214 return (8000 * 128 / 130); 1215 case PCIE_SPEED_5_0GT: 1216 return (5000 * 8 / 10); 1217 case PCIE_SPEED_2_5GT: 1218 return (2500 * 8 / 10); 1219 default: 1220 return (0); 1221 } 1222 } 1223 1224 static inline uint32_t 1225 pcie_bandwidth_available(struct pci_dev *pdev, 1226 struct pci_dev **limiting, 1227 enum pci_bus_speed *speed, 1228 enum pcie_link_width *width) 1229 { 1230 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1231 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1232 1233 if (speed) 1234 *speed = nspeed; 1235 if (width) 1236 *width = nwidth; 1237 1238 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1239 } 1240 1241 static inline bool 1242 pcie_aspm_enabled(struct pci_dev *pdev) 1243 { 1244 return (false); 1245 } 1246 1247 static inline struct pci_dev * 1248 pcie_find_root_port(struct pci_dev *pdev) 1249 { 1250 device_t root; 1251 1252 if (pdev->root != NULL) 1253 return (pdev->root); 1254 1255 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1256 if (root == NULL) 1257 return (NULL); 1258 1259 pdev->root = lkpinew_pci_dev(root); 1260 return (pdev->root); 1261 } 1262 1263 /* This is needed when people rip out the device "HotPlug". */ 1264 static inline void 1265 pci_lock_rescan_remove(void) 1266 { 1267 } 1268 1269 static inline void 1270 pci_unlock_rescan_remove(void) 1271 { 1272 } 1273 1274 static __inline void 1275 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1276 { 1277 } 1278 1279 static inline int 1280 pci_rescan_bus(struct pci_bus *pbus) 1281 { 1282 device_t *devlist, parent; 1283 int devcount, error; 1284 1285 if (!device_is_attached(pbus->self->dev.bsddev)) 1286 return (0); 1287 /* pci_rescan_method() will work on the pcib (parent). */ 1288 error = BUS_RESCAN(pbus->self->dev.bsddev); 1289 if (error != 0) 1290 return (0); 1291 1292 parent = device_get_parent(pbus->self->dev.bsddev); 1293 error = device_get_children(parent, &devlist, &devcount); 1294 if (error != 0) 1295 return (0); 1296 if (devcount != 0) 1297 free(devlist, M_TEMP); 1298 1299 return (devcount); 1300 } 1301 1302 /* 1303 * The following functions can be used to attach/detach the LinuxKPI's 1304 * PCI device runtime. The pci_driver and pci_device_id pointer is 1305 * allowed to be NULL. Other pointers must be all valid. 1306 * The pci_dev structure should be zero-initialized before passed 1307 * to the linux_pci_attach_device function. 1308 */ 1309 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1310 const struct pci_device_id *, struct pci_dev *); 1311 extern int linux_pci_detach_device(struct pci_dev *); 1312 1313 static inline int 1314 pci_dev_present(const struct pci_device_id *cur) 1315 { 1316 while (cur != NULL && (cur->vendor || cur->device)) { 1317 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1318 return (1); 1319 } 1320 cur++; 1321 } 1322 return (0); 1323 } 1324 1325 static inline const struct pci_device_id * 1326 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 1327 { 1328 if (ids == NULL) 1329 return (NULL); 1330 1331 for (; 1332 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0; 1333 ids++) 1334 if ((ids->vendor == PCI_ANY_ID || 1335 ids->vendor == pdev->vendor) && 1336 (ids->device == PCI_ANY_ID || 1337 ids->device == pdev->device) && 1338 (ids->subvendor == PCI_ANY_ID || 1339 ids->subvendor == pdev->subsystem_vendor) && 1340 (ids->subdevice == PCI_ANY_ID || 1341 ids->subdevice == pdev->subsystem_device) && 1342 ((ids->class ^ pdev->class) & ids->class_mask) == 0) 1343 return (ids); 1344 1345 return (NULL); 1346 } 1347 1348 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1349 unsigned int bus, unsigned int devfn); 1350 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1351 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1352 1353 struct pci_dev *lkpi_pci_get_slot(struct pci_bus *, unsigned int); 1354 #ifndef WANT_NATIVE_PCI_GET_SLOT 1355 #define pci_get_slot(_pbus, _devfn) \ 1356 lkpi_pci_get_slot(_pbus, _devfn) 1357 #endif 1358 1359 static inline int 1360 pci_domain_nr(struct pci_bus *pbus) 1361 { 1362 1363 return (pbus->domain); 1364 } 1365 1366 static inline int 1367 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1368 int pos, uint32_t *val, int len) 1369 { 1370 1371 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1372 return (0); 1373 } 1374 1375 static inline int 1376 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1377 { 1378 uint32_t tmp; 1379 int ret; 1380 1381 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1382 *val = (u16)tmp; 1383 return (ret); 1384 } 1385 1386 static inline int 1387 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1388 { 1389 uint32_t tmp; 1390 int ret; 1391 1392 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1393 *val = (u8)tmp; 1394 return (ret); 1395 } 1396 1397 static inline int 1398 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1399 uint32_t val, int size) 1400 { 1401 1402 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1403 return (0); 1404 } 1405 1406 static inline int 1407 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1408 uint8_t val) 1409 { 1410 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1411 } 1412 1413 static inline int 1414 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1415 uint16_t val) 1416 { 1417 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1418 } 1419 1420 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1421 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1422 struct pci_dev *lkpi_pci_get_base_class(unsigned int class, 1423 struct pci_dev *from); 1424 #define pci_get_base_class(class, from) lkpi_pci_get_base_class(class, from) 1425 1426 /* -------------------------------------------------------------------------- */ 1427 1428 #define pcim_enable_device(pdev) \ 1429 linuxkpi_pcim_enable_device(pdev) 1430 #define pcim_iomap_table(pdev) \ 1431 linuxkpi_pcim_iomap_table(pdev) 1432 #define pcim_iomap_regions(pdev, mask, name) \ 1433 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1434 1435 static inline int 1436 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1437 { 1438 uint32_t requests, req_mask; 1439 int bar, error; 1440 1441 /* Request all the BARs ("regions") we do not iomap. */ 1442 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1443 for (bar = requests = 0; requests != req_mask; bar++) { 1444 if ((req_mask & (1 << bar)) == 0) 1445 continue; 1446 error = pci_request_region(pdev, bar, name); 1447 if (error != 0 && error != -ENODEV) 1448 goto err; 1449 requests |= (1 << bar); 1450 } 1451 1452 error = pcim_iomap_regions(pdev, mask, name); 1453 if (error != 0) 1454 goto err; 1455 1456 return (0); 1457 1458 err: 1459 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1460 if ((requests & (1 << bar)) != 0) 1461 pci_release_region(pdev, bar); 1462 } 1463 1464 return (-EINVAL); 1465 } 1466 1467 /* 1468 * We cannot simply re-define pci_get_device() as we would normally do 1469 * and then hide it in linux_pci.c as too many semi-native drivers still 1470 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1471 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1472 */ 1473 static inline struct pci_dev * 1474 linuxkpi_pci_get_device(uint32_t vendor, uint32_t device, struct pci_dev *odev) 1475 { 1476 1477 return (lkpi_pci_get_device(vendor, device, odev)); 1478 } 1479 1480 #define for_each_pci_dev(_pdev) \ 1481 while ((_pdev = linuxkpi_pci_get_device(PCI_ANY_ID, PCI_ANY_ID, _pdev)) != NULL) 1482 1483 /* This is a FreeBSD extension so we can use bus_*(). */ 1484 static inline void 1485 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1486 { 1487 pdev->want_iomap_res = true; 1488 } 1489 1490 static inline bool 1491 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1492 { 1493 1494 return (false); 1495 } 1496 1497 static inline void * 1498 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1499 { 1500 1501 return (NULL); 1502 } 1503 1504 static inline void 1505 pci_ignore_hotplug(struct pci_dev *pdev) 1506 { 1507 } 1508 1509 static inline const char * 1510 pci_power_name(pci_power_t state) 1511 { 1512 int pstate = state + 1; 1513 1514 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1515 return (pci_power_names[pstate]); 1516 else 1517 return (pci_power_names[0]); 1518 } 1519 1520 static inline int 1521 pcie_get_readrq(struct pci_dev *dev) 1522 { 1523 u16 ctl; 1524 1525 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1526 return (-EINVAL); 1527 1528 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1529 } 1530 1531 static inline bool 1532 pci_is_enabled(struct pci_dev *pdev) 1533 { 1534 1535 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1536 PCIM_CMD_BUSMASTEREN) != 0); 1537 } 1538 1539 static inline int 1540 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1541 { 1542 1543 return (0); 1544 } 1545 1546 static inline int 1547 pci_assign_resource(struct pci_dev *pdev, int bar) 1548 { 1549 1550 return (0); 1551 } 1552 1553 static inline int 1554 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1555 { 1556 1557 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1558 if (vector != 0) 1559 return (-EINVAL); 1560 return (pdev->irq); 1561 } 1562 1563 if (pdev->msix_enabled || pdev->msi_enabled) { 1564 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1565 return (-EINVAL); 1566 return (pdev->dev.irq_start + vector); 1567 } 1568 1569 return (-ENXIO); 1570 } 1571 1572 static inline int 1573 pci_wake_from_d3(struct pci_dev *pdev, bool enable) 1574 { 1575 1576 pr_debug("%s: TODO\n", __func__); 1577 return (0); 1578 } 1579 1580 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1581