1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/pciio.h> 41 #include <sys/rman.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pci_private.h> 45 46 #include <machine/resource.h> 47 48 #include <linux/list.h> 49 #include <linux/dmapool.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/compiler.h> 52 #include <linux/errno.h> 53 #include <asm/atomic.h> 54 #include <linux/device.h> 55 56 struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class_mask; 62 uintptr_t driver_data; 63 }; 64 65 #define MODULE_DEVICE_TABLE(bus, table) 66 #define PCI_ANY_ID (-1) 67 #define PCI_VENDOR_ID_APPLE 0x106b 68 #define PCI_VENDOR_ID_ASUSTEK 0x1043 69 #define PCI_VENDOR_ID_ATI 0x1002 70 #define PCI_VENDOR_ID_DELL 0x1028 71 #define PCI_VENDOR_ID_HP 0x103c 72 #define PCI_VENDOR_ID_IBM 0x1014 73 #define PCI_VENDOR_ID_INTEL 0x8086 74 #define PCI_VENDOR_ID_MELLANOX 0x15b3 75 #define PCI_VENDOR_ID_SERVERWORKS 0x1166 76 #define PCI_VENDOR_ID_SONY 0x104d 77 #define PCI_VENDOR_ID_TOPSPIN 0x1867 78 #define PCI_VENDOR_ID_VIA 0x1106 79 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 80 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 81 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 82 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 83 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 84 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 85 86 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 87 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 88 #define PCI_FUNC(devfn) ((devfn) & 0x07) 89 90 #define PCI_VDEVICE(_vendor, _device) \ 91 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 92 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 93 #define PCI_DEVICE(_vendor, _device) \ 94 .vendor = (_vendor), .device = (_device), \ 95 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 96 97 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 98 99 #define PCI_VENDOR_ID PCIR_DEVVENDOR 100 #define PCI_COMMAND PCIR_COMMAND 101 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 102 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 103 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 104 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 105 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 106 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 107 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 108 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 109 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 110 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 111 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 112 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 113 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 114 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 115 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 116 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 117 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 118 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 119 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 120 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 121 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 122 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 123 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 124 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 125 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 126 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 127 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 128 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 129 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 130 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 131 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 132 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 133 134 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 135 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 136 #define PCI_EXP_DEVSTA_TRPND 0x0020 137 138 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 139 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 140 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 141 142 enum pci_bus_speed { 143 PCI_SPEED_UNKNOWN = -1, 144 PCIE_SPEED_2_5GT, 145 PCIE_SPEED_5_0GT, 146 PCIE_SPEED_8_0GT, 147 }; 148 149 enum pcie_link_width { 150 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 151 }; 152 153 typedef int pci_power_t; 154 155 #define PCI_D0 PCI_POWERSTATE_D0 156 #define PCI_D1 PCI_POWERSTATE_D1 157 #define PCI_D2 PCI_POWERSTATE_D2 158 #define PCI_D3hot PCI_POWERSTATE_D3 159 #define PCI_D3cold 4 160 161 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 162 163 struct pci_dev; 164 165 struct pci_driver { 166 struct list_head links; 167 char *name; 168 const struct pci_device_id *id_table; 169 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 170 void (*remove)(struct pci_dev *dev); 171 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 172 int (*resume) (struct pci_dev *dev); /* Device woken up */ 173 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 174 driver_t driver; 175 devclass_t bsdclass; 176 const struct pci_error_handlers *err_handler; 177 }; 178 179 extern struct list_head pci_drivers; 180 extern struct list_head pci_devices; 181 extern spinlock_t pci_lock; 182 183 #define __devexit_p(x) x 184 185 struct pci_dev { 186 struct device dev; 187 struct list_head links; 188 struct pci_driver *pdrv; 189 uint64_t dma_mask; 190 uint16_t device; 191 uint16_t vendor; 192 unsigned int irq; 193 unsigned int devfn; 194 u8 revision; 195 }; 196 197 static inline struct resource_list_entry * 198 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 199 { 200 struct pci_devinfo *dinfo; 201 struct resource_list *rl; 202 203 dinfo = device_get_ivars(pdev->dev.bsddev); 204 rl = &dinfo->resources; 205 return resource_list_find(rl, type, rid); 206 } 207 208 static inline struct resource_list_entry * 209 linux_pci_get_bar(struct pci_dev *pdev, int bar) 210 { 211 struct resource_list_entry *rle; 212 213 bar = PCIR_BAR(bar); 214 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 215 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 216 return (rle); 217 } 218 219 static inline struct device * 220 linux_pci_find_irq_dev(unsigned int irq) 221 { 222 struct pci_dev *pdev; 223 struct device *found; 224 225 found = NULL; 226 spin_lock(&pci_lock); 227 list_for_each_entry(pdev, &pci_devices, links) { 228 if (irq == pdev->dev.irq || 229 (irq >= pdev->dev.msix && irq < pdev->dev.msix_max)) { 230 found = &pdev->dev; 231 break; 232 } 233 } 234 spin_unlock(&pci_lock); 235 return (found); 236 } 237 238 static inline unsigned long 239 pci_resource_start(struct pci_dev *pdev, int bar) 240 { 241 struct resource_list_entry *rle; 242 243 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 244 return (0); 245 return rle->start; 246 } 247 248 static inline unsigned long 249 pci_resource_len(struct pci_dev *pdev, int bar) 250 { 251 struct resource_list_entry *rle; 252 253 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 254 return (0); 255 return rle->count; 256 } 257 258 static inline int 259 pci_resource_type(struct pci_dev *pdev, int bar) 260 { 261 struct pci_map *pm; 262 263 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 264 if (!pm) 265 return (-1); 266 267 if (PCI_BAR_IO(pm->pm_value)) 268 return (SYS_RES_IOPORT); 269 else 270 return (SYS_RES_MEMORY); 271 } 272 273 /* 274 * All drivers just seem to want to inspect the type not flags. 275 */ 276 static inline int 277 pci_resource_flags(struct pci_dev *pdev, int bar) 278 { 279 int type; 280 281 type = pci_resource_type(pdev, bar); 282 if (type < 0) 283 return (0); 284 return (1 << type); 285 } 286 287 static inline const char * 288 pci_name(struct pci_dev *d) 289 { 290 291 return device_get_desc(d->dev.bsddev); 292 } 293 294 static inline void * 295 pci_get_drvdata(struct pci_dev *pdev) 296 { 297 298 return dev_get_drvdata(&pdev->dev); 299 } 300 301 static inline void 302 pci_set_drvdata(struct pci_dev *pdev, void *data) 303 { 304 305 dev_set_drvdata(&pdev->dev, data); 306 } 307 308 static inline int 309 pci_enable_device(struct pci_dev *pdev) 310 { 311 312 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 313 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 314 return (0); 315 } 316 317 static inline void 318 pci_disable_device(struct pci_dev *pdev) 319 { 320 } 321 322 static inline int 323 pci_set_master(struct pci_dev *pdev) 324 { 325 326 pci_enable_busmaster(pdev->dev.bsddev); 327 return (0); 328 } 329 330 static inline int 331 pci_set_power_state(struct pci_dev *pdev, int state) 332 { 333 334 pci_set_powerstate(pdev->dev.bsddev, state); 335 return (0); 336 } 337 338 static inline int 339 pci_clear_master(struct pci_dev *pdev) 340 { 341 342 pci_disable_busmaster(pdev->dev.bsddev); 343 return (0); 344 } 345 346 static inline int 347 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 348 { 349 int rid; 350 int type; 351 352 type = pci_resource_type(pdev, bar); 353 if (type < 0) 354 return (-ENODEV); 355 rid = PCIR_BAR(bar); 356 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 357 RF_ACTIVE) == NULL) 358 return (-EINVAL); 359 return (0); 360 } 361 362 static inline void 363 pci_release_region(struct pci_dev *pdev, int bar) 364 { 365 struct resource_list_entry *rle; 366 367 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 368 return; 369 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 370 } 371 372 static inline void 373 pci_release_regions(struct pci_dev *pdev) 374 { 375 int i; 376 377 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 378 pci_release_region(pdev, i); 379 } 380 381 static inline int 382 pci_request_regions(struct pci_dev *pdev, const char *res_name) 383 { 384 int error; 385 int i; 386 387 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 388 error = pci_request_region(pdev, i, res_name); 389 if (error && error != -ENODEV) { 390 pci_release_regions(pdev); 391 return (error); 392 } 393 } 394 return (0); 395 } 396 397 static inline void 398 pci_disable_msix(struct pci_dev *pdev) 399 { 400 401 pci_release_msi(pdev->dev.bsddev); 402 } 403 404 static inline bus_addr_t 405 pci_bus_address(struct pci_dev *pdev, int bar) 406 { 407 408 return (pci_resource_start(pdev, bar)); 409 } 410 411 #define PCI_CAP_ID_EXP PCIY_EXPRESS 412 #define PCI_CAP_ID_PCIX PCIY_PCIX 413 #define PCI_CAP_ID_AGP PCIY_AGP 414 #define PCI_CAP_ID_PM PCIY_PMG 415 416 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 417 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 418 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 419 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 420 #define PCI_EXP_LNKSTA PCIER_LINK_STA 421 422 static inline int 423 pci_find_capability(struct pci_dev *pdev, int capid) 424 { 425 int reg; 426 427 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 428 return (0); 429 return (reg); 430 } 431 432 static inline int pci_pcie_cap(struct pci_dev *dev) 433 { 434 return pci_find_capability(dev, PCI_CAP_ID_EXP); 435 } 436 437 438 static inline int 439 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 440 { 441 442 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 443 return (0); 444 } 445 446 static inline int 447 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 448 { 449 450 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 451 return (0); 452 } 453 454 static inline int 455 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 456 { 457 458 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 459 return (0); 460 } 461 462 static inline int 463 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 464 { 465 466 pci_write_config(pdev->dev.bsddev, where, val, 1); 467 return (0); 468 } 469 470 static inline int 471 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 472 { 473 474 pci_write_config(pdev->dev.bsddev, where, val, 2); 475 return (0); 476 } 477 478 static inline int 479 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 480 { 481 482 pci_write_config(pdev->dev.bsddev, where, val, 4); 483 return (0); 484 } 485 486 extern int pci_register_driver(struct pci_driver *pdrv); 487 extern void pci_unregister_driver(struct pci_driver *pdrv); 488 489 struct msix_entry { 490 int entry; 491 int vector; 492 }; 493 494 /* 495 * Enable msix, positive errors indicate actual number of available 496 * vectors. Negative errors are failures. 497 * 498 * NB: define added to prevent this definition of pci_enable_msix from 499 * clashing with the native FreeBSD version. 500 */ 501 #define pci_enable_msix linux_pci_enable_msix 502 static inline int 503 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 504 { 505 struct resource_list_entry *rle; 506 int error; 507 int avail; 508 int i; 509 510 avail = pci_msix_count(pdev->dev.bsddev); 511 if (avail < nreq) { 512 if (avail == 0) 513 return -EINVAL; 514 return avail; 515 } 516 avail = nreq; 517 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 518 return error; 519 /* 520 * Handle case where "pci_alloc_msix()" may allocate less 521 * interrupts than available and return with no error: 522 */ 523 if (avail < nreq) { 524 pci_release_msi(pdev->dev.bsddev); 525 return avail; 526 } 527 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 528 pdev->dev.msix = rle->start; 529 pdev->dev.msix_max = rle->start + avail; 530 for (i = 0; i < nreq; i++) 531 entries[i].vector = pdev->dev.msix + i; 532 return (0); 533 } 534 535 #define pci_enable_msix_range linux_pci_enable_msix_range 536 static inline int 537 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 538 int minvec, int maxvec) 539 { 540 int nvec = maxvec; 541 int rc; 542 543 if (maxvec < minvec) 544 return (-ERANGE); 545 546 do { 547 rc = pci_enable_msix(dev, entries, nvec); 548 if (rc < 0) { 549 return (rc); 550 } else if (rc > 0) { 551 if (rc < minvec) 552 return (-ENOSPC); 553 nvec = rc; 554 } 555 } while (rc); 556 return (nvec); 557 } 558 559 static inline int pci_channel_offline(struct pci_dev *pdev) 560 { 561 return false; 562 } 563 564 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 565 { 566 return -ENODEV; 567 } 568 static inline void pci_disable_sriov(struct pci_dev *dev) 569 { 570 } 571 572 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 573 const struct pci_device_id _table[] __devinitdata 574 575 576 /* XXX This should not be necessary. */ 577 #define pcix_set_mmrbc(d, v) 0 578 #define pcix_get_max_mmrbc(d) 0 579 #define pcie_set_readrq(d, v) 0 580 581 #define PCI_DMA_BIDIRECTIONAL 0 582 #define PCI_DMA_TODEVICE 1 583 #define PCI_DMA_FROMDEVICE 2 584 #define PCI_DMA_NONE 3 585 586 #define pci_pool dma_pool 587 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 588 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 589 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 590 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 591 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 592 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 593 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 594 _size, _vaddr, _dma_handle) 595 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 596 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 597 _sg, _nents, (enum dma_data_direction)_dir) 598 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 599 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 600 (_ptr), (_size), (enum dma_data_direction)_dir) 601 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 602 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 603 _addr, _size, (enum dma_data_direction)_dir) 604 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 605 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 606 _sg, _nents, (enum dma_data_direction)_dir) 607 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 608 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 609 _offset, _size, (enum dma_data_direction)_dir) 610 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 611 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 612 _dma_address, _size, (enum dma_data_direction)_dir) 613 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 614 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 615 dma_mapping_error(&(_pdev)->dev, _dma_addr) 616 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 617 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 618 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 619 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 620 #define pci_unmap_addr dma_unmap_addr 621 #define pci_unmap_addr_set dma_unmap_addr_set 622 #define pci_unmap_len dma_unmap_len 623 #define pci_unmap_len_set dma_unmap_len_set 624 625 typedef unsigned int __bitwise pci_channel_state_t; 626 typedef unsigned int __bitwise pci_ers_result_t; 627 628 enum pci_channel_state { 629 pci_channel_io_normal = 1, 630 pci_channel_io_frozen = 2, 631 pci_channel_io_perm_failure = 3, 632 }; 633 634 enum pci_ers_result { 635 PCI_ERS_RESULT_NONE = 1, 636 PCI_ERS_RESULT_CAN_RECOVER = 2, 637 PCI_ERS_RESULT_NEED_RESET = 3, 638 PCI_ERS_RESULT_DISCONNECT = 4, 639 PCI_ERS_RESULT_RECOVERED = 5, 640 }; 641 642 643 /* PCI bus error event callbacks */ 644 struct pci_error_handlers { 645 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 646 enum pci_channel_state error); 647 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 648 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 649 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 650 void (*resume)(struct pci_dev *dev); 651 }; 652 653 /* FreeBSD does not support SRIOV - yet */ 654 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 655 { 656 return dev; 657 } 658 659 static inline bool pci_is_pcie(struct pci_dev *dev) 660 { 661 return !!pci_pcie_cap(dev); 662 } 663 664 static inline u16 pcie_flags_reg(struct pci_dev *dev) 665 { 666 int pos; 667 u16 reg16; 668 669 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 670 if (!pos) 671 return 0; 672 673 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 674 675 return reg16; 676 } 677 678 679 static inline int pci_pcie_type(struct pci_dev *dev) 680 { 681 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 682 } 683 684 static inline int pcie_cap_version(struct pci_dev *dev) 685 { 686 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 687 } 688 689 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 690 { 691 int type = pci_pcie_type(dev); 692 693 return pcie_cap_version(dev) > 1 || 694 type == PCI_EXP_TYPE_ROOT_PORT || 695 type == PCI_EXP_TYPE_ENDPOINT || 696 type == PCI_EXP_TYPE_LEG_END; 697 } 698 699 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 700 { 701 return true; 702 } 703 704 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 705 { 706 int type = pci_pcie_type(dev); 707 708 return pcie_cap_version(dev) > 1 || 709 type == PCI_EXP_TYPE_ROOT_PORT || 710 (type == PCI_EXP_TYPE_DOWNSTREAM && 711 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 712 } 713 714 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 715 { 716 int type = pci_pcie_type(dev); 717 718 return pcie_cap_version(dev) > 1 || 719 type == PCI_EXP_TYPE_ROOT_PORT || 720 type == PCI_EXP_TYPE_RC_EC; 721 } 722 723 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 724 { 725 if (!pci_is_pcie(dev)) 726 return false; 727 728 switch (pos) { 729 case PCI_EXP_FLAGS_TYPE: 730 return true; 731 case PCI_EXP_DEVCAP: 732 case PCI_EXP_DEVCTL: 733 case PCI_EXP_DEVSTA: 734 return pcie_cap_has_devctl(dev); 735 case PCI_EXP_LNKCAP: 736 case PCI_EXP_LNKCTL: 737 case PCI_EXP_LNKSTA: 738 return pcie_cap_has_lnkctl(dev); 739 case PCI_EXP_SLTCAP: 740 case PCI_EXP_SLTCTL: 741 case PCI_EXP_SLTSTA: 742 return pcie_cap_has_sltctl(dev); 743 case PCI_EXP_RTCTL: 744 case PCI_EXP_RTCAP: 745 case PCI_EXP_RTSTA: 746 return pcie_cap_has_rtctl(dev); 747 case PCI_EXP_DEVCAP2: 748 case PCI_EXP_DEVCTL2: 749 case PCI_EXP_LNKCAP2: 750 case PCI_EXP_LNKCTL2: 751 case PCI_EXP_LNKSTA2: 752 return pcie_cap_version(dev) > 1; 753 default: 754 return false; 755 } 756 } 757 758 static inline int 759 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 760 { 761 if (pos & 3) 762 return -EINVAL; 763 764 if (!pcie_capability_reg_implemented(dev, pos)) 765 return -EINVAL; 766 767 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 768 } 769 770 static inline int 771 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 772 { 773 if (pos & 3) 774 return -EINVAL; 775 776 if (!pcie_capability_reg_implemented(dev, pos)) 777 return -EINVAL; 778 779 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 780 } 781 782 static inline int 783 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 784 { 785 if (pos & 1) 786 return -EINVAL; 787 788 if (!pcie_capability_reg_implemented(dev, pos)) 789 return 0; 790 791 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 792 } 793 794 static inline int pcie_get_minimum_link(struct pci_dev *dev, 795 enum pci_bus_speed *speed, enum pcie_link_width *width) 796 { 797 *speed = PCI_SPEED_UNKNOWN; 798 *width = PCIE_LNK_WIDTH_UNKNOWN; 799 return (0); 800 } 801 802 static inline int 803 pci_num_vf(struct pci_dev *dev) 804 { 805 return (0); 806 } 807 808 #endif /* _LINUX_PCI_H_ */ 809