1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/nv.h> 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 74 #define MODULE_DEVICE_TABLE(_bus, _table) \ 75 \ 76 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 77 DEVMETHOD_END \ 78 }; \ 79 \ 80 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 81 "lkpi_" #_bus #_table, \ 82 _ ## _bus ## _ ## _table ## _methods, \ 83 0 \ 84 }; \ 85 \ 86 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 87 0, 0); \ 88 \ 89 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 90 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 91 92 #define PCI_ANY_ID -1U 93 94 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 95 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 96 #define PCI_FUNC(devfn) ((devfn) & 0x07) 97 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 98 99 #define PCI_VDEVICE(_vendor, _device) \ 100 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 101 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 102 #define PCI_DEVICE(_vendor, _device) \ 103 .vendor = (_vendor), .device = (_device), \ 104 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 105 106 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 107 108 #define PCI_VENDOR_ID PCIR_DEVVENDOR 109 #define PCI_COMMAND PCIR_COMMAND 110 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 111 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 112 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 113 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 114 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 115 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 116 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 117 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 118 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 119 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 120 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 121 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 122 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 123 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 124 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 125 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 126 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 127 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 128 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 129 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 130 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 131 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 132 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 133 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 134 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 135 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 136 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 137 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 138 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 139 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 140 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 141 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 142 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 143 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 144 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 145 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 146 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 147 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 148 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 149 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 150 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 151 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 152 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 153 #define PCI_EXP_LNKCTL2_TLS 0x000f 154 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 155 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 156 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 157 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 158 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 159 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 160 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 161 162 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 163 #define PCI_EXP_DEVSTA_TRPND 0x0020 164 165 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 166 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 167 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 168 169 enum pci_bus_speed { 170 PCI_SPEED_UNKNOWN = -1, 171 PCIE_SPEED_2_5GT, 172 PCIE_SPEED_5_0GT, 173 PCIE_SPEED_8_0GT, 174 PCIE_SPEED_16_0GT, 175 }; 176 177 enum pcie_link_width { 178 PCIE_LNK_WIDTH_RESRV = 0x00, 179 PCIE_LNK_X1 = 0x01, 180 PCIE_LNK_X2 = 0x02, 181 PCIE_LNK_X4 = 0x04, 182 PCIE_LNK_X8 = 0x08, 183 PCIE_LNK_X12 = 0x0c, 184 PCIE_LNK_X16 = 0x10, 185 PCIE_LNK_X32 = 0x20, 186 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 187 }; 188 189 #define PCIE_LINK_STATE_L0S 0x00000001 190 #define PCIE_LINK_STATE_L1 0x00000002 191 #define PCIE_LINK_STATE_CLKPM 0x00000004 192 193 typedef int pci_power_t; 194 195 #define PCI_D0 PCI_POWERSTATE_D0 196 #define PCI_D1 PCI_POWERSTATE_D1 197 #define PCI_D2 PCI_POWERSTATE_D2 198 #define PCI_D3hot PCI_POWERSTATE_D3 199 #define PCI_D3cold 4 200 201 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 202 203 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 204 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 205 206 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 207 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 208 209 #define PCI_L1SS_CTL1 0x8 210 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 211 212 #define PCI_IRQ_LEGACY 0x01 213 #define PCI_IRQ_MSI 0x02 214 #define PCI_IRQ_MSIX 0x04 215 216 struct pci_dev; 217 218 struct pci_driver { 219 struct list_head node; 220 char *name; 221 const struct pci_device_id *id_table; 222 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 223 void (*remove)(struct pci_dev *dev); 224 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 225 int (*resume) (struct pci_dev *dev); /* Device woken up */ 226 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 227 driver_t bsddriver; 228 devclass_t bsdclass; 229 struct device_driver driver; 230 const struct pci_error_handlers *err_handler; 231 bool isdrm; 232 int bsd_probe_return; 233 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 234 const nvlist_t *pf_config); 235 void (*bsd_iov_uninit)(device_t dev); 236 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 237 const nvlist_t *vf_config); 238 }; 239 240 struct pci_bus { 241 struct pci_dev *self; 242 int domain; 243 int number; 244 }; 245 246 extern struct list_head pci_drivers; 247 extern struct list_head pci_devices; 248 extern spinlock_t pci_lock; 249 250 #define __devexit_p(x) x 251 252 #define module_pci_driver(_driver) \ 253 \ 254 static inline int \ 255 _pci_init(void) \ 256 { \ 257 \ 258 return (linux_pci_register_driver(&_driver)); \ 259 } \ 260 \ 261 static inline void \ 262 _pci_exit(void) \ 263 { \ 264 \ 265 linux_pci_unregister_driver(&_driver); \ 266 } \ 267 \ 268 module_init(_pci_init); \ 269 module_exit(_pci_exit) 270 271 /* 272 * If we find drivers accessing this from multiple KPIs we may have to 273 * refcount objects of this structure. 274 */ 275 struct pci_mmio_region { 276 TAILQ_ENTRY(pci_mmio_region) next; 277 struct resource *res; 278 int rid; 279 int type; 280 }; 281 282 struct pci_dev { 283 struct device dev; 284 struct list_head links; 285 struct pci_driver *pdrv; 286 struct pci_bus *bus; 287 struct pci_dev *root; 288 uint16_t device; 289 uint16_t vendor; 290 uint16_t subsystem_vendor; 291 uint16_t subsystem_device; 292 unsigned int irq; 293 unsigned int devfn; 294 uint32_t class; 295 uint8_t revision; 296 bool managed; /* devres "pcim_*(). */ 297 bool want_iomap_res; 298 bool msi_enabled; 299 bool msix_enabled; 300 phys_addr_t rom; 301 size_t romlen; 302 303 TAILQ_HEAD(, pci_mmio_region) mmio; 304 }; 305 306 /* We need some meta-struct to keep track of these for devres. */ 307 struct pci_devres { 308 bool enable_io; 309 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 310 uint8_t region_mask; 311 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 312 }; 313 struct pcim_iomap_devres { 314 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 315 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 316 }; 317 318 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 319 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 320 unsigned int flags); 321 322 /* Internal helper function(s). */ 323 struct pci_dev *lkpinew_pci_dev(device_t); 324 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev); 325 void lkpi_pci_devres_release(struct device *, void *); 326 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size); 327 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev); 328 void lkpi_pcim_iomap_table_release(struct device *, void *); 329 330 static inline int 331 pci_resource_type(struct pci_dev *pdev, int bar) 332 { 333 struct pci_map *pm; 334 335 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 336 if (!pm) 337 return (-1); 338 339 if (PCI_BAR_IO(pm->pm_value)) 340 return (SYS_RES_IOPORT); 341 else 342 return (SYS_RES_MEMORY); 343 } 344 345 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 346 struct resource_list *rl, int type, int rid); 347 348 static inline struct resource_list_entry * 349 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 350 { 351 struct pci_devinfo *dinfo; 352 struct resource_list *rl; 353 struct resource_list_entry *rle; 354 355 dinfo = device_get_ivars(pdev->dev.bsddev); 356 rl = &dinfo->resources; 357 rle = resource_list_find(rl, type, rid); 358 /* Reserve resources for this BAR if needed. */ 359 if (rle == NULL && reserve_bar) 360 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 361 return (rle); 362 } 363 364 static inline struct resource_list_entry * 365 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 366 { 367 int type; 368 369 type = pci_resource_type(pdev, bar); 370 if (type < 0) 371 return (NULL); 372 bar = PCIR_BAR(bar); 373 return (linux_pci_get_rle(pdev, type, bar, reserve)); 374 } 375 376 static inline struct device * 377 linux_pci_find_irq_dev(unsigned int irq) 378 { 379 struct pci_dev *pdev; 380 struct device *found; 381 382 found = NULL; 383 spin_lock(&pci_lock); 384 list_for_each_entry(pdev, &pci_devices, links) { 385 if (irq == pdev->dev.irq || 386 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 387 found = &pdev->dev; 388 break; 389 } 390 } 391 spin_unlock(&pci_lock); 392 return (found); 393 } 394 395 /* 396 * All drivers just seem to want to inspect the type not flags. 397 */ 398 static inline int 399 pci_resource_flags(struct pci_dev *pdev, int bar) 400 { 401 int type; 402 403 type = pci_resource_type(pdev, bar); 404 if (type < 0) 405 return (0); 406 return (1 << type); 407 } 408 409 static inline const char * 410 pci_name(struct pci_dev *d) 411 { 412 413 return device_get_desc(d->dev.bsddev); 414 } 415 416 static inline void * 417 pci_get_drvdata(struct pci_dev *pdev) 418 { 419 420 return dev_get_drvdata(&pdev->dev); 421 } 422 423 static inline void 424 pci_set_drvdata(struct pci_dev *pdev, void *data) 425 { 426 427 dev_set_drvdata(&pdev->dev, data); 428 } 429 430 static inline struct pci_dev * 431 pci_dev_get(struct pci_dev *pdev) 432 { 433 434 if (pdev != NULL) 435 get_device(&pdev->dev); 436 return (pdev); 437 } 438 439 static __inline void 440 pci_dev_put(struct pci_dev *pdev) 441 { 442 443 if (pdev != NULL) 444 put_device(&pdev->dev); 445 } 446 447 static inline int 448 pci_enable_device(struct pci_dev *pdev) 449 { 450 451 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 452 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 453 return (0); 454 } 455 456 static inline void 457 pci_disable_device(struct pci_dev *pdev) 458 { 459 460 pci_disable_busmaster(pdev->dev.bsddev); 461 } 462 463 static inline int 464 pci_set_master(struct pci_dev *pdev) 465 { 466 467 pci_enable_busmaster(pdev->dev.bsddev); 468 return (0); 469 } 470 471 static inline int 472 pci_set_power_state(struct pci_dev *pdev, int state) 473 { 474 475 pci_set_powerstate(pdev->dev.bsddev, state); 476 return (0); 477 } 478 479 static inline int 480 pci_clear_master(struct pci_dev *pdev) 481 { 482 483 pci_disable_busmaster(pdev->dev.bsddev); 484 return (0); 485 } 486 487 static inline bool 488 pci_is_root_bus(struct pci_bus *pbus) 489 { 490 491 return (pbus->self == NULL); 492 } 493 494 static inline struct pci_dev * 495 pci_upstream_bridge(struct pci_dev *pdev) 496 { 497 498 if (pci_is_root_bus(pdev->bus)) 499 return (NULL); 500 501 /* 502 * If we do not have a (proper) "upstream bridge" set, e.g., we point 503 * to ourselves, try to handle this case on the fly like we do 504 * for pcie_find_root_port(). 505 */ 506 if (pdev == pdev->bus->self) { 507 device_t bridge; 508 509 bridge = device_get_parent(pdev->dev.bsddev); 510 if (bridge == NULL) 511 goto done; 512 bridge = device_get_parent(bridge); 513 if (bridge == NULL) 514 goto done; 515 if (device_get_devclass(device_get_parent(bridge)) != 516 devclass_find("pci")) 517 goto done; 518 519 /* 520 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 521 * for it so it can be returned. 522 */ 523 pdev->bus->self = lkpinew_pci_dev(bridge); 524 } 525 done: 526 return (pdev->bus->self); 527 } 528 529 static inline struct pci_devres * 530 lkpi_pci_devres_find(struct pci_dev *pdev) 531 { 532 533 if (!pdev->managed) 534 return (NULL); 535 536 return (lkpi_pci_devres_get_alloc(pdev)); 537 } 538 539 static inline void 540 pci_release_region(struct pci_dev *pdev, int bar) 541 { 542 struct resource_list_entry *rle; 543 struct pci_devres *dr; 544 struct pci_mmio_region *mmio, *p; 545 546 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 547 return; 548 549 /* 550 * As we implicitly track the requests we also need to clear them on 551 * release. Do clear before resource release. 552 */ 553 dr = lkpi_pci_devres_find(pdev); 554 if (dr != NULL) { 555 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 556 " region_table res %p != rel->res %p\n", __func__, pdev, 557 bar, dr->region_table[bar], rle->res)); 558 dr->region_table[bar] = NULL; 559 dr->region_mask &= ~(1 << bar); 560 } 561 562 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 563 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 564 continue; 565 TAILQ_REMOVE(&pdev->mmio, mmio, next); 566 free(mmio, M_DEVBUF); 567 } 568 569 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 570 } 571 572 static inline void 573 pci_release_regions(struct pci_dev *pdev) 574 { 575 int i; 576 577 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 578 pci_release_region(pdev, i); 579 } 580 581 static inline int 582 pci_request_regions(struct pci_dev *pdev, const char *res_name) 583 { 584 int error; 585 int i; 586 587 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 588 error = pci_request_region(pdev, i, res_name); 589 if (error && error != -ENODEV) { 590 pci_release_regions(pdev); 591 return (error); 592 } 593 } 594 return (0); 595 } 596 597 static inline void 598 lkpi_pci_disable_msix(struct pci_dev *pdev) 599 { 600 601 pci_release_msi(pdev->dev.bsddev); 602 603 /* 604 * The MSIX IRQ numbers associated with this PCI device are no 605 * longer valid and might be re-assigned. Make sure 606 * linux_pci_find_irq_dev() does no longer see them by 607 * resetting their references to zero: 608 */ 609 pdev->dev.irq_start = 0; 610 pdev->dev.irq_end = 0; 611 pdev->msix_enabled = false; 612 } 613 /* Only for consistency. No conflict on that one. */ 614 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 615 616 static inline void 617 lkpi_pci_disable_msi(struct pci_dev *pdev) 618 { 619 620 pci_release_msi(pdev->dev.bsddev); 621 622 pdev->dev.irq_start = 0; 623 pdev->dev.irq_end = 0; 624 pdev->irq = pdev->dev.irq; 625 pdev->msi_enabled = false; 626 } 627 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 628 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 629 630 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 631 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 632 633 static inline bus_addr_t 634 pci_bus_address(struct pci_dev *pdev, int bar) 635 { 636 637 return (pci_resource_start(pdev, bar)); 638 } 639 640 #define PCI_CAP_ID_EXP PCIY_EXPRESS 641 #define PCI_CAP_ID_PCIX PCIY_PCIX 642 #define PCI_CAP_ID_AGP PCIY_AGP 643 #define PCI_CAP_ID_PM PCIY_PMG 644 645 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 646 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 647 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 648 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 649 #define PCI_EXP_LNKSTA PCIER_LINK_STA 650 651 static inline int 652 pci_find_capability(struct pci_dev *pdev, int capid) 653 { 654 int reg; 655 656 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 657 return (0); 658 return (reg); 659 } 660 661 static inline int pci_pcie_cap(struct pci_dev *dev) 662 { 663 return pci_find_capability(dev, PCI_CAP_ID_EXP); 664 } 665 666 static inline int 667 pci_find_ext_capability(struct pci_dev *pdev, int capid) 668 { 669 int reg; 670 671 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 672 return (0); 673 return (reg); 674 } 675 676 #define PCIM_PCAP_PME_SHIFT 11 677 static __inline bool 678 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 679 { 680 struct pci_devinfo *dinfo; 681 pcicfgregs *cfg; 682 683 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 684 return (false); 685 686 dinfo = device_get_ivars(pdev->dev.bsddev); 687 cfg = &dinfo->cfg; 688 689 if (cfg->pp.pp_cap == 0) 690 return (false); 691 692 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 693 return (true); 694 695 return (false); 696 } 697 698 static inline int 699 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 700 { 701 702 if (!pci_enable_aspm) 703 return (-EPERM); 704 705 return (-ENXIO); 706 } 707 708 static inline int 709 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 710 { 711 712 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 713 return (0); 714 } 715 716 static inline int 717 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 718 { 719 720 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 721 return (0); 722 } 723 724 static inline int 725 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 726 { 727 728 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 729 return (0); 730 } 731 732 static inline int 733 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 734 { 735 736 pci_write_config(pdev->dev.bsddev, where, val, 1); 737 return (0); 738 } 739 740 static inline int 741 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 742 { 743 744 pci_write_config(pdev->dev.bsddev, where, val, 2); 745 return (0); 746 } 747 748 static inline int 749 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 750 { 751 752 pci_write_config(pdev->dev.bsddev, where, val, 4); 753 return (0); 754 } 755 756 int linux_pci_register_driver(struct pci_driver *pdrv); 757 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 758 void linux_pci_unregister_driver(struct pci_driver *pdrv); 759 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 760 761 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 762 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 763 764 struct msix_entry { 765 int entry; 766 int vector; 767 }; 768 769 /* 770 * Enable msix, positive errors indicate actual number of available 771 * vectors. Negative errors are failures. 772 * 773 * NB: define added to prevent this definition of pci_enable_msix from 774 * clashing with the native FreeBSD version. 775 */ 776 #define pci_enable_msix(...) \ 777 linux_pci_enable_msix(__VA_ARGS__) 778 779 static inline int 780 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 781 { 782 struct resource_list_entry *rle; 783 int error; 784 int avail; 785 int i; 786 787 avail = pci_msix_count(pdev->dev.bsddev); 788 if (avail < nreq) { 789 if (avail == 0) 790 return -EINVAL; 791 return avail; 792 } 793 avail = nreq; 794 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 795 return error; 796 /* 797 * Handle case where "pci_alloc_msix()" may allocate less 798 * interrupts than available and return with no error: 799 */ 800 if (avail < nreq) { 801 pci_release_msi(pdev->dev.bsddev); 802 return avail; 803 } 804 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 805 pdev->dev.irq_start = rle->start; 806 pdev->dev.irq_end = rle->start + avail; 807 for (i = 0; i < nreq; i++) 808 entries[i].vector = pdev->dev.irq_start + i; 809 pdev->msix_enabled = true; 810 return (0); 811 } 812 813 #define pci_enable_msix_range(...) \ 814 linux_pci_enable_msix_range(__VA_ARGS__) 815 816 static inline int 817 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 818 int minvec, int maxvec) 819 { 820 int nvec = maxvec; 821 int rc; 822 823 if (maxvec < minvec) 824 return (-ERANGE); 825 826 do { 827 rc = pci_enable_msix(dev, entries, nvec); 828 if (rc < 0) { 829 return (rc); 830 } else if (rc > 0) { 831 if (rc < minvec) 832 return (-ENOSPC); 833 nvec = rc; 834 } 835 } while (rc); 836 return (nvec); 837 } 838 839 #define pci_enable_msi(pdev) \ 840 linux_pci_enable_msi(pdev) 841 842 static inline int 843 pci_enable_msi(struct pci_dev *pdev) 844 { 845 struct resource_list_entry *rle; 846 int error; 847 int avail; 848 849 avail = pci_msi_count(pdev->dev.bsddev); 850 if (avail < 1) 851 return -EINVAL; 852 853 avail = 1; /* this function only enable one MSI IRQ */ 854 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 855 return error; 856 857 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 858 pdev->dev.irq_start = rle->start; 859 pdev->dev.irq_end = rle->start + avail; 860 pdev->irq = rle->start; 861 pdev->msi_enabled = true; 862 return (0); 863 } 864 865 static inline int 866 pci_channel_offline(struct pci_dev *pdev) 867 { 868 869 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 870 } 871 872 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 873 { 874 return -ENODEV; 875 } 876 877 static inline void pci_disable_sriov(struct pci_dev *dev) 878 { 879 } 880 881 static inline void * 882 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 883 { 884 struct resource *res; 885 886 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 887 if (res == NULL) 888 return (NULL); 889 /* This is a FreeBSD extension so we can use bus_*(). */ 890 if (pdev->want_iomap_res) 891 return (res); 892 return ((void *)rman_get_bushandle(res)); 893 } 894 895 static inline void 896 pci_iounmap(struct pci_dev *pdev, void *res) 897 { 898 struct pci_mmio_region *mmio, *p; 899 900 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 901 if (res != (void *)rman_get_bushandle(mmio->res)) 902 continue; 903 bus_release_resource(pdev->dev.bsddev, 904 mmio->type, mmio->rid, mmio->res); 905 TAILQ_REMOVE(&pdev->mmio, mmio, next); 906 free(mmio, M_DEVBUF); 907 return; 908 } 909 } 910 911 static inline void 912 lkpi_pci_save_state(struct pci_dev *pdev) 913 { 914 915 pci_save_state(pdev->dev.bsddev); 916 } 917 918 static inline void 919 lkpi_pci_restore_state(struct pci_dev *pdev) 920 { 921 922 pci_restore_state(pdev->dev.bsddev); 923 } 924 925 #define pci_save_state(dev) lkpi_pci_save_state(dev) 926 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 927 928 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 929 const struct pci_device_id _table[] __devinitdata 930 931 /* XXX This should not be necessary. */ 932 #define pcix_set_mmrbc(d, v) 0 933 #define pcix_get_max_mmrbc(d) 0 934 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 935 936 #define PCI_DMA_BIDIRECTIONAL 0 937 #define PCI_DMA_TODEVICE 1 938 #define PCI_DMA_FROMDEVICE 2 939 #define PCI_DMA_NONE 3 940 941 #define pci_pool dma_pool 942 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 943 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 944 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 945 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 946 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 947 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 948 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 949 _size, _vaddr, _dma_handle) 950 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 951 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 952 _sg, _nents, (enum dma_data_direction)_dir) 953 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 954 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 955 (_ptr), (_size), (enum dma_data_direction)_dir) 956 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 957 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 958 _addr, _size, (enum dma_data_direction)_dir) 959 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 960 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 961 _sg, _nents, (enum dma_data_direction)_dir) 962 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 963 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 964 _offset, _size, (enum dma_data_direction)_dir) 965 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 966 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 967 _dma_address, _size, (enum dma_data_direction)_dir) 968 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 969 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 970 dma_mapping_error(&(_pdev)->dev, _dma_addr) 971 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 972 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 973 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 974 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 975 #define pci_unmap_addr dma_unmap_addr 976 #define pci_unmap_addr_set dma_unmap_addr_set 977 #define pci_unmap_len dma_unmap_len 978 #define pci_unmap_len_set dma_unmap_len_set 979 980 typedef unsigned int __bitwise pci_channel_state_t; 981 typedef unsigned int __bitwise pci_ers_result_t; 982 983 enum pci_channel_state { 984 pci_channel_io_normal = 1, 985 pci_channel_io_frozen = 2, 986 pci_channel_io_perm_failure = 3, 987 }; 988 989 enum pci_ers_result { 990 PCI_ERS_RESULT_NONE = 1, 991 PCI_ERS_RESULT_CAN_RECOVER = 2, 992 PCI_ERS_RESULT_NEED_RESET = 3, 993 PCI_ERS_RESULT_DISCONNECT = 4, 994 PCI_ERS_RESULT_RECOVERED = 5, 995 }; 996 997 /* PCI bus error event callbacks */ 998 struct pci_error_handlers { 999 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1000 enum pci_channel_state error); 1001 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1002 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1003 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1004 void (*resume)(struct pci_dev *dev); 1005 }; 1006 1007 /* FreeBSD does not support SRIOV - yet */ 1008 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1009 { 1010 return dev; 1011 } 1012 1013 static inline bool pci_is_pcie(struct pci_dev *dev) 1014 { 1015 return !!pci_pcie_cap(dev); 1016 } 1017 1018 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1019 { 1020 int pos; 1021 u16 reg16; 1022 1023 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1024 if (!pos) 1025 return 0; 1026 1027 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1028 1029 return reg16; 1030 } 1031 1032 static inline int pci_pcie_type(struct pci_dev *dev) 1033 { 1034 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1035 } 1036 1037 static inline int pcie_cap_version(struct pci_dev *dev) 1038 { 1039 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1040 } 1041 1042 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1043 { 1044 int type = pci_pcie_type(dev); 1045 1046 return pcie_cap_version(dev) > 1 || 1047 type == PCI_EXP_TYPE_ROOT_PORT || 1048 type == PCI_EXP_TYPE_ENDPOINT || 1049 type == PCI_EXP_TYPE_LEG_END; 1050 } 1051 1052 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1053 { 1054 return true; 1055 } 1056 1057 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1058 { 1059 int type = pci_pcie_type(dev); 1060 1061 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1062 (type == PCI_EXP_TYPE_DOWNSTREAM && 1063 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1064 } 1065 1066 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1067 { 1068 int type = pci_pcie_type(dev); 1069 1070 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1071 type == PCI_EXP_TYPE_RC_EC; 1072 } 1073 1074 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1075 { 1076 if (!pci_is_pcie(dev)) 1077 return false; 1078 1079 switch (pos) { 1080 case PCI_EXP_FLAGS_TYPE: 1081 return true; 1082 case PCI_EXP_DEVCAP: 1083 case PCI_EXP_DEVCTL: 1084 case PCI_EXP_DEVSTA: 1085 return pcie_cap_has_devctl(dev); 1086 case PCI_EXP_LNKCAP: 1087 case PCI_EXP_LNKCTL: 1088 case PCI_EXP_LNKSTA: 1089 return pcie_cap_has_lnkctl(dev); 1090 case PCI_EXP_SLTCAP: 1091 case PCI_EXP_SLTCTL: 1092 case PCI_EXP_SLTSTA: 1093 return pcie_cap_has_sltctl(dev); 1094 case PCI_EXP_RTCTL: 1095 case PCI_EXP_RTCAP: 1096 case PCI_EXP_RTSTA: 1097 return pcie_cap_has_rtctl(dev); 1098 case PCI_EXP_DEVCAP2: 1099 case PCI_EXP_DEVCTL2: 1100 case PCI_EXP_LNKCAP2: 1101 case PCI_EXP_LNKCTL2: 1102 case PCI_EXP_LNKSTA2: 1103 return pcie_cap_version(dev) > 1; 1104 default: 1105 return false; 1106 } 1107 } 1108 1109 static inline int 1110 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1111 { 1112 if (pos & 3) 1113 return -EINVAL; 1114 1115 if (!pcie_capability_reg_implemented(dev, pos)) 1116 return -EINVAL; 1117 1118 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1119 } 1120 1121 static inline int 1122 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1123 { 1124 if (pos & 3) 1125 return -EINVAL; 1126 1127 if (!pcie_capability_reg_implemented(dev, pos)) 1128 return -EINVAL; 1129 1130 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1131 } 1132 1133 static inline int 1134 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1135 { 1136 if (pos & 1) 1137 return -EINVAL; 1138 1139 if (!pcie_capability_reg_implemented(dev, pos)) 1140 return 0; 1141 1142 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1143 } 1144 1145 static inline int 1146 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1147 { 1148 int error; 1149 uint16_t v; 1150 1151 error = pcie_capability_read_word(dev, pos, &v); 1152 if (error != 0) 1153 return (error); 1154 1155 v |= val; 1156 1157 error = pcie_capability_write_word(dev, pos, v); 1158 return (error); 1159 } 1160 1161 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1162 enum pci_bus_speed *speed, enum pcie_link_width *width) 1163 { 1164 *speed = PCI_SPEED_UNKNOWN; 1165 *width = PCIE_LNK_WIDTH_UNKNOWN; 1166 return (0); 1167 } 1168 1169 static inline int 1170 pci_num_vf(struct pci_dev *dev) 1171 { 1172 return (0); 1173 } 1174 1175 static inline enum pci_bus_speed 1176 pcie_get_speed_cap(struct pci_dev *dev) 1177 { 1178 device_t root; 1179 uint32_t lnkcap, lnkcap2; 1180 int error, pos; 1181 1182 root = device_get_parent(dev->dev.bsddev); 1183 if (root == NULL) 1184 return (PCI_SPEED_UNKNOWN); 1185 root = device_get_parent(root); 1186 if (root == NULL) 1187 return (PCI_SPEED_UNKNOWN); 1188 root = device_get_parent(root); 1189 if (root == NULL) 1190 return (PCI_SPEED_UNKNOWN); 1191 1192 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1193 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1194 return (PCI_SPEED_UNKNOWN); 1195 1196 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1197 return (PCI_SPEED_UNKNOWN); 1198 1199 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1200 1201 if (lnkcap2) { /* PCIe r3.0-compliant */ 1202 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1203 return (PCIE_SPEED_2_5GT); 1204 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1205 return (PCIE_SPEED_5_0GT); 1206 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1207 return (PCIE_SPEED_8_0GT); 1208 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1209 return (PCIE_SPEED_16_0GT); 1210 } else { /* pre-r3.0 */ 1211 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1212 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1213 return (PCIE_SPEED_2_5GT); 1214 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1215 return (PCIE_SPEED_5_0GT); 1216 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1217 return (PCIE_SPEED_8_0GT); 1218 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1219 return (PCIE_SPEED_16_0GT); 1220 } 1221 return (PCI_SPEED_UNKNOWN); 1222 } 1223 1224 static inline enum pcie_link_width 1225 pcie_get_width_cap(struct pci_dev *dev) 1226 { 1227 uint32_t lnkcap; 1228 1229 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1230 if (lnkcap) 1231 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1232 1233 return (PCIE_LNK_WIDTH_UNKNOWN); 1234 } 1235 1236 static inline int 1237 pcie_get_mps(struct pci_dev *dev) 1238 { 1239 return (pci_get_max_payload(dev->dev.bsddev)); 1240 } 1241 1242 static inline uint32_t 1243 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1244 { 1245 1246 switch(spd) { 1247 case PCIE_SPEED_16_0GT: 1248 return (16000 * 128 / 130); 1249 case PCIE_SPEED_8_0GT: 1250 return (8000 * 128 / 130); 1251 case PCIE_SPEED_5_0GT: 1252 return (5000 * 8 / 10); 1253 case PCIE_SPEED_2_5GT: 1254 return (2500 * 8 / 10); 1255 default: 1256 return (0); 1257 } 1258 } 1259 1260 static inline uint32_t 1261 pcie_bandwidth_available(struct pci_dev *pdev, 1262 struct pci_dev **limiting, 1263 enum pci_bus_speed *speed, 1264 enum pcie_link_width *width) 1265 { 1266 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1267 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1268 1269 if (speed) 1270 *speed = nspeed; 1271 if (width) 1272 *width = nwidth; 1273 1274 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1275 } 1276 1277 static inline struct pci_dev * 1278 pcie_find_root_port(struct pci_dev *pdev) 1279 { 1280 device_t root; 1281 1282 if (pdev->root != NULL) 1283 return (pdev->root); 1284 1285 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1286 if (root == NULL) 1287 return (NULL); 1288 1289 pdev->root = lkpinew_pci_dev(root); 1290 return (pdev->root); 1291 } 1292 1293 /* This is needed when people rip out the device "HotPlug". */ 1294 static inline void 1295 pci_lock_rescan_remove(void) 1296 { 1297 } 1298 1299 static inline void 1300 pci_unlock_rescan_remove(void) 1301 { 1302 } 1303 1304 static __inline void 1305 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1306 { 1307 } 1308 1309 /* 1310 * The following functions can be used to attach/detach the LinuxKPI's 1311 * PCI device runtime. The pci_driver and pci_device_id pointer is 1312 * allowed to be NULL. Other pointers must be all valid. 1313 * The pci_dev structure should be zero-initialized before passed 1314 * to the linux_pci_attach_device function. 1315 */ 1316 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1317 const struct pci_device_id *, struct pci_dev *); 1318 extern int linux_pci_detach_device(struct pci_dev *); 1319 1320 static inline int 1321 pci_dev_present(const struct pci_device_id *cur) 1322 { 1323 while (cur != NULL && (cur->vendor || cur->device)) { 1324 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1325 return (1); 1326 } 1327 cur++; 1328 } 1329 return (0); 1330 } 1331 1332 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1333 unsigned int bus, unsigned int devfn); 1334 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1335 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1336 1337 static inline int 1338 pci_domain_nr(struct pci_bus *pbus) 1339 { 1340 1341 return (pbus->domain); 1342 } 1343 1344 static inline int 1345 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1346 int pos, uint32_t *val, int len) 1347 { 1348 1349 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1350 return (0); 1351 } 1352 1353 static inline int 1354 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1355 { 1356 uint32_t tmp; 1357 int ret; 1358 1359 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1360 *val = (u16)tmp; 1361 return (ret); 1362 } 1363 1364 static inline int 1365 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1366 { 1367 uint32_t tmp; 1368 int ret; 1369 1370 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1371 *val = (u8)tmp; 1372 return (ret); 1373 } 1374 1375 static inline int 1376 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1377 uint32_t val, int size) 1378 { 1379 1380 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1381 return (0); 1382 } 1383 1384 static inline int 1385 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1386 uint8_t val) 1387 { 1388 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1389 } 1390 1391 static inline int 1392 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1393 uint16_t val) 1394 { 1395 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1396 } 1397 1398 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1399 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1400 1401 /* -------------------------------------------------------------------------- */ 1402 1403 static inline int 1404 pcim_enable_device(struct pci_dev *pdev) 1405 { 1406 struct pci_devres *dr; 1407 int error; 1408 1409 /* Here we cannot run through the pdev->managed check. */ 1410 dr = lkpi_pci_devres_get_alloc(pdev); 1411 if (dr == NULL) 1412 return (-ENOMEM); 1413 1414 /* If resources were enabled before do not do it again. */ 1415 if (dr->enable_io) 1416 return (0); 1417 1418 error = pci_enable_device(pdev); 1419 if (error == 0) 1420 dr->enable_io = true; 1421 1422 /* This device is not managed. */ 1423 pdev->managed = true; 1424 1425 return (error); 1426 } 1427 1428 static inline void __iomem ** 1429 pcim_iomap_table(struct pci_dev *pdev) 1430 { 1431 struct pcim_iomap_devres *dr; 1432 1433 dr = lkpi_pcim_iomap_devres_find(pdev); 1434 if (dr == NULL) 1435 return (NULL); 1436 1437 /* 1438 * If the driver has manually set a flag to be able to request the 1439 * resource to use bus_read/write_<n>, return the shadow table. 1440 */ 1441 if (pdev->want_iomap_res) 1442 return ((void **)dr->res_table); 1443 1444 /* This is the Linux default. */ 1445 return (dr->mmio_table); 1446 } 1447 1448 static inline int 1449 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1450 { 1451 struct pcim_iomap_devres *dr; 1452 void *res; 1453 uint32_t mappings, requests, req_mask; 1454 int bar, error; 1455 1456 dr = lkpi_pcim_iomap_devres_find(pdev); 1457 if (dr == NULL) 1458 return (-ENOMEM); 1459 1460 /* Request all the BARs ("regions") we do not iomap. */ 1461 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1462 for (bar = requests = 0; requests != req_mask; bar++) { 1463 if ((req_mask & (1 << bar)) == 0) 1464 continue; 1465 error = pci_request_region(pdev, bar, name); 1466 if (error != 0 && error != -ENODEV) 1467 goto err; 1468 requests |= (1 << bar); 1469 } 1470 1471 /* Now iomap all the requested (by "mask") ones. */ 1472 for (bar = mappings = 0; mappings != mask; bar++) { 1473 if ((mask & (1 << bar)) == 0) 1474 continue; 1475 1476 /* Request double is not allowed. */ 1477 if (dr->mmio_table[bar] != NULL) { 1478 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1479 __func__, bar, dr->mmio_table[bar]); 1480 goto err; 1481 } 1482 1483 res = _lkpi_pci_iomap(pdev, bar, 0); 1484 if (res == NULL) 1485 goto err; 1486 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1487 dr->res_table[bar] = res; 1488 1489 mappings |= (1 << bar); 1490 } 1491 1492 return (0); 1493 1494 err: 1495 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1496 if ((mappings & (1 << bar)) != 0) { 1497 res = dr->mmio_table[bar]; 1498 if (res == NULL) 1499 continue; 1500 pci_iounmap(pdev, res); 1501 } else if ((requests & (1 << bar)) != 0) { 1502 pci_release_region(pdev, bar); 1503 } 1504 } 1505 1506 return (-EINVAL); 1507 } 1508 1509 /* This is a FreeBSD extension so we can use bus_*(). */ 1510 static inline void 1511 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1512 { 1513 pdev->want_iomap_res = true; 1514 } 1515 1516 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1517