1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUX_PCI_H_ 36 #define _LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <sys/rman.h> 47 #include <sys/bus.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 #define MODULE_DEVICE_TABLE(bus, table) 74 75 #define PCI_ANY_ID -1U 76 77 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 78 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 79 #define PCI_FUNC(devfn) ((devfn) & 0x07) 80 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 81 82 #define PCI_VDEVICE(_vendor, _device) \ 83 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 84 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 85 #define PCI_DEVICE(_vendor, _device) \ 86 .vendor = (_vendor), .device = (_device), \ 87 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 88 89 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 90 91 #define PCI_VENDOR_ID PCIR_DEVVENDOR 92 #define PCI_COMMAND PCIR_COMMAND 93 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 94 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 95 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 96 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 97 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 98 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 99 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 100 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 101 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 102 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 103 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 104 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 105 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 106 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 107 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 108 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 109 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 110 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 111 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 112 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 113 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 114 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 115 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 116 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 117 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 118 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 119 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 120 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 121 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 122 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 123 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 124 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 125 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 126 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 127 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 128 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 129 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 130 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 131 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 132 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 133 #define PCI_EXP_LNKCTL2_TLS 0x000f 134 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 135 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 136 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 137 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 138 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 139 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 140 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 141 142 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 143 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 144 #define PCI_EXP_DEVSTA_TRPND 0x0020 145 146 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 147 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 148 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 149 150 enum pci_bus_speed { 151 PCI_SPEED_UNKNOWN = -1, 152 PCIE_SPEED_2_5GT, 153 PCIE_SPEED_5_0GT, 154 PCIE_SPEED_8_0GT, 155 PCIE_SPEED_16_0GT, 156 }; 157 158 enum pcie_link_width { 159 PCIE_LNK_WIDTH_RESRV = 0x00, 160 PCIE_LNK_X1 = 0x01, 161 PCIE_LNK_X2 = 0x02, 162 PCIE_LNK_X4 = 0x04, 163 PCIE_LNK_X8 = 0x08, 164 PCIE_LNK_X12 = 0x0c, 165 PCIE_LNK_X16 = 0x10, 166 PCIE_LNK_X32 = 0x20, 167 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 168 }; 169 170 #define PCIE_LINK_STATE_L0S 0x00000001 171 #define PCIE_LINK_STATE_L1 0x00000002 172 #define PCIE_LINK_STATE_CLKPM 0x00000004 173 174 typedef int pci_power_t; 175 176 #define PCI_D0 PCI_POWERSTATE_D0 177 #define PCI_D1 PCI_POWERSTATE_D1 178 #define PCI_D2 PCI_POWERSTATE_D2 179 #define PCI_D3hot PCI_POWERSTATE_D3 180 #define PCI_D3cold 4 181 182 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 183 184 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 185 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 186 187 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 188 189 struct pci_dev; 190 191 struct pci_driver { 192 struct list_head links; 193 char *name; 194 const struct pci_device_id *id_table; 195 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 196 void (*remove)(struct pci_dev *dev); 197 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 198 int (*resume) (struct pci_dev *dev); /* Device woken up */ 199 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 200 driver_t bsddriver; 201 devclass_t bsdclass; 202 struct device_driver driver; 203 const struct pci_error_handlers *err_handler; 204 bool isdrm; 205 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 206 const nvlist_t *pf_config); 207 void (*bsd_iov_uninit)(device_t dev); 208 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 209 const nvlist_t *vf_config); 210 }; 211 212 struct pci_bus { 213 struct pci_dev *self; 214 int domain; 215 int number; 216 }; 217 218 extern struct list_head pci_drivers; 219 extern struct list_head pci_devices; 220 extern spinlock_t pci_lock; 221 222 #define __devexit_p(x) x 223 224 /* 225 * If we find drivers accessing this from multiple KPIs we may have to 226 * refcount objects of this structure. 227 */ 228 struct pci_mmio_region { 229 TAILQ_ENTRY(pci_mmio_region) next; 230 struct resource *res; 231 int rid; 232 int type; 233 }; 234 235 struct pci_dev { 236 struct device dev; 237 struct list_head links; 238 struct pci_driver *pdrv; 239 struct pci_bus *bus; 240 struct pci_dev *root; 241 uint16_t device; 242 uint16_t vendor; 243 uint16_t subsystem_vendor; 244 uint16_t subsystem_device; 245 unsigned int irq; 246 unsigned int devfn; 247 uint32_t class; 248 uint8_t revision; 249 bool managed; /* devres "pcim_*(). */ 250 bool want_iomap_res; 251 bool msi_enabled; 252 bool msix_enabled; 253 phys_addr_t rom; 254 size_t romlen; 255 256 TAILQ_HEAD(, pci_mmio_region) mmio; 257 }; 258 259 /* We need some meta-struct to keep track of these for devres. */ 260 struct pci_devres { 261 bool enable_io; 262 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 263 uint8_t region_mask; 264 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 265 }; 266 struct pcim_iomap_devres { 267 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 268 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 269 }; 270 271 /* Internal helper function(s). */ 272 struct pci_dev *lkpinew_pci_dev(device_t); 273 void lkpi_pci_devres_release(struct device *, void *); 274 void lkpi_pcim_iomap_table_release(struct device *, void *); 275 276 static inline int 277 pci_resource_type(struct pci_dev *pdev, int bar) 278 { 279 struct pci_map *pm; 280 281 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 282 if (!pm) 283 return (-1); 284 285 if (PCI_BAR_IO(pm->pm_value)) 286 return (SYS_RES_IOPORT); 287 else 288 return (SYS_RES_MEMORY); 289 } 290 291 static inline struct resource_list_entry * 292 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 293 { 294 struct pci_devinfo *dinfo; 295 struct resource_list *rl; 296 297 dinfo = device_get_ivars(pdev->dev.bsddev); 298 rl = &dinfo->resources; 299 return resource_list_find(rl, type, rid); 300 } 301 302 static inline struct resource_list_entry * 303 linux_pci_get_bar(struct pci_dev *pdev, int bar) 304 { 305 int type; 306 307 type = pci_resource_type(pdev, bar); 308 if (type < 0) 309 return (NULL); 310 bar = PCIR_BAR(bar); 311 return (linux_pci_get_rle(pdev, type, bar)); 312 } 313 314 static inline struct device * 315 linux_pci_find_irq_dev(unsigned int irq) 316 { 317 struct pci_dev *pdev; 318 struct device *found; 319 320 found = NULL; 321 spin_lock(&pci_lock); 322 list_for_each_entry(pdev, &pci_devices, links) { 323 if (irq == pdev->dev.irq || 324 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 325 found = &pdev->dev; 326 break; 327 } 328 } 329 spin_unlock(&pci_lock); 330 return (found); 331 } 332 333 /* 334 * All drivers just seem to want to inspect the type not flags. 335 */ 336 static inline int 337 pci_resource_flags(struct pci_dev *pdev, int bar) 338 { 339 int type; 340 341 type = pci_resource_type(pdev, bar); 342 if (type < 0) 343 return (0); 344 return (1 << type); 345 } 346 347 static inline const char * 348 pci_name(struct pci_dev *d) 349 { 350 351 return device_get_desc(d->dev.bsddev); 352 } 353 354 static inline void * 355 pci_get_drvdata(struct pci_dev *pdev) 356 { 357 358 return dev_get_drvdata(&pdev->dev); 359 } 360 361 static inline void 362 pci_set_drvdata(struct pci_dev *pdev, void *data) 363 { 364 365 dev_set_drvdata(&pdev->dev, data); 366 } 367 368 static inline struct pci_dev * 369 pci_dev_get(struct pci_dev *pdev) 370 { 371 372 if (pdev != NULL) 373 get_device(&pdev->dev); 374 return (pdev); 375 } 376 377 static __inline void 378 pci_dev_put(struct pci_dev *pdev) 379 { 380 381 if (pdev != NULL) 382 put_device(&pdev->dev); 383 } 384 385 static inline int 386 pci_enable_device(struct pci_dev *pdev) 387 { 388 389 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 390 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 391 return (0); 392 } 393 394 static inline void 395 pci_disable_device(struct pci_dev *pdev) 396 { 397 398 pci_disable_busmaster(pdev->dev.bsddev); 399 } 400 401 static inline int 402 pci_set_master(struct pci_dev *pdev) 403 { 404 405 pci_enable_busmaster(pdev->dev.bsddev); 406 return (0); 407 } 408 409 static inline int 410 pci_set_power_state(struct pci_dev *pdev, int state) 411 { 412 413 pci_set_powerstate(pdev->dev.bsddev, state); 414 return (0); 415 } 416 417 static inline int 418 pci_clear_master(struct pci_dev *pdev) 419 { 420 421 pci_disable_busmaster(pdev->dev.bsddev); 422 return (0); 423 } 424 425 static inline struct pci_devres * 426 lkpi_pci_devres_get_alloc(struct pci_dev *pdev) 427 { 428 struct pci_devres *dr; 429 430 dr = lkpi_devres_find(&pdev->dev, lkpi_pci_devres_release, NULL, NULL); 431 if (dr == NULL) { 432 dr = lkpi_devres_alloc(lkpi_pci_devres_release, sizeof(*dr), 433 GFP_KERNEL | __GFP_ZERO); 434 if (dr != NULL) 435 lkpi_devres_add(&pdev->dev, dr); 436 } 437 438 return (dr); 439 } 440 static inline struct pci_devres * 441 lkpi_pci_devres_find(struct pci_dev *pdev) 442 { 443 444 if (!pdev->managed) 445 return (NULL); 446 447 return (lkpi_pci_devres_get_alloc(pdev)); 448 } 449 450 static inline int 451 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 452 { 453 struct resource *res; 454 struct pci_devres *dr; 455 struct pci_mmio_region *mmio; 456 int rid; 457 int type; 458 459 type = pci_resource_type(pdev, bar); 460 if (type < 0) 461 return (-ENODEV); 462 rid = PCIR_BAR(bar); 463 res = bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 464 RF_ACTIVE|RF_SHAREABLE); 465 if (res == NULL) { 466 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 467 "bar %d type %d rid %d\n", 468 __func__, bar, type, PCIR_BAR(bar)); 469 return (-ENODEV); 470 } 471 472 /* 473 * It seems there is an implicit devres tracking on these if the device 474 * is managed; otherwise the resources are not automatiaclly freed on 475 * FreeBSD/LinuxKPI tough they should be/are expected to be by Linux 476 * drivers. 477 */ 478 dr = lkpi_pci_devres_find(pdev); 479 if (dr != NULL) { 480 dr->region_mask |= (1 << bar); 481 dr->region_table[bar] = res; 482 } 483 484 /* Even if the device is not managed we need to track it for iomap. */ 485 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 486 mmio->rid = PCIR_BAR(bar); 487 mmio->type = type; 488 mmio->res = res; 489 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 490 491 return (0); 492 } 493 494 static inline void 495 pci_release_region(struct pci_dev *pdev, int bar) 496 { 497 struct resource_list_entry *rle; 498 struct pci_devres *dr; 499 struct pci_mmio_region *mmio, *p; 500 501 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 502 return; 503 504 /* 505 * As we implicitly track the requests we also need to clear them on 506 * release. Do clear before resource release. 507 */ 508 dr = lkpi_pci_devres_find(pdev); 509 if (dr != NULL) { 510 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 511 " region_table res %p != rel->res %p\n", __func__, pdev, 512 bar, dr->region_table[bar], rle->res)); 513 dr->region_table[bar] = NULL; 514 dr->region_mask &= ~(1 << bar); 515 } 516 517 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 518 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 519 continue; 520 TAILQ_REMOVE(&pdev->mmio, mmio, next); 521 free(mmio, M_DEVBUF); 522 } 523 524 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 525 } 526 527 static inline void 528 pci_release_regions(struct pci_dev *pdev) 529 { 530 int i; 531 532 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 533 pci_release_region(pdev, i); 534 } 535 536 static inline int 537 pci_request_regions(struct pci_dev *pdev, const char *res_name) 538 { 539 int error; 540 int i; 541 542 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 543 error = pci_request_region(pdev, i, res_name); 544 if (error && error != -ENODEV) { 545 pci_release_regions(pdev); 546 return (error); 547 } 548 } 549 return (0); 550 } 551 552 static inline void 553 lkpi_pci_disable_msix(struct pci_dev *pdev) 554 { 555 556 pci_release_msi(pdev->dev.bsddev); 557 558 /* 559 * The MSIX IRQ numbers associated with this PCI device are no 560 * longer valid and might be re-assigned. Make sure 561 * linux_pci_find_irq_dev() does no longer see them by 562 * resetting their references to zero: 563 */ 564 pdev->dev.irq_start = 0; 565 pdev->dev.irq_end = 0; 566 pdev->msix_enabled = false; 567 } 568 /* Only for consistency. No conflict on that one. */ 569 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 570 571 static inline void 572 lkpi_pci_disable_msi(struct pci_dev *pdev) 573 { 574 575 pci_release_msi(pdev->dev.bsddev); 576 577 pdev->dev.irq_start = 0; 578 pdev->dev.irq_end = 0; 579 pdev->irq = pdev->dev.irq; 580 pdev->msi_enabled = false; 581 } 582 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 583 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 584 585 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 586 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 587 588 static inline bus_addr_t 589 pci_bus_address(struct pci_dev *pdev, int bar) 590 { 591 592 return (pci_resource_start(pdev, bar)); 593 } 594 595 #define PCI_CAP_ID_EXP PCIY_EXPRESS 596 #define PCI_CAP_ID_PCIX PCIY_PCIX 597 #define PCI_CAP_ID_AGP PCIY_AGP 598 #define PCI_CAP_ID_PM PCIY_PMG 599 600 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 601 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 602 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 603 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 604 #define PCI_EXP_LNKSTA PCIER_LINK_STA 605 606 static inline int 607 pci_find_capability(struct pci_dev *pdev, int capid) 608 { 609 int reg; 610 611 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 612 return (0); 613 return (reg); 614 } 615 616 static inline int pci_pcie_cap(struct pci_dev *dev) 617 { 618 return pci_find_capability(dev, PCI_CAP_ID_EXP); 619 } 620 621 static inline int 622 pci_find_ext_capability(struct pci_dev *pdev, int capid) 623 { 624 int reg; 625 626 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 627 return (0); 628 return (reg); 629 } 630 631 #define PCIM_PCAP_PME_SHIFT 11 632 static __inline bool 633 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 634 { 635 struct pci_devinfo *dinfo; 636 pcicfgregs *cfg; 637 638 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 639 return (false); 640 641 dinfo = device_get_ivars(pdev->dev.bsddev); 642 cfg = &dinfo->cfg; 643 644 if (cfg->pp.pp_cap == 0) 645 return (false); 646 647 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 648 return (true); 649 650 return (false); 651 } 652 653 static inline int 654 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 655 { 656 657 if (!pci_enable_aspm) 658 return (-EPERM); 659 660 return (-ENXIO); 661 } 662 663 static inline int 664 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 665 { 666 667 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 668 return (0); 669 } 670 671 static inline int 672 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 673 { 674 675 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 676 return (0); 677 } 678 679 static inline int 680 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 681 { 682 683 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 684 return (0); 685 } 686 687 static inline int 688 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 689 { 690 691 pci_write_config(pdev->dev.bsddev, where, val, 1); 692 return (0); 693 } 694 695 static inline int 696 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 697 { 698 699 pci_write_config(pdev->dev.bsddev, where, val, 2); 700 return (0); 701 } 702 703 static inline int 704 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 705 { 706 707 pci_write_config(pdev->dev.bsddev, where, val, 4); 708 return (0); 709 } 710 711 int linux_pci_register_driver(struct pci_driver *pdrv); 712 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 713 void linux_pci_unregister_driver(struct pci_driver *pdrv); 714 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 715 716 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 717 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 718 719 struct msix_entry { 720 int entry; 721 int vector; 722 }; 723 724 /* 725 * Enable msix, positive errors indicate actual number of available 726 * vectors. Negative errors are failures. 727 * 728 * NB: define added to prevent this definition of pci_enable_msix from 729 * clashing with the native FreeBSD version. 730 */ 731 #define pci_enable_msix(...) \ 732 linux_pci_enable_msix(__VA_ARGS__) 733 734 static inline int 735 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 736 { 737 struct resource_list_entry *rle; 738 int error; 739 int avail; 740 int i; 741 742 avail = pci_msix_count(pdev->dev.bsddev); 743 if (avail < nreq) { 744 if (avail == 0) 745 return -EINVAL; 746 return avail; 747 } 748 avail = nreq; 749 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 750 return error; 751 /* 752 * Handle case where "pci_alloc_msix()" may allocate less 753 * interrupts than available and return with no error: 754 */ 755 if (avail < nreq) { 756 pci_release_msi(pdev->dev.bsddev); 757 return avail; 758 } 759 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 760 pdev->dev.irq_start = rle->start; 761 pdev->dev.irq_end = rle->start + avail; 762 for (i = 0; i < nreq; i++) 763 entries[i].vector = pdev->dev.irq_start + i; 764 pdev->msix_enabled = true; 765 return (0); 766 } 767 768 #define pci_enable_msix_range(...) \ 769 linux_pci_enable_msix_range(__VA_ARGS__) 770 771 static inline int 772 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 773 int minvec, int maxvec) 774 { 775 int nvec = maxvec; 776 int rc; 777 778 if (maxvec < minvec) 779 return (-ERANGE); 780 781 do { 782 rc = pci_enable_msix(dev, entries, nvec); 783 if (rc < 0) { 784 return (rc); 785 } else if (rc > 0) { 786 if (rc < minvec) 787 return (-ENOSPC); 788 nvec = rc; 789 } 790 } while (rc); 791 return (nvec); 792 } 793 794 #define pci_enable_msi(pdev) \ 795 linux_pci_enable_msi(pdev) 796 797 static inline int 798 pci_enable_msi(struct pci_dev *pdev) 799 { 800 struct resource_list_entry *rle; 801 int error; 802 int avail; 803 804 avail = pci_msi_count(pdev->dev.bsddev); 805 if (avail < 1) 806 return -EINVAL; 807 808 avail = 1; /* this function only enable one MSI IRQ */ 809 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 810 return error; 811 812 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 813 pdev->dev.irq_start = rle->start; 814 pdev->dev.irq_end = rle->start + avail; 815 pdev->irq = rle->start; 816 pdev->msi_enabled = true; 817 return (0); 818 } 819 820 static inline int 821 pci_channel_offline(struct pci_dev *pdev) 822 { 823 824 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 825 } 826 827 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 828 { 829 return -ENODEV; 830 } 831 static inline void pci_disable_sriov(struct pci_dev *dev) 832 { 833 } 834 835 static inline struct resource * 836 _lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size __unused) 837 { 838 struct pci_mmio_region *mmio, *p; 839 int type; 840 841 type = pci_resource_type(pdev, bar); 842 if (type < 0) { 843 device_printf(pdev->dev.bsddev, "%s: bar %d type %d\n", 844 __func__, bar, type); 845 return (NULL); 846 } 847 848 /* 849 * Check for duplicate mappings. 850 * This can happen if a driver calls pci_request_region() first. 851 */ 852 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 853 if (mmio->type == type && mmio->rid == PCIR_BAR(bar)) { 854 return (mmio->res); 855 } 856 } 857 858 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 859 mmio->rid = PCIR_BAR(bar); 860 mmio->type = type; 861 mmio->res = bus_alloc_resource_any(pdev->dev.bsddev, mmio->type, 862 &mmio->rid, RF_ACTIVE|RF_SHAREABLE); 863 if (mmio->res == NULL) { 864 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 865 "bar %d type %d rid %d\n", 866 __func__, bar, type, PCIR_BAR(bar)); 867 free(mmio, M_DEVBUF); 868 return (NULL); 869 } 870 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 871 872 return (mmio->res); 873 } 874 875 static inline void * 876 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 877 { 878 struct resource *res; 879 880 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 881 if (res == NULL) 882 return (NULL); 883 /* This is a FreeBSD extension so we can use bus_*(). */ 884 if (pdev->want_iomap_res) 885 return (res); 886 return ((void *)rman_get_bushandle(res)); 887 } 888 889 static inline void 890 pci_iounmap(struct pci_dev *pdev, void *res) 891 { 892 struct pci_mmio_region *mmio, *p; 893 894 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 895 if (res != (void *)rman_get_bushandle(mmio->res)) 896 continue; 897 bus_release_resource(pdev->dev.bsddev, 898 mmio->type, mmio->rid, mmio->res); 899 TAILQ_REMOVE(&pdev->mmio, mmio, next); 900 free(mmio, M_DEVBUF); 901 return; 902 } 903 } 904 905 static inline void 906 lkpi_pci_save_state(struct pci_dev *pdev) 907 { 908 909 pci_save_state(pdev->dev.bsddev); 910 } 911 912 static inline void 913 lkpi_pci_restore_state(struct pci_dev *pdev) 914 { 915 916 pci_restore_state(pdev->dev.bsddev); 917 } 918 919 #define pci_save_state(dev) lkpi_pci_save_state(dev) 920 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 921 922 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 923 const struct pci_device_id _table[] __devinitdata 924 925 /* XXX This should not be necessary. */ 926 #define pcix_set_mmrbc(d, v) 0 927 #define pcix_get_max_mmrbc(d) 0 928 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 929 930 #define PCI_DMA_BIDIRECTIONAL 0 931 #define PCI_DMA_TODEVICE 1 932 #define PCI_DMA_FROMDEVICE 2 933 #define PCI_DMA_NONE 3 934 935 #define pci_pool dma_pool 936 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 937 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 938 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 939 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 940 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 941 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 942 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 943 _size, _vaddr, _dma_handle) 944 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 945 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 946 _sg, _nents, (enum dma_data_direction)_dir) 947 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 948 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 949 (_ptr), (_size), (enum dma_data_direction)_dir) 950 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 951 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 952 _addr, _size, (enum dma_data_direction)_dir) 953 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 954 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 955 _sg, _nents, (enum dma_data_direction)_dir) 956 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 957 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 958 _offset, _size, (enum dma_data_direction)_dir) 959 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 960 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 961 _dma_address, _size, (enum dma_data_direction)_dir) 962 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 963 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 964 dma_mapping_error(&(_pdev)->dev, _dma_addr) 965 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 966 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 967 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 968 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 969 #define pci_unmap_addr dma_unmap_addr 970 #define pci_unmap_addr_set dma_unmap_addr_set 971 #define pci_unmap_len dma_unmap_len 972 #define pci_unmap_len_set dma_unmap_len_set 973 974 typedef unsigned int __bitwise pci_channel_state_t; 975 typedef unsigned int __bitwise pci_ers_result_t; 976 977 enum pci_channel_state { 978 pci_channel_io_normal = 1, 979 pci_channel_io_frozen = 2, 980 pci_channel_io_perm_failure = 3, 981 }; 982 983 enum pci_ers_result { 984 PCI_ERS_RESULT_NONE = 1, 985 PCI_ERS_RESULT_CAN_RECOVER = 2, 986 PCI_ERS_RESULT_NEED_RESET = 3, 987 PCI_ERS_RESULT_DISCONNECT = 4, 988 PCI_ERS_RESULT_RECOVERED = 5, 989 }; 990 991 /* PCI bus error event callbacks */ 992 struct pci_error_handlers { 993 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 994 enum pci_channel_state error); 995 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 996 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 997 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 998 void (*resume)(struct pci_dev *dev); 999 }; 1000 1001 /* FreeBSD does not support SRIOV - yet */ 1002 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1003 { 1004 return dev; 1005 } 1006 1007 static inline bool pci_is_pcie(struct pci_dev *dev) 1008 { 1009 return !!pci_pcie_cap(dev); 1010 } 1011 1012 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1013 { 1014 int pos; 1015 u16 reg16; 1016 1017 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1018 if (!pos) 1019 return 0; 1020 1021 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1022 1023 return reg16; 1024 } 1025 1026 static inline int pci_pcie_type(struct pci_dev *dev) 1027 { 1028 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1029 } 1030 1031 static inline int pcie_cap_version(struct pci_dev *dev) 1032 { 1033 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1034 } 1035 1036 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1037 { 1038 int type = pci_pcie_type(dev); 1039 1040 return pcie_cap_version(dev) > 1 || 1041 type == PCI_EXP_TYPE_ROOT_PORT || 1042 type == PCI_EXP_TYPE_ENDPOINT || 1043 type == PCI_EXP_TYPE_LEG_END; 1044 } 1045 1046 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1047 { 1048 return true; 1049 } 1050 1051 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1052 { 1053 int type = pci_pcie_type(dev); 1054 1055 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1056 (type == PCI_EXP_TYPE_DOWNSTREAM && 1057 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1058 } 1059 1060 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1061 { 1062 int type = pci_pcie_type(dev); 1063 1064 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1065 type == PCI_EXP_TYPE_RC_EC; 1066 } 1067 1068 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1069 { 1070 if (!pci_is_pcie(dev)) 1071 return false; 1072 1073 switch (pos) { 1074 case PCI_EXP_FLAGS_TYPE: 1075 return true; 1076 case PCI_EXP_DEVCAP: 1077 case PCI_EXP_DEVCTL: 1078 case PCI_EXP_DEVSTA: 1079 return pcie_cap_has_devctl(dev); 1080 case PCI_EXP_LNKCAP: 1081 case PCI_EXP_LNKCTL: 1082 case PCI_EXP_LNKSTA: 1083 return pcie_cap_has_lnkctl(dev); 1084 case PCI_EXP_SLTCAP: 1085 case PCI_EXP_SLTCTL: 1086 case PCI_EXP_SLTSTA: 1087 return pcie_cap_has_sltctl(dev); 1088 case PCI_EXP_RTCTL: 1089 case PCI_EXP_RTCAP: 1090 case PCI_EXP_RTSTA: 1091 return pcie_cap_has_rtctl(dev); 1092 case PCI_EXP_DEVCAP2: 1093 case PCI_EXP_DEVCTL2: 1094 case PCI_EXP_LNKCAP2: 1095 case PCI_EXP_LNKCTL2: 1096 case PCI_EXP_LNKSTA2: 1097 return pcie_cap_version(dev) > 1; 1098 default: 1099 return false; 1100 } 1101 } 1102 1103 static inline int 1104 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1105 { 1106 if (pos & 3) 1107 return -EINVAL; 1108 1109 if (!pcie_capability_reg_implemented(dev, pos)) 1110 return -EINVAL; 1111 1112 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1113 } 1114 1115 static inline int 1116 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1117 { 1118 if (pos & 3) 1119 return -EINVAL; 1120 1121 if (!pcie_capability_reg_implemented(dev, pos)) 1122 return -EINVAL; 1123 1124 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1125 } 1126 1127 static inline int 1128 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1129 { 1130 if (pos & 1) 1131 return -EINVAL; 1132 1133 if (!pcie_capability_reg_implemented(dev, pos)) 1134 return 0; 1135 1136 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1137 } 1138 1139 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1140 enum pci_bus_speed *speed, enum pcie_link_width *width) 1141 { 1142 *speed = PCI_SPEED_UNKNOWN; 1143 *width = PCIE_LNK_WIDTH_UNKNOWN; 1144 return (0); 1145 } 1146 1147 static inline int 1148 pci_num_vf(struct pci_dev *dev) 1149 { 1150 return (0); 1151 } 1152 1153 static inline enum pci_bus_speed 1154 pcie_get_speed_cap(struct pci_dev *dev) 1155 { 1156 device_t root; 1157 uint32_t lnkcap, lnkcap2; 1158 int error, pos; 1159 1160 root = device_get_parent(dev->dev.bsddev); 1161 if (root == NULL) 1162 return (PCI_SPEED_UNKNOWN); 1163 root = device_get_parent(root); 1164 if (root == NULL) 1165 return (PCI_SPEED_UNKNOWN); 1166 root = device_get_parent(root); 1167 if (root == NULL) 1168 return (PCI_SPEED_UNKNOWN); 1169 1170 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1171 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1172 return (PCI_SPEED_UNKNOWN); 1173 1174 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1175 return (PCI_SPEED_UNKNOWN); 1176 1177 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1178 1179 if (lnkcap2) { /* PCIe r3.0-compliant */ 1180 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1181 return (PCIE_SPEED_2_5GT); 1182 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1183 return (PCIE_SPEED_5_0GT); 1184 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1185 return (PCIE_SPEED_8_0GT); 1186 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1187 return (PCIE_SPEED_16_0GT); 1188 } else { /* pre-r3.0 */ 1189 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1190 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1191 return (PCIE_SPEED_2_5GT); 1192 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1193 return (PCIE_SPEED_5_0GT); 1194 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1195 return (PCIE_SPEED_8_0GT); 1196 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1197 return (PCIE_SPEED_16_0GT); 1198 } 1199 return (PCI_SPEED_UNKNOWN); 1200 } 1201 1202 static inline enum pcie_link_width 1203 pcie_get_width_cap(struct pci_dev *dev) 1204 { 1205 uint32_t lnkcap; 1206 1207 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1208 if (lnkcap) 1209 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1210 1211 return (PCIE_LNK_WIDTH_UNKNOWN); 1212 } 1213 1214 static inline int 1215 pcie_get_mps(struct pci_dev *dev) 1216 { 1217 return (pci_get_max_payload(dev->dev.bsddev)); 1218 } 1219 1220 static inline uint32_t 1221 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1222 { 1223 1224 switch(spd) { 1225 case PCIE_SPEED_16_0GT: 1226 return (16000 * 128 / 130); 1227 case PCIE_SPEED_8_0GT: 1228 return (8000 * 128 / 130); 1229 case PCIE_SPEED_5_0GT: 1230 return (5000 * 8 / 10); 1231 case PCIE_SPEED_2_5GT: 1232 return (2500 * 8 / 10); 1233 default: 1234 return (0); 1235 } 1236 } 1237 1238 static inline uint32_t 1239 pcie_bandwidth_available(struct pci_dev *pdev, 1240 struct pci_dev **limiting, 1241 enum pci_bus_speed *speed, 1242 enum pcie_link_width *width) 1243 { 1244 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1245 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1246 1247 if (speed) 1248 *speed = nspeed; 1249 if (width) 1250 *width = nwidth; 1251 1252 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1253 } 1254 1255 static inline struct pci_dev * 1256 pcie_find_root_port(struct pci_dev *pdev) 1257 { 1258 device_t root; 1259 1260 if (pdev->root != NULL) 1261 return (pdev->root); 1262 1263 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1264 if (root == NULL) 1265 return (NULL); 1266 1267 pdev->root = lkpinew_pci_dev(root); 1268 return (pdev->root); 1269 } 1270 1271 /* This is needed when people rip out the device "HotPlug". */ 1272 static inline void 1273 pci_lock_rescan_remove(void) 1274 { 1275 } 1276 1277 static inline void 1278 pci_unlock_rescan_remove(void) 1279 { 1280 } 1281 1282 static __inline void 1283 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1284 { 1285 } 1286 1287 /* 1288 * The following functions can be used to attach/detach the LinuxKPI's 1289 * PCI device runtime. The pci_driver and pci_device_id pointer is 1290 * allowed to be NULL. Other pointers must be all valid. 1291 * The pci_dev structure should be zero-initialized before passed 1292 * to the linux_pci_attach_device function. 1293 */ 1294 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1295 const struct pci_device_id *, struct pci_dev *); 1296 extern int linux_pci_detach_device(struct pci_dev *); 1297 1298 static inline int 1299 pci_dev_present(const struct pci_device_id *cur) 1300 { 1301 while (cur != NULL && (cur->vendor || cur->device)) { 1302 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1303 return (1); 1304 } 1305 cur++; 1306 } 1307 return (0); 1308 } 1309 1310 static inline bool 1311 pci_is_root_bus(struct pci_bus *pbus) 1312 { 1313 1314 return (pbus->self == NULL); 1315 } 1316 1317 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1318 unsigned int bus, unsigned int devfn); 1319 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1320 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1321 1322 static inline int 1323 pci_domain_nr(struct pci_bus *pbus) 1324 { 1325 1326 return (pbus->domain); 1327 } 1328 1329 static inline int 1330 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1331 int pos, uint32_t *val, int len) 1332 { 1333 1334 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1335 return (0); 1336 } 1337 1338 static inline int 1339 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1340 { 1341 uint32_t tmp; 1342 int ret; 1343 1344 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1345 *val = (u16)tmp; 1346 return (ret); 1347 } 1348 1349 static inline int 1350 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1351 { 1352 uint32_t tmp; 1353 int ret; 1354 1355 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1356 *val = (u8)tmp; 1357 return (ret); 1358 } 1359 1360 static inline int 1361 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1362 uint32_t val, int size) 1363 { 1364 1365 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1366 return (0); 1367 } 1368 1369 static inline int 1370 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1371 uint8_t val) 1372 { 1373 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1374 } 1375 1376 static inline int 1377 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1378 uint16_t val) 1379 { 1380 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1381 } 1382 1383 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1384 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1385 1386 /* -------------------------------------------------------------------------- */ 1387 1388 static inline int 1389 pcim_enable_device(struct pci_dev *pdev) 1390 { 1391 struct pci_devres *dr; 1392 int error; 1393 1394 /* Here we cannot run through the pdev->managed check. */ 1395 dr = lkpi_pci_devres_get_alloc(pdev); 1396 if (dr == NULL) 1397 return (-ENOMEM); 1398 1399 /* If resources were enabled before do not do it again. */ 1400 if (dr->enable_io) 1401 return (0); 1402 1403 error = pci_enable_device(pdev); 1404 if (error == 0) 1405 dr->enable_io = true; 1406 1407 /* This device is not managed. */ 1408 pdev->managed = true; 1409 1410 return (error); 1411 } 1412 1413 static inline struct pcim_iomap_devres * 1414 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev) 1415 { 1416 struct pcim_iomap_devres *dr; 1417 1418 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release, 1419 NULL, NULL); 1420 if (dr == NULL) { 1421 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release, 1422 sizeof(*dr), GFP_KERNEL | __GFP_ZERO); 1423 if (dr != NULL) 1424 lkpi_devres_add(&pdev->dev, dr); 1425 } 1426 1427 if (dr == NULL) 1428 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__); 1429 1430 return (dr); 1431 } 1432 1433 static inline void __iomem ** 1434 pcim_iomap_table(struct pci_dev *pdev) 1435 { 1436 struct pcim_iomap_devres *dr; 1437 1438 dr = lkpi_pcim_iomap_devres_find(pdev); 1439 if (dr == NULL) 1440 return (NULL); 1441 1442 /* 1443 * If the driver has manually set a flag to be able to request the 1444 * resource to use bus_read/write_<n>, return the shadow table. 1445 */ 1446 if (pdev->want_iomap_res) 1447 return ((void **)dr->res_table); 1448 1449 /* This is the Linux default. */ 1450 return (dr->mmio_table); 1451 } 1452 1453 static inline int 1454 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1455 { 1456 struct pcim_iomap_devres *dr; 1457 void *res; 1458 uint32_t mappings, requests, req_mask; 1459 int bar, error; 1460 1461 dr = lkpi_pcim_iomap_devres_find(pdev); 1462 if (dr == NULL) 1463 return (-ENOMEM); 1464 1465 /* Request all the BARs ("regions") we do not iomap. */ 1466 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1467 for (bar = requests = 0; requests != req_mask; bar++) { 1468 if ((req_mask & (1 << bar)) == 0) 1469 continue; 1470 error = pci_request_region(pdev, bar, name); 1471 if (error != 0 && error != -ENODEV) 1472 goto err; 1473 requests |= (1 << bar); 1474 } 1475 1476 /* Now iomap all the requested (by "mask") ones. */ 1477 for (bar = mappings = 0; mappings != mask; bar++) { 1478 if ((mask & (1 << bar)) == 0) 1479 continue; 1480 1481 /* Request double is not allowed. */ 1482 if (dr->mmio_table[bar] != NULL) { 1483 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1484 __func__, bar, dr->mmio_table[bar]); 1485 goto err; 1486 } 1487 1488 res = _lkpi_pci_iomap(pdev, bar, 0); 1489 if (res == NULL) 1490 goto err; 1491 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1492 dr->res_table[bar] = res; 1493 1494 mappings |= (1 << bar); 1495 } 1496 1497 return (0); 1498 1499 err: 1500 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1501 if ((mappings & (1 << bar)) != 0) { 1502 res = dr->mmio_table[bar]; 1503 if (res == NULL) 1504 continue; 1505 pci_iounmap(pdev, res); 1506 } else if ((requests & (1 << bar)) != 0) { 1507 pci_release_region(pdev, bar); 1508 } 1509 } 1510 1511 return (-EINVAL); 1512 } 1513 1514 /* This is a FreeBSD extension so we can use bus_*(). */ 1515 static inline void 1516 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1517 { 1518 pdev->want_iomap_res = true; 1519 } 1520 1521 #endif /* _LINUX_PCI_H_ */ 1522