1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/nv.h> 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 74 #define MODULE_DEVICE_TABLE(_bus, _table) \ 75 \ 76 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 77 DEVMETHOD_END \ 78 }; \ 79 \ 80 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 81 "lkpi_" #_bus #_table, \ 82 _ ## _bus ## _ ## _table ## _methods, \ 83 0 \ 84 }; \ 85 \ 86 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 87 0, 0); \ 88 \ 89 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 90 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 91 92 #define PCI_ANY_ID -1U 93 94 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 95 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 96 #define PCI_FUNC(devfn) ((devfn) & 0x07) 97 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 98 99 #define PCI_VDEVICE(_vendor, _device) \ 100 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 101 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 102 #define PCI_DEVICE(_vendor, _device) \ 103 .vendor = (_vendor), .device = (_device), \ 104 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 105 106 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 107 108 #define PCI_VENDOR_ID PCIR_DEVVENDOR 109 #define PCI_COMMAND PCIR_COMMAND 110 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 111 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 112 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 113 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 114 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 115 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 116 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 117 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 118 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 119 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 120 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 121 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 122 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 123 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 124 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 125 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 126 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 127 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 128 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 129 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 130 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 131 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 132 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 133 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 134 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 135 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 136 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 137 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 138 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 139 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 140 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 141 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 142 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 143 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 144 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 145 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 146 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 147 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 148 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 149 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 150 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 151 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 152 #define PCI_EXP_LNKCTL2_TLS 0x000f 153 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 154 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 155 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 156 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 157 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 158 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 159 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 160 161 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 162 #define PCI_EXP_DEVSTA_TRPND 0x0020 163 164 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 165 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 166 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 167 168 enum pci_bus_speed { 169 PCI_SPEED_UNKNOWN = -1, 170 PCIE_SPEED_2_5GT, 171 PCIE_SPEED_5_0GT, 172 PCIE_SPEED_8_0GT, 173 PCIE_SPEED_16_0GT, 174 }; 175 176 enum pcie_link_width { 177 PCIE_LNK_WIDTH_RESRV = 0x00, 178 PCIE_LNK_X1 = 0x01, 179 PCIE_LNK_X2 = 0x02, 180 PCIE_LNK_X4 = 0x04, 181 PCIE_LNK_X8 = 0x08, 182 PCIE_LNK_X12 = 0x0c, 183 PCIE_LNK_X16 = 0x10, 184 PCIE_LNK_X32 = 0x20, 185 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 186 }; 187 188 #define PCIE_LINK_STATE_L0S 0x00000001 189 #define PCIE_LINK_STATE_L1 0x00000002 190 #define PCIE_LINK_STATE_CLKPM 0x00000004 191 192 typedef int pci_power_t; 193 194 #define PCI_D0 PCI_POWERSTATE_D0 195 #define PCI_D1 PCI_POWERSTATE_D1 196 #define PCI_D2 PCI_POWERSTATE_D2 197 #define PCI_D3hot PCI_POWERSTATE_D3 198 #define PCI_D3cold 4 199 200 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 201 202 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 203 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 204 205 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 206 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 207 208 #define PCI_L1SS_CTL1 0x8 209 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 210 211 #define PCI_IRQ_LEGACY 0x01 212 #define PCI_IRQ_MSI 0x02 213 #define PCI_IRQ_MSIX 0x04 214 215 struct pci_dev; 216 217 struct pci_driver { 218 struct list_head node; 219 char *name; 220 const struct pci_device_id *id_table; 221 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 222 void (*remove)(struct pci_dev *dev); 223 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 224 int (*resume) (struct pci_dev *dev); /* Device woken up */ 225 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 226 driver_t bsddriver; 227 devclass_t bsdclass; 228 struct device_driver driver; 229 const struct pci_error_handlers *err_handler; 230 bool isdrm; 231 int bsd_probe_return; 232 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 233 const nvlist_t *pf_config); 234 void (*bsd_iov_uninit)(device_t dev); 235 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 236 const nvlist_t *vf_config); 237 }; 238 239 struct pci_bus { 240 struct pci_dev *self; 241 int domain; 242 int number; 243 }; 244 245 extern struct list_head pci_drivers; 246 extern struct list_head pci_devices; 247 extern spinlock_t pci_lock; 248 249 #define __devexit_p(x) x 250 251 #define module_pci_driver(_driver) \ 252 \ 253 static inline int \ 254 _pci_init(void) \ 255 { \ 256 \ 257 return (linux_pci_register_driver(&_driver)); \ 258 } \ 259 \ 260 static inline void \ 261 _pci_exit(void) \ 262 { \ 263 \ 264 linux_pci_unregister_driver(&_driver); \ 265 } \ 266 \ 267 module_init(_pci_init); \ 268 module_exit(_pci_exit) 269 270 /* 271 * If we find drivers accessing this from multiple KPIs we may have to 272 * refcount objects of this structure. 273 */ 274 struct pci_mmio_region { 275 TAILQ_ENTRY(pci_mmio_region) next; 276 struct resource *res; 277 int rid; 278 int type; 279 }; 280 281 struct pci_dev { 282 struct device dev; 283 struct list_head links; 284 struct pci_driver *pdrv; 285 struct pci_bus *bus; 286 struct pci_dev *root; 287 uint16_t device; 288 uint16_t vendor; 289 uint16_t subsystem_vendor; 290 uint16_t subsystem_device; 291 unsigned int irq; 292 unsigned int devfn; 293 uint32_t class; 294 uint8_t revision; 295 bool managed; /* devres "pcim_*(). */ 296 bool want_iomap_res; 297 bool msi_enabled; 298 bool msix_enabled; 299 phys_addr_t rom; 300 size_t romlen; 301 302 TAILQ_HEAD(, pci_mmio_region) mmio; 303 }; 304 305 /* We need some meta-struct to keep track of these for devres. */ 306 struct pci_devres { 307 bool enable_io; 308 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 309 uint8_t region_mask; 310 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 311 }; 312 struct pcim_iomap_devres { 313 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 314 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 315 }; 316 317 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 318 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 319 unsigned int flags); 320 321 /* Internal helper function(s). */ 322 struct pci_dev *lkpinew_pci_dev(device_t); 323 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev); 324 void lkpi_pci_devres_release(struct device *, void *); 325 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size); 326 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev); 327 void lkpi_pcim_iomap_table_release(struct device *, void *); 328 329 static inline int 330 pci_resource_type(struct pci_dev *pdev, int bar) 331 { 332 struct pci_map *pm; 333 334 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 335 if (!pm) 336 return (-1); 337 338 if (PCI_BAR_IO(pm->pm_value)) 339 return (SYS_RES_IOPORT); 340 else 341 return (SYS_RES_MEMORY); 342 } 343 344 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 345 struct resource_list *rl, int type, int rid); 346 347 static inline struct resource_list_entry * 348 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 349 { 350 struct pci_devinfo *dinfo; 351 struct resource_list *rl; 352 struct resource_list_entry *rle; 353 354 dinfo = device_get_ivars(pdev->dev.bsddev); 355 rl = &dinfo->resources; 356 rle = resource_list_find(rl, type, rid); 357 /* Reserve resources for this BAR if needed. */ 358 if (rle == NULL && reserve_bar) 359 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 360 return (rle); 361 } 362 363 static inline struct resource_list_entry * 364 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 365 { 366 int type; 367 368 type = pci_resource_type(pdev, bar); 369 if (type < 0) 370 return (NULL); 371 bar = PCIR_BAR(bar); 372 return (linux_pci_get_rle(pdev, type, bar, reserve)); 373 } 374 375 static inline struct device * 376 linux_pci_find_irq_dev(unsigned int irq) 377 { 378 struct pci_dev *pdev; 379 struct device *found; 380 381 found = NULL; 382 spin_lock(&pci_lock); 383 list_for_each_entry(pdev, &pci_devices, links) { 384 if (irq == pdev->dev.irq || 385 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 386 found = &pdev->dev; 387 break; 388 } 389 } 390 spin_unlock(&pci_lock); 391 return (found); 392 } 393 394 /* 395 * All drivers just seem to want to inspect the type not flags. 396 */ 397 static inline int 398 pci_resource_flags(struct pci_dev *pdev, int bar) 399 { 400 int type; 401 402 type = pci_resource_type(pdev, bar); 403 if (type < 0) 404 return (0); 405 return (1 << type); 406 } 407 408 static inline const char * 409 pci_name(struct pci_dev *d) 410 { 411 412 return device_get_desc(d->dev.bsddev); 413 } 414 415 static inline void * 416 pci_get_drvdata(struct pci_dev *pdev) 417 { 418 419 return dev_get_drvdata(&pdev->dev); 420 } 421 422 static inline void 423 pci_set_drvdata(struct pci_dev *pdev, void *data) 424 { 425 426 dev_set_drvdata(&pdev->dev, data); 427 } 428 429 static inline struct pci_dev * 430 pci_dev_get(struct pci_dev *pdev) 431 { 432 433 if (pdev != NULL) 434 get_device(&pdev->dev); 435 return (pdev); 436 } 437 438 static __inline void 439 pci_dev_put(struct pci_dev *pdev) 440 { 441 442 if (pdev != NULL) 443 put_device(&pdev->dev); 444 } 445 446 static inline int 447 pci_enable_device(struct pci_dev *pdev) 448 { 449 450 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 451 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 452 return (0); 453 } 454 455 static inline void 456 pci_disable_device(struct pci_dev *pdev) 457 { 458 459 pci_disable_busmaster(pdev->dev.bsddev); 460 } 461 462 static inline int 463 pci_set_master(struct pci_dev *pdev) 464 { 465 466 pci_enable_busmaster(pdev->dev.bsddev); 467 return (0); 468 } 469 470 static inline int 471 pci_set_power_state(struct pci_dev *pdev, int state) 472 { 473 474 pci_set_powerstate(pdev->dev.bsddev, state); 475 return (0); 476 } 477 478 static inline int 479 pci_clear_master(struct pci_dev *pdev) 480 { 481 482 pci_disable_busmaster(pdev->dev.bsddev); 483 return (0); 484 } 485 486 static inline bool 487 pci_is_root_bus(struct pci_bus *pbus) 488 { 489 490 return (pbus->self == NULL); 491 } 492 493 static inline struct pci_dev * 494 pci_upstream_bridge(struct pci_dev *pdev) 495 { 496 497 if (pci_is_root_bus(pdev->bus)) 498 return (NULL); 499 500 /* 501 * If we do not have a (proper) "upstream bridge" set, e.g., we point 502 * to ourselves, try to handle this case on the fly like we do 503 * for pcie_find_root_port(). 504 */ 505 if (pdev == pdev->bus->self) { 506 device_t bridge; 507 508 bridge = device_get_parent(pdev->dev.bsddev); 509 if (bridge == NULL) 510 goto done; 511 bridge = device_get_parent(bridge); 512 if (bridge == NULL) 513 goto done; 514 if (device_get_devclass(device_get_parent(bridge)) != 515 devclass_find("pci")) 516 goto done; 517 518 /* 519 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 520 * for it so it can be returned. 521 */ 522 pdev->bus->self = lkpinew_pci_dev(bridge); 523 } 524 done: 525 return (pdev->bus->self); 526 } 527 528 static inline struct pci_devres * 529 lkpi_pci_devres_find(struct pci_dev *pdev) 530 { 531 532 if (!pdev->managed) 533 return (NULL); 534 535 return (lkpi_pci_devres_get_alloc(pdev)); 536 } 537 538 static inline void 539 pci_release_region(struct pci_dev *pdev, int bar) 540 { 541 struct resource_list_entry *rle; 542 struct pci_devres *dr; 543 struct pci_mmio_region *mmio, *p; 544 545 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 546 return; 547 548 /* 549 * As we implicitly track the requests we also need to clear them on 550 * release. Do clear before resource release. 551 */ 552 dr = lkpi_pci_devres_find(pdev); 553 if (dr != NULL) { 554 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 555 " region_table res %p != rel->res %p\n", __func__, pdev, 556 bar, dr->region_table[bar], rle->res)); 557 dr->region_table[bar] = NULL; 558 dr->region_mask &= ~(1 << bar); 559 } 560 561 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 562 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 563 continue; 564 TAILQ_REMOVE(&pdev->mmio, mmio, next); 565 free(mmio, M_DEVBUF); 566 } 567 568 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 569 } 570 571 static inline void 572 pci_release_regions(struct pci_dev *pdev) 573 { 574 int i; 575 576 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 577 pci_release_region(pdev, i); 578 } 579 580 static inline int 581 pci_request_regions(struct pci_dev *pdev, const char *res_name) 582 { 583 int error; 584 int i; 585 586 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 587 error = pci_request_region(pdev, i, res_name); 588 if (error && error != -ENODEV) { 589 pci_release_regions(pdev); 590 return (error); 591 } 592 } 593 return (0); 594 } 595 596 static inline void 597 lkpi_pci_disable_msix(struct pci_dev *pdev) 598 { 599 600 pci_release_msi(pdev->dev.bsddev); 601 602 /* 603 * The MSIX IRQ numbers associated with this PCI device are no 604 * longer valid and might be re-assigned. Make sure 605 * linux_pci_find_irq_dev() does no longer see them by 606 * resetting their references to zero: 607 */ 608 pdev->dev.irq_start = 0; 609 pdev->dev.irq_end = 0; 610 pdev->msix_enabled = false; 611 } 612 /* Only for consistency. No conflict on that one. */ 613 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 614 615 static inline void 616 lkpi_pci_disable_msi(struct pci_dev *pdev) 617 { 618 619 pci_release_msi(pdev->dev.bsddev); 620 621 pdev->dev.irq_start = 0; 622 pdev->dev.irq_end = 0; 623 pdev->irq = pdev->dev.irq; 624 pdev->msi_enabled = false; 625 } 626 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 627 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 628 629 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 630 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 631 632 static inline bus_addr_t 633 pci_bus_address(struct pci_dev *pdev, int bar) 634 { 635 636 return (pci_resource_start(pdev, bar)); 637 } 638 639 #define PCI_CAP_ID_EXP PCIY_EXPRESS 640 #define PCI_CAP_ID_PCIX PCIY_PCIX 641 #define PCI_CAP_ID_AGP PCIY_AGP 642 #define PCI_CAP_ID_PM PCIY_PMG 643 644 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 645 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 646 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 647 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 648 #define PCI_EXP_LNKSTA PCIER_LINK_STA 649 650 static inline int 651 pci_find_capability(struct pci_dev *pdev, int capid) 652 { 653 int reg; 654 655 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 656 return (0); 657 return (reg); 658 } 659 660 static inline int pci_pcie_cap(struct pci_dev *dev) 661 { 662 return pci_find_capability(dev, PCI_CAP_ID_EXP); 663 } 664 665 static inline int 666 pci_find_ext_capability(struct pci_dev *pdev, int capid) 667 { 668 int reg; 669 670 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 671 return (0); 672 return (reg); 673 } 674 675 #define PCIM_PCAP_PME_SHIFT 11 676 static __inline bool 677 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 678 { 679 struct pci_devinfo *dinfo; 680 pcicfgregs *cfg; 681 682 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 683 return (false); 684 685 dinfo = device_get_ivars(pdev->dev.bsddev); 686 cfg = &dinfo->cfg; 687 688 if (cfg->pp.pp_cap == 0) 689 return (false); 690 691 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 692 return (true); 693 694 return (false); 695 } 696 697 static inline int 698 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 699 { 700 701 if (!pci_enable_aspm) 702 return (-EPERM); 703 704 return (-ENXIO); 705 } 706 707 static inline int 708 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 709 { 710 711 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 712 return (0); 713 } 714 715 static inline int 716 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 717 { 718 719 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 720 return (0); 721 } 722 723 static inline int 724 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 725 { 726 727 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 728 return (0); 729 } 730 731 static inline int 732 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 733 { 734 735 pci_write_config(pdev->dev.bsddev, where, val, 1); 736 return (0); 737 } 738 739 static inline int 740 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 741 { 742 743 pci_write_config(pdev->dev.bsddev, where, val, 2); 744 return (0); 745 } 746 747 static inline int 748 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 749 { 750 751 pci_write_config(pdev->dev.bsddev, where, val, 4); 752 return (0); 753 } 754 755 int linux_pci_register_driver(struct pci_driver *pdrv); 756 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 757 void linux_pci_unregister_driver(struct pci_driver *pdrv); 758 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 759 760 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 761 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 762 763 struct msix_entry { 764 int entry; 765 int vector; 766 }; 767 768 /* 769 * Enable msix, positive errors indicate actual number of available 770 * vectors. Negative errors are failures. 771 * 772 * NB: define added to prevent this definition of pci_enable_msix from 773 * clashing with the native FreeBSD version. 774 */ 775 #define pci_enable_msix(...) \ 776 linux_pci_enable_msix(__VA_ARGS__) 777 778 static inline int 779 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 780 { 781 struct resource_list_entry *rle; 782 int error; 783 int avail; 784 int i; 785 786 avail = pci_msix_count(pdev->dev.bsddev); 787 if (avail < nreq) { 788 if (avail == 0) 789 return -EINVAL; 790 return avail; 791 } 792 avail = nreq; 793 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 794 return error; 795 /* 796 * Handle case where "pci_alloc_msix()" may allocate less 797 * interrupts than available and return with no error: 798 */ 799 if (avail < nreq) { 800 pci_release_msi(pdev->dev.bsddev); 801 return avail; 802 } 803 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 804 pdev->dev.irq_start = rle->start; 805 pdev->dev.irq_end = rle->start + avail; 806 for (i = 0; i < nreq; i++) 807 entries[i].vector = pdev->dev.irq_start + i; 808 pdev->msix_enabled = true; 809 return (0); 810 } 811 812 #define pci_enable_msix_range(...) \ 813 linux_pci_enable_msix_range(__VA_ARGS__) 814 815 static inline int 816 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 817 int minvec, int maxvec) 818 { 819 int nvec = maxvec; 820 int rc; 821 822 if (maxvec < minvec) 823 return (-ERANGE); 824 825 do { 826 rc = pci_enable_msix(dev, entries, nvec); 827 if (rc < 0) { 828 return (rc); 829 } else if (rc > 0) { 830 if (rc < minvec) 831 return (-ENOSPC); 832 nvec = rc; 833 } 834 } while (rc); 835 return (nvec); 836 } 837 838 #define pci_enable_msi(pdev) \ 839 linux_pci_enable_msi(pdev) 840 841 static inline int 842 pci_enable_msi(struct pci_dev *pdev) 843 { 844 struct resource_list_entry *rle; 845 int error; 846 int avail; 847 848 avail = pci_msi_count(pdev->dev.bsddev); 849 if (avail < 1) 850 return -EINVAL; 851 852 avail = 1; /* this function only enable one MSI IRQ */ 853 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 854 return error; 855 856 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 857 pdev->dev.irq_start = rle->start; 858 pdev->dev.irq_end = rle->start + avail; 859 pdev->irq = rle->start; 860 pdev->msi_enabled = true; 861 return (0); 862 } 863 864 static inline int 865 pci_channel_offline(struct pci_dev *pdev) 866 { 867 868 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 869 } 870 871 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 872 { 873 return -ENODEV; 874 } 875 876 static inline void pci_disable_sriov(struct pci_dev *dev) 877 { 878 } 879 880 static inline void * 881 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 882 { 883 struct resource *res; 884 885 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 886 if (res == NULL) 887 return (NULL); 888 /* This is a FreeBSD extension so we can use bus_*(). */ 889 if (pdev->want_iomap_res) 890 return (res); 891 return ((void *)rman_get_bushandle(res)); 892 } 893 894 static inline void 895 pci_iounmap(struct pci_dev *pdev, void *res) 896 { 897 struct pci_mmio_region *mmio, *p; 898 899 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 900 if (res != (void *)rman_get_bushandle(mmio->res)) 901 continue; 902 bus_release_resource(pdev->dev.bsddev, 903 mmio->type, mmio->rid, mmio->res); 904 TAILQ_REMOVE(&pdev->mmio, mmio, next); 905 free(mmio, M_DEVBUF); 906 return; 907 } 908 } 909 910 static inline void 911 lkpi_pci_save_state(struct pci_dev *pdev) 912 { 913 914 pci_save_state(pdev->dev.bsddev); 915 } 916 917 static inline void 918 lkpi_pci_restore_state(struct pci_dev *pdev) 919 { 920 921 pci_restore_state(pdev->dev.bsddev); 922 } 923 924 #define pci_save_state(dev) lkpi_pci_save_state(dev) 925 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 926 927 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 928 const struct pci_device_id _table[] __devinitdata 929 930 /* XXX This should not be necessary. */ 931 #define pcix_set_mmrbc(d, v) 0 932 #define pcix_get_max_mmrbc(d) 0 933 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 934 935 #define PCI_DMA_BIDIRECTIONAL 0 936 #define PCI_DMA_TODEVICE 1 937 #define PCI_DMA_FROMDEVICE 2 938 #define PCI_DMA_NONE 3 939 940 #define pci_pool dma_pool 941 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 942 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 943 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 944 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 945 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 946 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 947 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 948 _size, _vaddr, _dma_handle) 949 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 950 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 951 _sg, _nents, (enum dma_data_direction)_dir) 952 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 953 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 954 (_ptr), (_size), (enum dma_data_direction)_dir) 955 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 956 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 957 _addr, _size, (enum dma_data_direction)_dir) 958 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 959 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 960 _sg, _nents, (enum dma_data_direction)_dir) 961 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 962 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 963 _offset, _size, (enum dma_data_direction)_dir) 964 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 965 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 966 _dma_address, _size, (enum dma_data_direction)_dir) 967 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 968 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 969 dma_mapping_error(&(_pdev)->dev, _dma_addr) 970 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 971 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 972 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 973 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 974 #define pci_unmap_addr dma_unmap_addr 975 #define pci_unmap_addr_set dma_unmap_addr_set 976 #define pci_unmap_len dma_unmap_len 977 #define pci_unmap_len_set dma_unmap_len_set 978 979 typedef unsigned int __bitwise pci_channel_state_t; 980 typedef unsigned int __bitwise pci_ers_result_t; 981 982 enum pci_channel_state { 983 pci_channel_io_normal = 1, 984 pci_channel_io_frozen = 2, 985 pci_channel_io_perm_failure = 3, 986 }; 987 988 enum pci_ers_result { 989 PCI_ERS_RESULT_NONE = 1, 990 PCI_ERS_RESULT_CAN_RECOVER = 2, 991 PCI_ERS_RESULT_NEED_RESET = 3, 992 PCI_ERS_RESULT_DISCONNECT = 4, 993 PCI_ERS_RESULT_RECOVERED = 5, 994 }; 995 996 /* PCI bus error event callbacks */ 997 struct pci_error_handlers { 998 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 999 enum pci_channel_state error); 1000 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1001 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1002 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1003 void (*resume)(struct pci_dev *dev); 1004 }; 1005 1006 /* FreeBSD does not support SRIOV - yet */ 1007 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1008 { 1009 return dev; 1010 } 1011 1012 static inline bool pci_is_pcie(struct pci_dev *dev) 1013 { 1014 return !!pci_pcie_cap(dev); 1015 } 1016 1017 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1018 { 1019 int pos; 1020 u16 reg16; 1021 1022 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1023 if (!pos) 1024 return 0; 1025 1026 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1027 1028 return reg16; 1029 } 1030 1031 static inline int pci_pcie_type(struct pci_dev *dev) 1032 { 1033 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1034 } 1035 1036 static inline int pcie_cap_version(struct pci_dev *dev) 1037 { 1038 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1039 } 1040 1041 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1042 { 1043 int type = pci_pcie_type(dev); 1044 1045 return pcie_cap_version(dev) > 1 || 1046 type == PCI_EXP_TYPE_ROOT_PORT || 1047 type == PCI_EXP_TYPE_ENDPOINT || 1048 type == PCI_EXP_TYPE_LEG_END; 1049 } 1050 1051 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1052 { 1053 return true; 1054 } 1055 1056 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1057 { 1058 int type = pci_pcie_type(dev); 1059 1060 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1061 (type == PCI_EXP_TYPE_DOWNSTREAM && 1062 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1063 } 1064 1065 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1066 { 1067 int type = pci_pcie_type(dev); 1068 1069 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1070 type == PCI_EXP_TYPE_RC_EC; 1071 } 1072 1073 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1074 { 1075 if (!pci_is_pcie(dev)) 1076 return false; 1077 1078 switch (pos) { 1079 case PCI_EXP_FLAGS_TYPE: 1080 return true; 1081 case PCI_EXP_DEVCAP: 1082 case PCI_EXP_DEVCTL: 1083 case PCI_EXP_DEVSTA: 1084 return pcie_cap_has_devctl(dev); 1085 case PCI_EXP_LNKCAP: 1086 case PCI_EXP_LNKCTL: 1087 case PCI_EXP_LNKSTA: 1088 return pcie_cap_has_lnkctl(dev); 1089 case PCI_EXP_SLTCAP: 1090 case PCI_EXP_SLTCTL: 1091 case PCI_EXP_SLTSTA: 1092 return pcie_cap_has_sltctl(dev); 1093 case PCI_EXP_RTCTL: 1094 case PCI_EXP_RTCAP: 1095 case PCI_EXP_RTSTA: 1096 return pcie_cap_has_rtctl(dev); 1097 case PCI_EXP_DEVCAP2: 1098 case PCI_EXP_DEVCTL2: 1099 case PCI_EXP_LNKCAP2: 1100 case PCI_EXP_LNKCTL2: 1101 case PCI_EXP_LNKSTA2: 1102 return pcie_cap_version(dev) > 1; 1103 default: 1104 return false; 1105 } 1106 } 1107 1108 static inline int 1109 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1110 { 1111 if (pos & 3) 1112 return -EINVAL; 1113 1114 if (!pcie_capability_reg_implemented(dev, pos)) 1115 return -EINVAL; 1116 1117 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1118 } 1119 1120 static inline int 1121 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1122 { 1123 if (pos & 3) 1124 return -EINVAL; 1125 1126 if (!pcie_capability_reg_implemented(dev, pos)) 1127 return -EINVAL; 1128 1129 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1130 } 1131 1132 static inline int 1133 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1134 { 1135 if (pos & 1) 1136 return -EINVAL; 1137 1138 if (!pcie_capability_reg_implemented(dev, pos)) 1139 return 0; 1140 1141 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1142 } 1143 1144 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1145 enum pci_bus_speed *speed, enum pcie_link_width *width) 1146 { 1147 *speed = PCI_SPEED_UNKNOWN; 1148 *width = PCIE_LNK_WIDTH_UNKNOWN; 1149 return (0); 1150 } 1151 1152 static inline int 1153 pci_num_vf(struct pci_dev *dev) 1154 { 1155 return (0); 1156 } 1157 1158 static inline enum pci_bus_speed 1159 pcie_get_speed_cap(struct pci_dev *dev) 1160 { 1161 device_t root; 1162 uint32_t lnkcap, lnkcap2; 1163 int error, pos; 1164 1165 root = device_get_parent(dev->dev.bsddev); 1166 if (root == NULL) 1167 return (PCI_SPEED_UNKNOWN); 1168 root = device_get_parent(root); 1169 if (root == NULL) 1170 return (PCI_SPEED_UNKNOWN); 1171 root = device_get_parent(root); 1172 if (root == NULL) 1173 return (PCI_SPEED_UNKNOWN); 1174 1175 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1176 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1177 return (PCI_SPEED_UNKNOWN); 1178 1179 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1180 return (PCI_SPEED_UNKNOWN); 1181 1182 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1183 1184 if (lnkcap2) { /* PCIe r3.0-compliant */ 1185 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1186 return (PCIE_SPEED_2_5GT); 1187 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1188 return (PCIE_SPEED_5_0GT); 1189 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1190 return (PCIE_SPEED_8_0GT); 1191 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1192 return (PCIE_SPEED_16_0GT); 1193 } else { /* pre-r3.0 */ 1194 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1195 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1196 return (PCIE_SPEED_2_5GT); 1197 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1198 return (PCIE_SPEED_5_0GT); 1199 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1200 return (PCIE_SPEED_8_0GT); 1201 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1202 return (PCIE_SPEED_16_0GT); 1203 } 1204 return (PCI_SPEED_UNKNOWN); 1205 } 1206 1207 static inline enum pcie_link_width 1208 pcie_get_width_cap(struct pci_dev *dev) 1209 { 1210 uint32_t lnkcap; 1211 1212 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1213 if (lnkcap) 1214 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1215 1216 return (PCIE_LNK_WIDTH_UNKNOWN); 1217 } 1218 1219 static inline int 1220 pcie_get_mps(struct pci_dev *dev) 1221 { 1222 return (pci_get_max_payload(dev->dev.bsddev)); 1223 } 1224 1225 static inline uint32_t 1226 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1227 { 1228 1229 switch(spd) { 1230 case PCIE_SPEED_16_0GT: 1231 return (16000 * 128 / 130); 1232 case PCIE_SPEED_8_0GT: 1233 return (8000 * 128 / 130); 1234 case PCIE_SPEED_5_0GT: 1235 return (5000 * 8 / 10); 1236 case PCIE_SPEED_2_5GT: 1237 return (2500 * 8 / 10); 1238 default: 1239 return (0); 1240 } 1241 } 1242 1243 static inline uint32_t 1244 pcie_bandwidth_available(struct pci_dev *pdev, 1245 struct pci_dev **limiting, 1246 enum pci_bus_speed *speed, 1247 enum pcie_link_width *width) 1248 { 1249 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1250 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1251 1252 if (speed) 1253 *speed = nspeed; 1254 if (width) 1255 *width = nwidth; 1256 1257 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1258 } 1259 1260 static inline struct pci_dev * 1261 pcie_find_root_port(struct pci_dev *pdev) 1262 { 1263 device_t root; 1264 1265 if (pdev->root != NULL) 1266 return (pdev->root); 1267 1268 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1269 if (root == NULL) 1270 return (NULL); 1271 1272 pdev->root = lkpinew_pci_dev(root); 1273 return (pdev->root); 1274 } 1275 1276 /* This is needed when people rip out the device "HotPlug". */ 1277 static inline void 1278 pci_lock_rescan_remove(void) 1279 { 1280 } 1281 1282 static inline void 1283 pci_unlock_rescan_remove(void) 1284 { 1285 } 1286 1287 static __inline void 1288 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1289 { 1290 } 1291 1292 /* 1293 * The following functions can be used to attach/detach the LinuxKPI's 1294 * PCI device runtime. The pci_driver and pci_device_id pointer is 1295 * allowed to be NULL. Other pointers must be all valid. 1296 * The pci_dev structure should be zero-initialized before passed 1297 * to the linux_pci_attach_device function. 1298 */ 1299 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1300 const struct pci_device_id *, struct pci_dev *); 1301 extern int linux_pci_detach_device(struct pci_dev *); 1302 1303 static inline int 1304 pci_dev_present(const struct pci_device_id *cur) 1305 { 1306 while (cur != NULL && (cur->vendor || cur->device)) { 1307 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1308 return (1); 1309 } 1310 cur++; 1311 } 1312 return (0); 1313 } 1314 1315 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1316 unsigned int bus, unsigned int devfn); 1317 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1318 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1319 1320 static inline int 1321 pci_domain_nr(struct pci_bus *pbus) 1322 { 1323 1324 return (pbus->domain); 1325 } 1326 1327 static inline int 1328 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1329 int pos, uint32_t *val, int len) 1330 { 1331 1332 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1333 return (0); 1334 } 1335 1336 static inline int 1337 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1338 { 1339 uint32_t tmp; 1340 int ret; 1341 1342 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1343 *val = (u16)tmp; 1344 return (ret); 1345 } 1346 1347 static inline int 1348 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1349 { 1350 uint32_t tmp; 1351 int ret; 1352 1353 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1354 *val = (u8)tmp; 1355 return (ret); 1356 } 1357 1358 static inline int 1359 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1360 uint32_t val, int size) 1361 { 1362 1363 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1364 return (0); 1365 } 1366 1367 static inline int 1368 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1369 uint8_t val) 1370 { 1371 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1372 } 1373 1374 static inline int 1375 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1376 uint16_t val) 1377 { 1378 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1379 } 1380 1381 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1382 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1383 1384 /* -------------------------------------------------------------------------- */ 1385 1386 static inline int 1387 pcim_enable_device(struct pci_dev *pdev) 1388 { 1389 struct pci_devres *dr; 1390 int error; 1391 1392 /* Here we cannot run through the pdev->managed check. */ 1393 dr = lkpi_pci_devres_get_alloc(pdev); 1394 if (dr == NULL) 1395 return (-ENOMEM); 1396 1397 /* If resources were enabled before do not do it again. */ 1398 if (dr->enable_io) 1399 return (0); 1400 1401 error = pci_enable_device(pdev); 1402 if (error == 0) 1403 dr->enable_io = true; 1404 1405 /* This device is not managed. */ 1406 pdev->managed = true; 1407 1408 return (error); 1409 } 1410 1411 static inline void __iomem ** 1412 pcim_iomap_table(struct pci_dev *pdev) 1413 { 1414 struct pcim_iomap_devres *dr; 1415 1416 dr = lkpi_pcim_iomap_devres_find(pdev); 1417 if (dr == NULL) 1418 return (NULL); 1419 1420 /* 1421 * If the driver has manually set a flag to be able to request the 1422 * resource to use bus_read/write_<n>, return the shadow table. 1423 */ 1424 if (pdev->want_iomap_res) 1425 return ((void **)dr->res_table); 1426 1427 /* This is the Linux default. */ 1428 return (dr->mmio_table); 1429 } 1430 1431 static inline int 1432 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1433 { 1434 struct pcim_iomap_devres *dr; 1435 void *res; 1436 uint32_t mappings, requests, req_mask; 1437 int bar, error; 1438 1439 dr = lkpi_pcim_iomap_devres_find(pdev); 1440 if (dr == NULL) 1441 return (-ENOMEM); 1442 1443 /* Request all the BARs ("regions") we do not iomap. */ 1444 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1445 for (bar = requests = 0; requests != req_mask; bar++) { 1446 if ((req_mask & (1 << bar)) == 0) 1447 continue; 1448 error = pci_request_region(pdev, bar, name); 1449 if (error != 0 && error != -ENODEV) 1450 goto err; 1451 requests |= (1 << bar); 1452 } 1453 1454 /* Now iomap all the requested (by "mask") ones. */ 1455 for (bar = mappings = 0; mappings != mask; bar++) { 1456 if ((mask & (1 << bar)) == 0) 1457 continue; 1458 1459 /* Request double is not allowed. */ 1460 if (dr->mmio_table[bar] != NULL) { 1461 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1462 __func__, bar, dr->mmio_table[bar]); 1463 goto err; 1464 } 1465 1466 res = _lkpi_pci_iomap(pdev, bar, 0); 1467 if (res == NULL) 1468 goto err; 1469 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1470 dr->res_table[bar] = res; 1471 1472 mappings |= (1 << bar); 1473 } 1474 1475 return (0); 1476 1477 err: 1478 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1479 if ((mappings & (1 << bar)) != 0) { 1480 res = dr->mmio_table[bar]; 1481 if (res == NULL) 1482 continue; 1483 pci_iounmap(pdev, res); 1484 } else if ((requests & (1 << bar)) != 0) { 1485 pci_release_region(pdev, bar); 1486 } 1487 } 1488 1489 return (-EINVAL); 1490 } 1491 1492 /* This is a FreeBSD extension so we can use bus_*(). */ 1493 static inline void 1494 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1495 { 1496 pdev->want_iomap_res = true; 1497 } 1498 1499 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1500