1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUX_PCI_H_ 36 #define _LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <sys/rman.h> 47 #include <sys/bus.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 #define MODULE_DEVICE_TABLE(bus, table) 74 75 #define PCI_ANY_ID -1U 76 77 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 78 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 79 #define PCI_FUNC(devfn) ((devfn) & 0x07) 80 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 81 82 #define PCI_VDEVICE(_vendor, _device) \ 83 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 84 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 85 #define PCI_DEVICE(_vendor, _device) \ 86 .vendor = (_vendor), .device = (_device), \ 87 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 88 89 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 90 91 #define PCI_VENDOR_ID PCIR_DEVVENDOR 92 #define PCI_COMMAND PCIR_COMMAND 93 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 94 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 95 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 96 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 97 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 98 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 99 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 100 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 101 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 102 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 103 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 104 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 105 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 106 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 107 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 108 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 109 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 110 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 111 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 112 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 113 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 114 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 115 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 116 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 117 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 118 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 119 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 120 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 121 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 122 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 123 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 124 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 125 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 126 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 127 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 128 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 129 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 130 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 131 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 132 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 133 134 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 135 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 136 #define PCI_EXP_DEVSTA_TRPND 0x0020 137 138 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 139 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 140 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 141 142 enum pci_bus_speed { 143 PCI_SPEED_UNKNOWN = -1, 144 PCIE_SPEED_2_5GT, 145 PCIE_SPEED_5_0GT, 146 PCIE_SPEED_8_0GT, 147 PCIE_SPEED_16_0GT, 148 }; 149 150 enum pcie_link_width { 151 PCIE_LNK_WIDTH_RESRV = 0x00, 152 PCIE_LNK_X1 = 0x01, 153 PCIE_LNK_X2 = 0x02, 154 PCIE_LNK_X4 = 0x04, 155 PCIE_LNK_X8 = 0x08, 156 PCIE_LNK_X12 = 0x0c, 157 PCIE_LNK_X16 = 0x10, 158 PCIE_LNK_X32 = 0x20, 159 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 160 }; 161 162 #define PCIE_LINK_STATE_L0S 0x00000001 163 #define PCIE_LINK_STATE_L1 0x00000002 164 #define PCIE_LINK_STATE_CLKPM 0x00000004 165 166 typedef int pci_power_t; 167 168 #define PCI_D0 PCI_POWERSTATE_D0 169 #define PCI_D1 PCI_POWERSTATE_D1 170 #define PCI_D2 PCI_POWERSTATE_D2 171 #define PCI_D3hot PCI_POWERSTATE_D3 172 #define PCI_D3cold 4 173 174 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 175 176 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 177 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 178 179 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 180 181 struct pci_dev; 182 183 struct pci_driver { 184 struct list_head links; 185 char *name; 186 const struct pci_device_id *id_table; 187 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 188 void (*remove)(struct pci_dev *dev); 189 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 190 int (*resume) (struct pci_dev *dev); /* Device woken up */ 191 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 192 driver_t bsddriver; 193 devclass_t bsdclass; 194 struct device_driver driver; 195 const struct pci_error_handlers *err_handler; 196 bool isdrm; 197 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 198 const nvlist_t *pf_config); 199 void (*bsd_iov_uninit)(device_t dev); 200 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 201 const nvlist_t *vf_config); 202 }; 203 204 struct pci_bus { 205 struct pci_dev *self; 206 int domain; 207 int number; 208 }; 209 210 extern struct list_head pci_drivers; 211 extern struct list_head pci_devices; 212 extern spinlock_t pci_lock; 213 214 #define __devexit_p(x) x 215 216 /* 217 * If we find drivers accessing this from multiple KPIs we may have to 218 * refcount objects of this structure. 219 */ 220 struct pci_mmio_region { 221 TAILQ_ENTRY(pci_mmio_region) next; 222 struct resource *res; 223 int rid; 224 int type; 225 }; 226 227 struct pci_dev { 228 struct device dev; 229 struct list_head links; 230 struct pci_driver *pdrv; 231 struct pci_bus *bus; 232 struct pci_dev *root; 233 uint16_t device; 234 uint16_t vendor; 235 uint16_t subsystem_vendor; 236 uint16_t subsystem_device; 237 unsigned int irq; 238 unsigned int devfn; 239 uint32_t class; 240 uint8_t revision; 241 bool managed; /* devres "pcim_*(). */ 242 bool want_iomap_res; 243 bool msi_enabled; 244 bool msix_enabled; 245 phys_addr_t rom; 246 size_t romlen; 247 248 TAILQ_HEAD(, pci_mmio_region) mmio; 249 }; 250 251 /* We need some meta-struct to keep track of these for devres. */ 252 struct pci_devres { 253 bool enable_io; 254 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 255 uint8_t region_mask; 256 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 257 }; 258 struct pcim_iomap_devres { 259 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 260 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 261 }; 262 263 /* Internal helper function(s). */ 264 struct pci_dev *lkpinew_pci_dev(device_t); 265 void lkpi_pci_devres_release(struct device *, void *); 266 void lkpi_pcim_iomap_table_release(struct device *, void *); 267 268 static inline int 269 pci_resource_type(struct pci_dev *pdev, int bar) 270 { 271 struct pci_map *pm; 272 273 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 274 if (!pm) 275 return (-1); 276 277 if (PCI_BAR_IO(pm->pm_value)) 278 return (SYS_RES_IOPORT); 279 else 280 return (SYS_RES_MEMORY); 281 } 282 283 static inline struct resource_list_entry * 284 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 285 { 286 struct pci_devinfo *dinfo; 287 struct resource_list *rl; 288 289 dinfo = device_get_ivars(pdev->dev.bsddev); 290 rl = &dinfo->resources; 291 return resource_list_find(rl, type, rid); 292 } 293 294 static inline struct resource_list_entry * 295 linux_pci_get_bar(struct pci_dev *pdev, int bar) 296 { 297 int type; 298 299 type = pci_resource_type(pdev, bar); 300 if (type < 0) 301 return (NULL); 302 bar = PCIR_BAR(bar); 303 return (linux_pci_get_rle(pdev, type, bar)); 304 } 305 306 static inline struct device * 307 linux_pci_find_irq_dev(unsigned int irq) 308 { 309 struct pci_dev *pdev; 310 struct device *found; 311 312 found = NULL; 313 spin_lock(&pci_lock); 314 list_for_each_entry(pdev, &pci_devices, links) { 315 if (irq == pdev->dev.irq || 316 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 317 found = &pdev->dev; 318 break; 319 } 320 } 321 spin_unlock(&pci_lock); 322 return (found); 323 } 324 325 /* 326 * All drivers just seem to want to inspect the type not flags. 327 */ 328 static inline int 329 pci_resource_flags(struct pci_dev *pdev, int bar) 330 { 331 int type; 332 333 type = pci_resource_type(pdev, bar); 334 if (type < 0) 335 return (0); 336 return (1 << type); 337 } 338 339 static inline const char * 340 pci_name(struct pci_dev *d) 341 { 342 343 return device_get_desc(d->dev.bsddev); 344 } 345 346 static inline void * 347 pci_get_drvdata(struct pci_dev *pdev) 348 { 349 350 return dev_get_drvdata(&pdev->dev); 351 } 352 353 static inline void 354 pci_set_drvdata(struct pci_dev *pdev, void *data) 355 { 356 357 dev_set_drvdata(&pdev->dev, data); 358 } 359 360 static inline struct pci_dev * 361 pci_dev_get(struct pci_dev *pdev) 362 { 363 364 if (pdev != NULL) 365 get_device(&pdev->dev); 366 return (pdev); 367 } 368 369 static __inline void 370 pci_dev_put(struct pci_dev *pdev) 371 { 372 373 if (pdev != NULL) 374 put_device(&pdev->dev); 375 } 376 377 static inline int 378 pci_enable_device(struct pci_dev *pdev) 379 { 380 381 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 382 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 383 return (0); 384 } 385 386 static inline void 387 pci_disable_device(struct pci_dev *pdev) 388 { 389 390 pci_disable_busmaster(pdev->dev.bsddev); 391 } 392 393 static inline int 394 pci_set_master(struct pci_dev *pdev) 395 { 396 397 pci_enable_busmaster(pdev->dev.bsddev); 398 return (0); 399 } 400 401 static inline int 402 pci_set_power_state(struct pci_dev *pdev, int state) 403 { 404 405 pci_set_powerstate(pdev->dev.bsddev, state); 406 return (0); 407 } 408 409 static inline int 410 pci_clear_master(struct pci_dev *pdev) 411 { 412 413 pci_disable_busmaster(pdev->dev.bsddev); 414 return (0); 415 } 416 417 static inline struct pci_devres * 418 lkpi_pci_devres_get_alloc(struct pci_dev *pdev) 419 { 420 struct pci_devres *dr; 421 422 dr = lkpi_devres_find(&pdev->dev, lkpi_pci_devres_release, NULL, NULL); 423 if (dr == NULL) { 424 dr = lkpi_devres_alloc(lkpi_pci_devres_release, sizeof(*dr), 425 GFP_KERNEL | __GFP_ZERO); 426 if (dr != NULL) 427 lkpi_devres_add(&pdev->dev, dr); 428 } 429 430 return (dr); 431 } 432 static inline struct pci_devres * 433 lkpi_pci_devres_find(struct pci_dev *pdev) 434 { 435 436 if (!pdev->managed) 437 return (NULL); 438 439 return (lkpi_pci_devres_get_alloc(pdev)); 440 } 441 442 static inline int 443 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 444 { 445 struct resource *res; 446 struct pci_devres *dr; 447 struct pci_mmio_region *mmio; 448 int rid; 449 int type; 450 451 type = pci_resource_type(pdev, bar); 452 if (type < 0) 453 return (-ENODEV); 454 rid = PCIR_BAR(bar); 455 res = bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 456 RF_ACTIVE|RF_SHAREABLE); 457 if (res == NULL) { 458 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 459 "bar %d type %d rid %d\n", 460 __func__, bar, type, PCIR_BAR(bar)); 461 return (-ENODEV); 462 } 463 464 /* 465 * It seems there is an implicit devres tracking on these if the device 466 * is managed; otherwise the resources are not automatiaclly freed on 467 * FreeBSD/LinuxKPI tough they should be/are expected to be by Linux 468 * drivers. 469 */ 470 dr = lkpi_pci_devres_find(pdev); 471 if (dr != NULL) { 472 dr->region_mask |= (1 << bar); 473 dr->region_table[bar] = res; 474 } 475 476 /* Even if the device is not managed we need to track it for iomap. */ 477 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 478 mmio->rid = PCIR_BAR(bar); 479 mmio->type = type; 480 mmio->res = res; 481 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 482 483 return (0); 484 } 485 486 static inline void 487 pci_release_region(struct pci_dev *pdev, int bar) 488 { 489 struct resource_list_entry *rle; 490 struct pci_devres *dr; 491 struct pci_mmio_region *mmio, *p; 492 493 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 494 return; 495 496 /* 497 * As we implicitly track the requests we also need to clear them on 498 * release. Do clear before resource release. 499 */ 500 dr = lkpi_pci_devres_find(pdev); 501 if (dr != NULL) { 502 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 503 " region_table res %p != rel->res %p\n", __func__, pdev, 504 bar, dr->region_table[bar], rle->res)); 505 dr->region_table[bar] = NULL; 506 dr->region_mask &= ~(1 << bar); 507 } 508 509 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 510 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 511 continue; 512 TAILQ_REMOVE(&pdev->mmio, mmio, next); 513 free(mmio, M_DEVBUF); 514 } 515 516 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 517 } 518 519 static inline void 520 pci_release_regions(struct pci_dev *pdev) 521 { 522 int i; 523 524 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 525 pci_release_region(pdev, i); 526 } 527 528 static inline int 529 pci_request_regions(struct pci_dev *pdev, const char *res_name) 530 { 531 int error; 532 int i; 533 534 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 535 error = pci_request_region(pdev, i, res_name); 536 if (error && error != -ENODEV) { 537 pci_release_regions(pdev); 538 return (error); 539 } 540 } 541 return (0); 542 } 543 544 static inline void 545 lkpi_pci_disable_msix(struct pci_dev *pdev) 546 { 547 548 pci_release_msi(pdev->dev.bsddev); 549 550 /* 551 * The MSIX IRQ numbers associated with this PCI device are no 552 * longer valid and might be re-assigned. Make sure 553 * linux_pci_find_irq_dev() does no longer see them by 554 * resetting their references to zero: 555 */ 556 pdev->dev.irq_start = 0; 557 pdev->dev.irq_end = 0; 558 pdev->msix_enabled = false; 559 } 560 /* Only for consistency. No conflict on that one. */ 561 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 562 563 static inline void 564 lkpi_pci_disable_msi(struct pci_dev *pdev) 565 { 566 567 pci_release_msi(pdev->dev.bsddev); 568 569 pdev->dev.irq_start = 0; 570 pdev->dev.irq_end = 0; 571 pdev->irq = pdev->dev.irq; 572 pdev->msi_enabled = false; 573 } 574 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 575 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 576 577 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 578 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 579 580 static inline bus_addr_t 581 pci_bus_address(struct pci_dev *pdev, int bar) 582 { 583 584 return (pci_resource_start(pdev, bar)); 585 } 586 587 #define PCI_CAP_ID_EXP PCIY_EXPRESS 588 #define PCI_CAP_ID_PCIX PCIY_PCIX 589 #define PCI_CAP_ID_AGP PCIY_AGP 590 #define PCI_CAP_ID_PM PCIY_PMG 591 592 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 593 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 594 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 595 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 596 #define PCI_EXP_LNKSTA PCIER_LINK_STA 597 598 static inline int 599 pci_find_capability(struct pci_dev *pdev, int capid) 600 { 601 int reg; 602 603 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 604 return (0); 605 return (reg); 606 } 607 608 static inline int pci_pcie_cap(struct pci_dev *dev) 609 { 610 return pci_find_capability(dev, PCI_CAP_ID_EXP); 611 } 612 613 static inline int 614 pci_find_ext_capability(struct pci_dev *pdev, int capid) 615 { 616 int reg; 617 618 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 619 return (0); 620 return (reg); 621 } 622 623 #define PCIM_PCAP_PME_SHIFT 11 624 static __inline bool 625 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 626 { 627 struct pci_devinfo *dinfo; 628 pcicfgregs *cfg; 629 630 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 631 return (false); 632 633 dinfo = device_get_ivars(pdev->dev.bsddev); 634 cfg = &dinfo->cfg; 635 636 if (cfg->pp.pp_cap == 0) 637 return (false); 638 639 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 640 return (true); 641 642 return (false); 643 } 644 645 static inline int 646 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 647 { 648 649 if (!pci_enable_aspm) 650 return (-EPERM); 651 652 return (-ENXIO); 653 } 654 655 static inline int 656 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 657 { 658 659 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 660 return (0); 661 } 662 663 static inline int 664 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 665 { 666 667 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 668 return (0); 669 } 670 671 static inline int 672 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 673 { 674 675 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 676 return (0); 677 } 678 679 static inline int 680 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 681 { 682 683 pci_write_config(pdev->dev.bsddev, where, val, 1); 684 return (0); 685 } 686 687 static inline int 688 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 689 { 690 691 pci_write_config(pdev->dev.bsddev, where, val, 2); 692 return (0); 693 } 694 695 static inline int 696 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 697 { 698 699 pci_write_config(pdev->dev.bsddev, where, val, 4); 700 return (0); 701 } 702 703 int linux_pci_register_driver(struct pci_driver *pdrv); 704 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 705 void linux_pci_unregister_driver(struct pci_driver *pdrv); 706 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 707 708 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 709 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 710 711 struct msix_entry { 712 int entry; 713 int vector; 714 }; 715 716 /* 717 * Enable msix, positive errors indicate actual number of available 718 * vectors. Negative errors are failures. 719 * 720 * NB: define added to prevent this definition of pci_enable_msix from 721 * clashing with the native FreeBSD version. 722 */ 723 #define pci_enable_msix(...) \ 724 linux_pci_enable_msix(__VA_ARGS__) 725 726 static inline int 727 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 728 { 729 struct resource_list_entry *rle; 730 int error; 731 int avail; 732 int i; 733 734 avail = pci_msix_count(pdev->dev.bsddev); 735 if (avail < nreq) { 736 if (avail == 0) 737 return -EINVAL; 738 return avail; 739 } 740 avail = nreq; 741 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 742 return error; 743 /* 744 * Handle case where "pci_alloc_msix()" may allocate less 745 * interrupts than available and return with no error: 746 */ 747 if (avail < nreq) { 748 pci_release_msi(pdev->dev.bsddev); 749 return avail; 750 } 751 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 752 pdev->dev.irq_start = rle->start; 753 pdev->dev.irq_end = rle->start + avail; 754 for (i = 0; i < nreq; i++) 755 entries[i].vector = pdev->dev.irq_start + i; 756 pdev->msix_enabled = true; 757 return (0); 758 } 759 760 #define pci_enable_msix_range(...) \ 761 linux_pci_enable_msix_range(__VA_ARGS__) 762 763 static inline int 764 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 765 int minvec, int maxvec) 766 { 767 int nvec = maxvec; 768 int rc; 769 770 if (maxvec < minvec) 771 return (-ERANGE); 772 773 do { 774 rc = pci_enable_msix(dev, entries, nvec); 775 if (rc < 0) { 776 return (rc); 777 } else if (rc > 0) { 778 if (rc < minvec) 779 return (-ENOSPC); 780 nvec = rc; 781 } 782 } while (rc); 783 return (nvec); 784 } 785 786 #define pci_enable_msi(pdev) \ 787 linux_pci_enable_msi(pdev) 788 789 static inline int 790 pci_enable_msi(struct pci_dev *pdev) 791 { 792 struct resource_list_entry *rle; 793 int error; 794 int avail; 795 796 avail = pci_msi_count(pdev->dev.bsddev); 797 if (avail < 1) 798 return -EINVAL; 799 800 avail = 1; /* this function only enable one MSI IRQ */ 801 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 802 return error; 803 804 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 805 pdev->dev.irq_start = rle->start; 806 pdev->dev.irq_end = rle->start + avail; 807 pdev->irq = rle->start; 808 pdev->msi_enabled = true; 809 return (0); 810 } 811 812 static inline int 813 pci_channel_offline(struct pci_dev *pdev) 814 { 815 816 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 817 } 818 819 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 820 { 821 return -ENODEV; 822 } 823 static inline void pci_disable_sriov(struct pci_dev *dev) 824 { 825 } 826 827 static inline struct resource * 828 _lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size __unused) 829 { 830 struct pci_mmio_region *mmio, *p; 831 int type; 832 833 type = pci_resource_type(pdev, bar); 834 if (type < 0) { 835 device_printf(pdev->dev.bsddev, "%s: bar %d type %d\n", 836 __func__, bar, type); 837 return (NULL); 838 } 839 840 /* 841 * Check for duplicate mappings. 842 * This can happen if a driver calls pci_request_region() first. 843 */ 844 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 845 if (mmio->type == type && mmio->rid == PCIR_BAR(bar)) { 846 return (mmio->res); 847 } 848 } 849 850 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 851 mmio->rid = PCIR_BAR(bar); 852 mmio->type = type; 853 mmio->res = bus_alloc_resource_any(pdev->dev.bsddev, mmio->type, 854 &mmio->rid, RF_ACTIVE|RF_SHAREABLE); 855 if (mmio->res == NULL) { 856 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 857 "bar %d type %d rid %d\n", 858 __func__, bar, type, PCIR_BAR(bar)); 859 free(mmio, M_DEVBUF); 860 return (NULL); 861 } 862 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 863 864 return (mmio->res); 865 } 866 867 static inline void * 868 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 869 { 870 struct resource *res; 871 872 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 873 if (res == NULL) 874 return (NULL); 875 /* This is a FreeBSD extension so we can use bus_*(). */ 876 if (pdev->want_iomap_res) 877 return (res); 878 return ((void *)rman_get_bushandle(res)); 879 } 880 881 static inline void 882 pci_iounmap(struct pci_dev *pdev, void *res) 883 { 884 struct pci_mmio_region *mmio, *p; 885 886 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 887 if (res != (void *)rman_get_bushandle(mmio->res)) 888 continue; 889 bus_release_resource(pdev->dev.bsddev, 890 mmio->type, mmio->rid, mmio->res); 891 TAILQ_REMOVE(&pdev->mmio, mmio, next); 892 free(mmio, M_DEVBUF); 893 return; 894 } 895 } 896 897 static inline void 898 lkpi_pci_save_state(struct pci_dev *pdev) 899 { 900 901 pci_save_state(pdev->dev.bsddev); 902 } 903 904 static inline void 905 lkpi_pci_restore_state(struct pci_dev *pdev) 906 { 907 908 pci_restore_state(pdev->dev.bsddev); 909 } 910 911 #define pci_save_state(dev) lkpi_pci_save_state(dev) 912 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 913 914 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 915 const struct pci_device_id _table[] __devinitdata 916 917 /* XXX This should not be necessary. */ 918 #define pcix_set_mmrbc(d, v) 0 919 #define pcix_get_max_mmrbc(d) 0 920 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 921 922 #define PCI_DMA_BIDIRECTIONAL 0 923 #define PCI_DMA_TODEVICE 1 924 #define PCI_DMA_FROMDEVICE 2 925 #define PCI_DMA_NONE 3 926 927 #define pci_pool dma_pool 928 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 929 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 930 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 931 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 932 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 933 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 934 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 935 _size, _vaddr, _dma_handle) 936 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 937 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 938 _sg, _nents, (enum dma_data_direction)_dir) 939 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 940 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 941 (_ptr), (_size), (enum dma_data_direction)_dir) 942 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 943 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 944 _addr, _size, (enum dma_data_direction)_dir) 945 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 946 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 947 _sg, _nents, (enum dma_data_direction)_dir) 948 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 949 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 950 _offset, _size, (enum dma_data_direction)_dir) 951 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 952 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 953 _dma_address, _size, (enum dma_data_direction)_dir) 954 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 955 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 956 dma_mapping_error(&(_pdev)->dev, _dma_addr) 957 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 958 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 959 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 960 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 961 #define pci_unmap_addr dma_unmap_addr 962 #define pci_unmap_addr_set dma_unmap_addr_set 963 #define pci_unmap_len dma_unmap_len 964 #define pci_unmap_len_set dma_unmap_len_set 965 966 typedef unsigned int __bitwise pci_channel_state_t; 967 typedef unsigned int __bitwise pci_ers_result_t; 968 969 enum pci_channel_state { 970 pci_channel_io_normal = 1, 971 pci_channel_io_frozen = 2, 972 pci_channel_io_perm_failure = 3, 973 }; 974 975 enum pci_ers_result { 976 PCI_ERS_RESULT_NONE = 1, 977 PCI_ERS_RESULT_CAN_RECOVER = 2, 978 PCI_ERS_RESULT_NEED_RESET = 3, 979 PCI_ERS_RESULT_DISCONNECT = 4, 980 PCI_ERS_RESULT_RECOVERED = 5, 981 }; 982 983 /* PCI bus error event callbacks */ 984 struct pci_error_handlers { 985 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 986 enum pci_channel_state error); 987 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 988 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 989 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 990 void (*resume)(struct pci_dev *dev); 991 }; 992 993 /* FreeBSD does not support SRIOV - yet */ 994 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 995 { 996 return dev; 997 } 998 999 static inline bool pci_is_pcie(struct pci_dev *dev) 1000 { 1001 return !!pci_pcie_cap(dev); 1002 } 1003 1004 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1005 { 1006 int pos; 1007 u16 reg16; 1008 1009 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1010 if (!pos) 1011 return 0; 1012 1013 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1014 1015 return reg16; 1016 } 1017 1018 static inline int pci_pcie_type(struct pci_dev *dev) 1019 { 1020 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1021 } 1022 1023 static inline int pcie_cap_version(struct pci_dev *dev) 1024 { 1025 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1026 } 1027 1028 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1029 { 1030 int type = pci_pcie_type(dev); 1031 1032 return pcie_cap_version(dev) > 1 || 1033 type == PCI_EXP_TYPE_ROOT_PORT || 1034 type == PCI_EXP_TYPE_ENDPOINT || 1035 type == PCI_EXP_TYPE_LEG_END; 1036 } 1037 1038 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1039 { 1040 return true; 1041 } 1042 1043 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1044 { 1045 int type = pci_pcie_type(dev); 1046 1047 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1048 (type == PCI_EXP_TYPE_DOWNSTREAM && 1049 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1050 } 1051 1052 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1053 { 1054 int type = pci_pcie_type(dev); 1055 1056 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1057 type == PCI_EXP_TYPE_RC_EC; 1058 } 1059 1060 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1061 { 1062 if (!pci_is_pcie(dev)) 1063 return false; 1064 1065 switch (pos) { 1066 case PCI_EXP_FLAGS_TYPE: 1067 return true; 1068 case PCI_EXP_DEVCAP: 1069 case PCI_EXP_DEVCTL: 1070 case PCI_EXP_DEVSTA: 1071 return pcie_cap_has_devctl(dev); 1072 case PCI_EXP_LNKCAP: 1073 case PCI_EXP_LNKCTL: 1074 case PCI_EXP_LNKSTA: 1075 return pcie_cap_has_lnkctl(dev); 1076 case PCI_EXP_SLTCAP: 1077 case PCI_EXP_SLTCTL: 1078 case PCI_EXP_SLTSTA: 1079 return pcie_cap_has_sltctl(dev); 1080 case PCI_EXP_RTCTL: 1081 case PCI_EXP_RTCAP: 1082 case PCI_EXP_RTSTA: 1083 return pcie_cap_has_rtctl(dev); 1084 case PCI_EXP_DEVCAP2: 1085 case PCI_EXP_DEVCTL2: 1086 case PCI_EXP_LNKCAP2: 1087 case PCI_EXP_LNKCTL2: 1088 case PCI_EXP_LNKSTA2: 1089 return pcie_cap_version(dev) > 1; 1090 default: 1091 return false; 1092 } 1093 } 1094 1095 static inline int 1096 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1097 { 1098 if (pos & 3) 1099 return -EINVAL; 1100 1101 if (!pcie_capability_reg_implemented(dev, pos)) 1102 return -EINVAL; 1103 1104 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1105 } 1106 1107 static inline int 1108 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1109 { 1110 if (pos & 3) 1111 return -EINVAL; 1112 1113 if (!pcie_capability_reg_implemented(dev, pos)) 1114 return -EINVAL; 1115 1116 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1117 } 1118 1119 static inline int 1120 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1121 { 1122 if (pos & 1) 1123 return -EINVAL; 1124 1125 if (!pcie_capability_reg_implemented(dev, pos)) 1126 return 0; 1127 1128 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1129 } 1130 1131 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1132 enum pci_bus_speed *speed, enum pcie_link_width *width) 1133 { 1134 *speed = PCI_SPEED_UNKNOWN; 1135 *width = PCIE_LNK_WIDTH_UNKNOWN; 1136 return (0); 1137 } 1138 1139 static inline int 1140 pci_num_vf(struct pci_dev *dev) 1141 { 1142 return (0); 1143 } 1144 1145 static inline enum pci_bus_speed 1146 pcie_get_speed_cap(struct pci_dev *dev) 1147 { 1148 device_t root; 1149 uint32_t lnkcap, lnkcap2; 1150 int error, pos; 1151 1152 root = device_get_parent(dev->dev.bsddev); 1153 if (root == NULL) 1154 return (PCI_SPEED_UNKNOWN); 1155 root = device_get_parent(root); 1156 if (root == NULL) 1157 return (PCI_SPEED_UNKNOWN); 1158 root = device_get_parent(root); 1159 if (root == NULL) 1160 return (PCI_SPEED_UNKNOWN); 1161 1162 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1163 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1164 return (PCI_SPEED_UNKNOWN); 1165 1166 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1167 return (PCI_SPEED_UNKNOWN); 1168 1169 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1170 1171 if (lnkcap2) { /* PCIe r3.0-compliant */ 1172 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1173 return (PCIE_SPEED_2_5GT); 1174 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1175 return (PCIE_SPEED_5_0GT); 1176 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1177 return (PCIE_SPEED_8_0GT); 1178 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1179 return (PCIE_SPEED_16_0GT); 1180 } else { /* pre-r3.0 */ 1181 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1182 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1183 return (PCIE_SPEED_2_5GT); 1184 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1185 return (PCIE_SPEED_5_0GT); 1186 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1187 return (PCIE_SPEED_8_0GT); 1188 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1189 return (PCIE_SPEED_16_0GT); 1190 } 1191 return (PCI_SPEED_UNKNOWN); 1192 } 1193 1194 static inline enum pcie_link_width 1195 pcie_get_width_cap(struct pci_dev *dev) 1196 { 1197 uint32_t lnkcap; 1198 1199 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1200 if (lnkcap) 1201 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1202 1203 return (PCIE_LNK_WIDTH_UNKNOWN); 1204 } 1205 1206 static inline int 1207 pcie_get_mps(struct pci_dev *dev) 1208 { 1209 return (pci_get_max_payload(dev->dev.bsddev)); 1210 } 1211 1212 static inline uint32_t 1213 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1214 { 1215 1216 switch(spd) { 1217 case PCIE_SPEED_16_0GT: 1218 return (16000 * 128 / 130); 1219 case PCIE_SPEED_8_0GT: 1220 return (8000 * 128 / 130); 1221 case PCIE_SPEED_5_0GT: 1222 return (5000 * 8 / 10); 1223 case PCIE_SPEED_2_5GT: 1224 return (2500 * 8 / 10); 1225 default: 1226 return (0); 1227 } 1228 } 1229 1230 static inline uint32_t 1231 pcie_bandwidth_available(struct pci_dev *pdev, 1232 struct pci_dev **limiting, 1233 enum pci_bus_speed *speed, 1234 enum pcie_link_width *width) 1235 { 1236 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1237 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1238 1239 if (speed) 1240 *speed = nspeed; 1241 if (width) 1242 *width = nwidth; 1243 1244 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1245 } 1246 1247 static inline struct pci_dev * 1248 pcie_find_root_port(struct pci_dev *pdev) 1249 { 1250 device_t root; 1251 1252 if (pdev->root != NULL) 1253 return (pdev->root); 1254 1255 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1256 if (root == NULL) 1257 return (NULL); 1258 1259 pdev->root = lkpinew_pci_dev(root); 1260 return (pdev->root); 1261 } 1262 1263 /* This is needed when people rip out the device "HotPlug". */ 1264 static inline void 1265 pci_lock_rescan_remove(void) 1266 { 1267 } 1268 1269 static inline void 1270 pci_unlock_rescan_remove(void) 1271 { 1272 } 1273 1274 static __inline void 1275 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1276 { 1277 } 1278 1279 /* 1280 * The following functions can be used to attach/detach the LinuxKPI's 1281 * PCI device runtime. The pci_driver and pci_device_id pointer is 1282 * allowed to be NULL. Other pointers must be all valid. 1283 * The pci_dev structure should be zero-initialized before passed 1284 * to the linux_pci_attach_device function. 1285 */ 1286 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1287 const struct pci_device_id *, struct pci_dev *); 1288 extern int linux_pci_detach_device(struct pci_dev *); 1289 1290 static inline int 1291 pci_dev_present(const struct pci_device_id *cur) 1292 { 1293 while (cur != NULL && (cur->vendor || cur->device)) { 1294 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1295 return (1); 1296 } 1297 cur++; 1298 } 1299 return (0); 1300 } 1301 1302 static inline bool 1303 pci_is_root_bus(struct pci_bus *pbus) 1304 { 1305 1306 return (pbus->self == NULL); 1307 } 1308 1309 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1310 unsigned int bus, unsigned int devfn); 1311 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1312 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1313 1314 static inline int 1315 pci_domain_nr(struct pci_bus *pbus) 1316 { 1317 1318 return (pbus->domain); 1319 } 1320 1321 static inline int 1322 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1323 int pos, uint32_t *val, int len) 1324 { 1325 1326 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1327 return (0); 1328 } 1329 1330 static inline int 1331 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1332 { 1333 uint32_t tmp; 1334 int ret; 1335 1336 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1337 *val = (u16)tmp; 1338 return (ret); 1339 } 1340 1341 static inline int 1342 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1343 { 1344 uint32_t tmp; 1345 int ret; 1346 1347 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1348 *val = (u8)tmp; 1349 return (ret); 1350 } 1351 1352 static inline int 1353 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1354 uint32_t val, int size) 1355 { 1356 1357 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1358 return (0); 1359 } 1360 1361 static inline int 1362 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1363 uint8_t val) 1364 { 1365 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1366 } 1367 1368 static inline int 1369 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1370 uint16_t val) 1371 { 1372 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1373 } 1374 1375 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1376 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1377 1378 /* -------------------------------------------------------------------------- */ 1379 1380 static inline int 1381 pcim_enable_device(struct pci_dev *pdev) 1382 { 1383 struct pci_devres *dr; 1384 int error; 1385 1386 /* Here we cannot run through the pdev->managed check. */ 1387 dr = lkpi_pci_devres_get_alloc(pdev); 1388 if (dr == NULL) 1389 return (-ENOMEM); 1390 1391 /* If resources were enabled before do not do it again. */ 1392 if (dr->enable_io) 1393 return (0); 1394 1395 error = pci_enable_device(pdev); 1396 if (error == 0) 1397 dr->enable_io = true; 1398 1399 /* This device is not managed. */ 1400 pdev->managed = true; 1401 1402 return (error); 1403 } 1404 1405 static inline struct pcim_iomap_devres * 1406 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev) 1407 { 1408 struct pcim_iomap_devres *dr; 1409 1410 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release, 1411 NULL, NULL); 1412 if (dr == NULL) { 1413 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release, 1414 sizeof(*dr), GFP_KERNEL | __GFP_ZERO); 1415 if (dr != NULL) 1416 lkpi_devres_add(&pdev->dev, dr); 1417 } 1418 1419 if (dr == NULL) 1420 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__); 1421 1422 return (dr); 1423 } 1424 1425 static inline void __iomem ** 1426 pcim_iomap_table(struct pci_dev *pdev) 1427 { 1428 struct pcim_iomap_devres *dr; 1429 1430 dr = lkpi_pcim_iomap_devres_find(pdev); 1431 if (dr == NULL) 1432 return (NULL); 1433 1434 /* 1435 * If the driver has manually set a flag to be able to request the 1436 * resource to use bus_read/write_<n>, return the shadow table. 1437 */ 1438 if (pdev->want_iomap_res) 1439 return ((void **)dr->res_table); 1440 1441 /* This is the Linux default. */ 1442 return (dr->mmio_table); 1443 } 1444 1445 static inline int 1446 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1447 { 1448 struct pcim_iomap_devres *dr; 1449 void *res; 1450 uint32_t mappings, requests, req_mask; 1451 int bar, error; 1452 1453 dr = lkpi_pcim_iomap_devres_find(pdev); 1454 if (dr == NULL) 1455 return (-ENOMEM); 1456 1457 /* Request all the BARs ("regions") we do not iomap. */ 1458 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1459 for (bar = requests = 0; requests != req_mask; bar++) { 1460 if ((req_mask & (1 << bar)) == 0) 1461 continue; 1462 error = pci_request_region(pdev, bar, name); 1463 if (error != 0 && error != -ENODEV) 1464 goto err; 1465 requests |= (1 << bar); 1466 } 1467 1468 /* Now iomap all the requested (by "mask") ones. */ 1469 for (bar = mappings = 0; mappings != mask; bar++) { 1470 if ((mask & (1 << bar)) == 0) 1471 continue; 1472 1473 /* Request double is not allowed. */ 1474 if (dr->mmio_table[bar] != NULL) { 1475 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1476 __func__, bar, dr->mmio_table[bar]); 1477 goto err; 1478 } 1479 1480 res = _lkpi_pci_iomap(pdev, bar, 0); 1481 if (res == NULL) 1482 goto err; 1483 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1484 dr->res_table[bar] = res; 1485 1486 mappings |= (1 << bar); 1487 } 1488 1489 return (0); 1490 1491 err: 1492 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1493 if ((mappings & (1 << bar)) != 0) { 1494 res = dr->mmio_table[bar]; 1495 if (res == NULL) 1496 continue; 1497 pci_iounmap(pdev, res); 1498 } else if ((requests & (1 << bar)) != 0) { 1499 pci_release_region(pdev, bar); 1500 } 1501 } 1502 1503 return (-EINVAL); 1504 } 1505 1506 /* This is a FreeBSD extension so we can use bus_*(). */ 1507 static inline void 1508 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1509 { 1510 pdev->want_iomap_res = true; 1511 } 1512 1513 #endif /* _LINUX_PCI_H_ */ 1514