1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/nv.h> 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 74 #define MODULE_DEVICE_TABLE(_bus, _table) \ 75 \ 76 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 77 DEVMETHOD_END \ 78 }; \ 79 \ 80 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 81 "lkpi_" #_bus #_table, \ 82 _ ## _bus ## _ ## _table ## _methods, \ 83 0 \ 84 }; \ 85 \ 86 static devclass_t _ ## _bus ## _ ## _table ## _devclass; \ 87 \ 88 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 89 _ ## _bus ## _ ## _table ## _devclass, 0, 0); \ 90 \ 91 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 92 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 93 94 #define PCI_ANY_ID -1U 95 96 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 97 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 98 #define PCI_FUNC(devfn) ((devfn) & 0x07) 99 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 100 101 #define PCI_VDEVICE(_vendor, _device) \ 102 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 103 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 104 #define PCI_DEVICE(_vendor, _device) \ 105 .vendor = (_vendor), .device = (_device), \ 106 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 107 108 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 109 110 #define PCI_VENDOR_ID PCIR_DEVVENDOR 111 #define PCI_COMMAND PCIR_COMMAND 112 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 115 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 116 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 117 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 118 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 119 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 120 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 121 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 122 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 123 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 124 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 125 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 126 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 127 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 128 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 129 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 130 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 131 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 132 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 133 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 134 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 135 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 136 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 137 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 138 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 139 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 140 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 141 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 142 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 143 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 144 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 145 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 146 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 147 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 148 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 149 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 150 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 151 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 152 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 153 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 154 #define PCI_EXP_LNKCTL2_TLS 0x000f 155 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 156 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 157 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 158 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 159 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 160 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 161 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 162 163 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 164 #define PCI_EXP_DEVSTA_TRPND 0x0020 165 166 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 167 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 168 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 169 170 enum pci_bus_speed { 171 PCI_SPEED_UNKNOWN = -1, 172 PCIE_SPEED_2_5GT, 173 PCIE_SPEED_5_0GT, 174 PCIE_SPEED_8_0GT, 175 PCIE_SPEED_16_0GT, 176 }; 177 178 enum pcie_link_width { 179 PCIE_LNK_WIDTH_RESRV = 0x00, 180 PCIE_LNK_X1 = 0x01, 181 PCIE_LNK_X2 = 0x02, 182 PCIE_LNK_X4 = 0x04, 183 PCIE_LNK_X8 = 0x08, 184 PCIE_LNK_X12 = 0x0c, 185 PCIE_LNK_X16 = 0x10, 186 PCIE_LNK_X32 = 0x20, 187 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 188 }; 189 190 #define PCIE_LINK_STATE_L0S 0x00000001 191 #define PCIE_LINK_STATE_L1 0x00000002 192 #define PCIE_LINK_STATE_CLKPM 0x00000004 193 194 typedef int pci_power_t; 195 196 #define PCI_D0 PCI_POWERSTATE_D0 197 #define PCI_D1 PCI_POWERSTATE_D1 198 #define PCI_D2 PCI_POWERSTATE_D2 199 #define PCI_D3hot PCI_POWERSTATE_D3 200 #define PCI_D3cold 4 201 202 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 203 204 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 205 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 206 207 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 208 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 209 210 #define PCI_L1SS_CTL1 0x8 211 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 212 213 #define PCI_IRQ_LEGACY 0x01 214 #define PCI_IRQ_MSI 0x02 215 #define PCI_IRQ_MSIX 0x04 216 217 struct pci_dev; 218 219 struct pci_driver { 220 struct list_head node; 221 char *name; 222 const struct pci_device_id *id_table; 223 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 224 void (*remove)(struct pci_dev *dev); 225 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 226 int (*resume) (struct pci_dev *dev); /* Device woken up */ 227 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 228 driver_t bsddriver; 229 devclass_t bsdclass; 230 struct device_driver driver; 231 const struct pci_error_handlers *err_handler; 232 bool isdrm; 233 int bsd_probe_return; 234 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 235 const nvlist_t *pf_config); 236 void (*bsd_iov_uninit)(device_t dev); 237 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 238 const nvlist_t *vf_config); 239 }; 240 241 struct pci_bus { 242 struct pci_dev *self; 243 int domain; 244 int number; 245 }; 246 247 extern struct list_head pci_drivers; 248 extern struct list_head pci_devices; 249 extern spinlock_t pci_lock; 250 251 #define __devexit_p(x) x 252 253 #define module_pci_driver(_driver) \ 254 \ 255 static inline int \ 256 _pci_init(void) \ 257 { \ 258 \ 259 return (linux_pci_register_driver(&_driver)); \ 260 } \ 261 \ 262 static inline void \ 263 _pci_exit(void) \ 264 { \ 265 \ 266 linux_pci_unregister_driver(&_driver); \ 267 } \ 268 \ 269 module_init(_pci_init); \ 270 module_exit(_pci_exit) 271 272 /* 273 * If we find drivers accessing this from multiple KPIs we may have to 274 * refcount objects of this structure. 275 */ 276 struct pci_mmio_region { 277 TAILQ_ENTRY(pci_mmio_region) next; 278 struct resource *res; 279 int rid; 280 int type; 281 }; 282 283 struct pci_dev { 284 struct device dev; 285 struct list_head links; 286 struct pci_driver *pdrv; 287 struct pci_bus *bus; 288 struct pci_dev *root; 289 uint16_t device; 290 uint16_t vendor; 291 uint16_t subsystem_vendor; 292 uint16_t subsystem_device; 293 unsigned int irq; 294 unsigned int devfn; 295 uint32_t class; 296 uint8_t revision; 297 bool managed; /* devres "pcim_*(). */ 298 bool want_iomap_res; 299 bool msi_enabled; 300 bool msix_enabled; 301 phys_addr_t rom; 302 size_t romlen; 303 304 TAILQ_HEAD(, pci_mmio_region) mmio; 305 }; 306 307 /* We need some meta-struct to keep track of these for devres. */ 308 struct pci_devres { 309 bool enable_io; 310 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 311 uint8_t region_mask; 312 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 313 }; 314 struct pcim_iomap_devres { 315 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 316 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 317 }; 318 319 /* Internal helper function(s). */ 320 struct pci_dev *lkpinew_pci_dev(device_t); 321 void lkpi_pci_devres_release(struct device *, void *); 322 void lkpi_pcim_iomap_table_release(struct device *, void *); 323 324 static inline int 325 pci_resource_type(struct pci_dev *pdev, int bar) 326 { 327 struct pci_map *pm; 328 329 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 330 if (!pm) 331 return (-1); 332 333 if (PCI_BAR_IO(pm->pm_value)) 334 return (SYS_RES_IOPORT); 335 else 336 return (SYS_RES_MEMORY); 337 } 338 339 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 340 struct resource_list *rl, int type, int rid); 341 342 static inline struct resource_list_entry * 343 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 344 { 345 struct pci_devinfo *dinfo; 346 struct resource_list *rl; 347 struct resource_list_entry *rle; 348 349 dinfo = device_get_ivars(pdev->dev.bsddev); 350 rl = &dinfo->resources; 351 rle = resource_list_find(rl, type, rid); 352 /* Reserve resources for this BAR if needed. */ 353 if (rle == NULL && reserve_bar) 354 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 355 return (rle); 356 } 357 358 static inline struct resource_list_entry * 359 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 360 { 361 int type; 362 363 type = pci_resource_type(pdev, bar); 364 if (type < 0) 365 return (NULL); 366 bar = PCIR_BAR(bar); 367 return (linux_pci_get_rle(pdev, type, bar, reserve)); 368 } 369 370 static inline struct device * 371 linux_pci_find_irq_dev(unsigned int irq) 372 { 373 struct pci_dev *pdev; 374 struct device *found; 375 376 found = NULL; 377 spin_lock(&pci_lock); 378 list_for_each_entry(pdev, &pci_devices, links) { 379 if (irq == pdev->dev.irq || 380 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 381 found = &pdev->dev; 382 break; 383 } 384 } 385 spin_unlock(&pci_lock); 386 return (found); 387 } 388 389 /* 390 * All drivers just seem to want to inspect the type not flags. 391 */ 392 static inline int 393 pci_resource_flags(struct pci_dev *pdev, int bar) 394 { 395 int type; 396 397 type = pci_resource_type(pdev, bar); 398 if (type < 0) 399 return (0); 400 return (1 << type); 401 } 402 403 static inline const char * 404 pci_name(struct pci_dev *d) 405 { 406 407 return device_get_desc(d->dev.bsddev); 408 } 409 410 static inline void * 411 pci_get_drvdata(struct pci_dev *pdev) 412 { 413 414 return dev_get_drvdata(&pdev->dev); 415 } 416 417 static inline void 418 pci_set_drvdata(struct pci_dev *pdev, void *data) 419 { 420 421 dev_set_drvdata(&pdev->dev, data); 422 } 423 424 static inline struct pci_dev * 425 pci_dev_get(struct pci_dev *pdev) 426 { 427 428 if (pdev != NULL) 429 get_device(&pdev->dev); 430 return (pdev); 431 } 432 433 static __inline void 434 pci_dev_put(struct pci_dev *pdev) 435 { 436 437 if (pdev != NULL) 438 put_device(&pdev->dev); 439 } 440 441 static inline int 442 pci_enable_device(struct pci_dev *pdev) 443 { 444 445 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 446 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 447 return (0); 448 } 449 450 static inline void 451 pci_disable_device(struct pci_dev *pdev) 452 { 453 454 pci_disable_busmaster(pdev->dev.bsddev); 455 } 456 457 static inline int 458 pci_set_master(struct pci_dev *pdev) 459 { 460 461 pci_enable_busmaster(pdev->dev.bsddev); 462 return (0); 463 } 464 465 static inline int 466 pci_set_power_state(struct pci_dev *pdev, int state) 467 { 468 469 pci_set_powerstate(pdev->dev.bsddev, state); 470 return (0); 471 } 472 473 static inline int 474 pci_clear_master(struct pci_dev *pdev) 475 { 476 477 pci_disable_busmaster(pdev->dev.bsddev); 478 return (0); 479 } 480 481 static inline struct pci_devres * 482 lkpi_pci_devres_get_alloc(struct pci_dev *pdev) 483 { 484 struct pci_devres *dr; 485 486 dr = lkpi_devres_find(&pdev->dev, lkpi_pci_devres_release, NULL, NULL); 487 if (dr == NULL) { 488 dr = lkpi_devres_alloc(lkpi_pci_devres_release, sizeof(*dr), 489 GFP_KERNEL | __GFP_ZERO); 490 if (dr != NULL) 491 lkpi_devres_add(&pdev->dev, dr); 492 } 493 494 return (dr); 495 } 496 static inline struct pci_devres * 497 lkpi_pci_devres_find(struct pci_dev *pdev) 498 { 499 500 if (!pdev->managed) 501 return (NULL); 502 503 return (lkpi_pci_devres_get_alloc(pdev)); 504 } 505 506 static inline int 507 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 508 { 509 struct resource *res; 510 struct pci_devres *dr; 511 struct pci_mmio_region *mmio; 512 int rid; 513 int type; 514 515 type = pci_resource_type(pdev, bar); 516 if (type < 0) 517 return (-ENODEV); 518 rid = PCIR_BAR(bar); 519 res = bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 520 RF_ACTIVE|RF_SHAREABLE); 521 if (res == NULL) { 522 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 523 "bar %d type %d rid %d\n", 524 __func__, bar, type, PCIR_BAR(bar)); 525 return (-ENODEV); 526 } 527 528 /* 529 * It seems there is an implicit devres tracking on these if the device 530 * is managed; otherwise the resources are not automatiaclly freed on 531 * FreeBSD/LinuxKPI tough they should be/are expected to be by Linux 532 * drivers. 533 */ 534 dr = lkpi_pci_devres_find(pdev); 535 if (dr != NULL) { 536 dr->region_mask |= (1 << bar); 537 dr->region_table[bar] = res; 538 } 539 540 /* Even if the device is not managed we need to track it for iomap. */ 541 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 542 mmio->rid = PCIR_BAR(bar); 543 mmio->type = type; 544 mmio->res = res; 545 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 546 547 return (0); 548 } 549 550 static inline void 551 pci_release_region(struct pci_dev *pdev, int bar) 552 { 553 struct resource_list_entry *rle; 554 struct pci_devres *dr; 555 struct pci_mmio_region *mmio, *p; 556 557 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 558 return; 559 560 /* 561 * As we implicitly track the requests we also need to clear them on 562 * release. Do clear before resource release. 563 */ 564 dr = lkpi_pci_devres_find(pdev); 565 if (dr != NULL) { 566 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 567 " region_table res %p != rel->res %p\n", __func__, pdev, 568 bar, dr->region_table[bar], rle->res)); 569 dr->region_table[bar] = NULL; 570 dr->region_mask &= ~(1 << bar); 571 } 572 573 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 574 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 575 continue; 576 TAILQ_REMOVE(&pdev->mmio, mmio, next); 577 free(mmio, M_DEVBUF); 578 } 579 580 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 581 } 582 583 static inline void 584 pci_release_regions(struct pci_dev *pdev) 585 { 586 int i; 587 588 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 589 pci_release_region(pdev, i); 590 } 591 592 static inline int 593 pci_request_regions(struct pci_dev *pdev, const char *res_name) 594 { 595 int error; 596 int i; 597 598 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 599 error = pci_request_region(pdev, i, res_name); 600 if (error && error != -ENODEV) { 601 pci_release_regions(pdev); 602 return (error); 603 } 604 } 605 return (0); 606 } 607 608 static inline void 609 lkpi_pci_disable_msix(struct pci_dev *pdev) 610 { 611 612 pci_release_msi(pdev->dev.bsddev); 613 614 /* 615 * The MSIX IRQ numbers associated with this PCI device are no 616 * longer valid and might be re-assigned. Make sure 617 * linux_pci_find_irq_dev() does no longer see them by 618 * resetting their references to zero: 619 */ 620 pdev->dev.irq_start = 0; 621 pdev->dev.irq_end = 0; 622 pdev->msix_enabled = false; 623 } 624 /* Only for consistency. No conflict on that one. */ 625 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 626 627 static inline void 628 lkpi_pci_disable_msi(struct pci_dev *pdev) 629 { 630 631 pci_release_msi(pdev->dev.bsddev); 632 633 pdev->dev.irq_start = 0; 634 pdev->dev.irq_end = 0; 635 pdev->irq = pdev->dev.irq; 636 pdev->msi_enabled = false; 637 } 638 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 639 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 640 641 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 642 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 643 644 static inline bus_addr_t 645 pci_bus_address(struct pci_dev *pdev, int bar) 646 { 647 648 return (pci_resource_start(pdev, bar)); 649 } 650 651 #define PCI_CAP_ID_EXP PCIY_EXPRESS 652 #define PCI_CAP_ID_PCIX PCIY_PCIX 653 #define PCI_CAP_ID_AGP PCIY_AGP 654 #define PCI_CAP_ID_PM PCIY_PMG 655 656 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 657 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 658 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 659 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 660 #define PCI_EXP_LNKSTA PCIER_LINK_STA 661 662 static inline int 663 pci_find_capability(struct pci_dev *pdev, int capid) 664 { 665 int reg; 666 667 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 668 return (0); 669 return (reg); 670 } 671 672 static inline int pci_pcie_cap(struct pci_dev *dev) 673 { 674 return pci_find_capability(dev, PCI_CAP_ID_EXP); 675 } 676 677 static inline int 678 pci_find_ext_capability(struct pci_dev *pdev, int capid) 679 { 680 int reg; 681 682 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 683 return (0); 684 return (reg); 685 } 686 687 #define PCIM_PCAP_PME_SHIFT 11 688 static __inline bool 689 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 690 { 691 struct pci_devinfo *dinfo; 692 pcicfgregs *cfg; 693 694 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 695 return (false); 696 697 dinfo = device_get_ivars(pdev->dev.bsddev); 698 cfg = &dinfo->cfg; 699 700 if (cfg->pp.pp_cap == 0) 701 return (false); 702 703 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 704 return (true); 705 706 return (false); 707 } 708 709 static inline int 710 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 711 { 712 713 if (!pci_enable_aspm) 714 return (-EPERM); 715 716 return (-ENXIO); 717 } 718 719 static inline int 720 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 721 { 722 723 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 724 return (0); 725 } 726 727 static inline int 728 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 729 { 730 731 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 732 return (0); 733 } 734 735 static inline int 736 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 737 { 738 739 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 740 return (0); 741 } 742 743 static inline int 744 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 745 { 746 747 pci_write_config(pdev->dev.bsddev, where, val, 1); 748 return (0); 749 } 750 751 static inline int 752 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 753 { 754 755 pci_write_config(pdev->dev.bsddev, where, val, 2); 756 return (0); 757 } 758 759 static inline int 760 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 761 { 762 763 pci_write_config(pdev->dev.bsddev, where, val, 4); 764 return (0); 765 } 766 767 int linux_pci_register_driver(struct pci_driver *pdrv); 768 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 769 void linux_pci_unregister_driver(struct pci_driver *pdrv); 770 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 771 772 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 773 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 774 775 struct msix_entry { 776 int entry; 777 int vector; 778 }; 779 780 /* 781 * Enable msix, positive errors indicate actual number of available 782 * vectors. Negative errors are failures. 783 * 784 * NB: define added to prevent this definition of pci_enable_msix from 785 * clashing with the native FreeBSD version. 786 */ 787 #define pci_enable_msix(...) \ 788 linux_pci_enable_msix(__VA_ARGS__) 789 790 static inline int 791 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 792 { 793 struct resource_list_entry *rle; 794 int error; 795 int avail; 796 int i; 797 798 avail = pci_msix_count(pdev->dev.bsddev); 799 if (avail < nreq) { 800 if (avail == 0) 801 return -EINVAL; 802 return avail; 803 } 804 avail = nreq; 805 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 806 return error; 807 /* 808 * Handle case where "pci_alloc_msix()" may allocate less 809 * interrupts than available and return with no error: 810 */ 811 if (avail < nreq) { 812 pci_release_msi(pdev->dev.bsddev); 813 return avail; 814 } 815 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 816 pdev->dev.irq_start = rle->start; 817 pdev->dev.irq_end = rle->start + avail; 818 for (i = 0; i < nreq; i++) 819 entries[i].vector = pdev->dev.irq_start + i; 820 pdev->msix_enabled = true; 821 return (0); 822 } 823 824 #define pci_enable_msix_range(...) \ 825 linux_pci_enable_msix_range(__VA_ARGS__) 826 827 static inline int 828 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 829 int minvec, int maxvec) 830 { 831 int nvec = maxvec; 832 int rc; 833 834 if (maxvec < minvec) 835 return (-ERANGE); 836 837 do { 838 rc = pci_enable_msix(dev, entries, nvec); 839 if (rc < 0) { 840 return (rc); 841 } else if (rc > 0) { 842 if (rc < minvec) 843 return (-ENOSPC); 844 nvec = rc; 845 } 846 } while (rc); 847 return (nvec); 848 } 849 850 #define pci_enable_msi(pdev) \ 851 linux_pci_enable_msi(pdev) 852 853 static inline int 854 pci_enable_msi(struct pci_dev *pdev) 855 { 856 struct resource_list_entry *rle; 857 int error; 858 int avail; 859 860 avail = pci_msi_count(pdev->dev.bsddev); 861 if (avail < 1) 862 return -EINVAL; 863 864 avail = 1; /* this function only enable one MSI IRQ */ 865 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 866 return error; 867 868 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 869 pdev->dev.irq_start = rle->start; 870 pdev->dev.irq_end = rle->start + avail; 871 pdev->irq = rle->start; 872 pdev->msi_enabled = true; 873 return (0); 874 } 875 876 static inline int 877 pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 878 unsigned int flags) 879 { 880 int error; 881 882 if (flags & PCI_IRQ_MSIX) { 883 struct msix_entry *entries; 884 int i; 885 886 entries = kcalloc(maxv, sizeof(*entries), GFP_KERNEL); 887 if (entries == NULL) { 888 error = -ENOMEM; 889 goto out; 890 } 891 for (i = 0; i < maxv; ++i) 892 entries[i].entry = i; 893 error = pci_enable_msix(pdev, entries, maxv); 894 out: 895 kfree(entries); 896 if (error == 0 && pdev->msix_enabled) 897 return (pdev->dev.irq_end - pdev->dev.irq_start); 898 } 899 if (flags & PCI_IRQ_MSI) { 900 error = pci_enable_msi(pdev); 901 if (error == 0 && pdev->msi_enabled) 902 return (pdev->dev.irq_end - pdev->dev.irq_start); 903 } 904 if (flags & PCI_IRQ_LEGACY) { 905 if (pdev->irq) 906 return (1); 907 } 908 909 return (-EINVAL); 910 } 911 912 static inline int 913 pci_channel_offline(struct pci_dev *pdev) 914 { 915 916 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 917 } 918 919 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 920 { 921 return -ENODEV; 922 } 923 static inline void pci_disable_sriov(struct pci_dev *dev) 924 { 925 } 926 927 static inline struct resource * 928 _lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size __unused) 929 { 930 struct pci_mmio_region *mmio, *p; 931 int type; 932 933 type = pci_resource_type(pdev, bar); 934 if (type < 0) { 935 device_printf(pdev->dev.bsddev, "%s: bar %d type %d\n", 936 __func__, bar, type); 937 return (NULL); 938 } 939 940 /* 941 * Check for duplicate mappings. 942 * This can happen if a driver calls pci_request_region() first. 943 */ 944 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 945 if (mmio->type == type && mmio->rid == PCIR_BAR(bar)) { 946 return (mmio->res); 947 } 948 } 949 950 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 951 mmio->rid = PCIR_BAR(bar); 952 mmio->type = type; 953 mmio->res = bus_alloc_resource_any(pdev->dev.bsddev, mmio->type, 954 &mmio->rid, RF_ACTIVE|RF_SHAREABLE); 955 if (mmio->res == NULL) { 956 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 957 "bar %d type %d rid %d\n", 958 __func__, bar, type, PCIR_BAR(bar)); 959 free(mmio, M_DEVBUF); 960 return (NULL); 961 } 962 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 963 964 return (mmio->res); 965 } 966 967 static inline void * 968 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 969 { 970 struct resource *res; 971 972 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 973 if (res == NULL) 974 return (NULL); 975 /* This is a FreeBSD extension so we can use bus_*(). */ 976 if (pdev->want_iomap_res) 977 return (res); 978 return ((void *)rman_get_bushandle(res)); 979 } 980 981 static inline void 982 pci_iounmap(struct pci_dev *pdev, void *res) 983 { 984 struct pci_mmio_region *mmio, *p; 985 986 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 987 if (res != (void *)rman_get_bushandle(mmio->res)) 988 continue; 989 bus_release_resource(pdev->dev.bsddev, 990 mmio->type, mmio->rid, mmio->res); 991 TAILQ_REMOVE(&pdev->mmio, mmio, next); 992 free(mmio, M_DEVBUF); 993 return; 994 } 995 } 996 997 static inline void 998 lkpi_pci_save_state(struct pci_dev *pdev) 999 { 1000 1001 pci_save_state(pdev->dev.bsddev); 1002 } 1003 1004 static inline void 1005 lkpi_pci_restore_state(struct pci_dev *pdev) 1006 { 1007 1008 pci_restore_state(pdev->dev.bsddev); 1009 } 1010 1011 #define pci_save_state(dev) lkpi_pci_save_state(dev) 1012 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 1013 1014 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 1015 const struct pci_device_id _table[] __devinitdata 1016 1017 /* XXX This should not be necessary. */ 1018 #define pcix_set_mmrbc(d, v) 0 1019 #define pcix_get_max_mmrbc(d) 0 1020 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 1021 1022 #define PCI_DMA_BIDIRECTIONAL 0 1023 #define PCI_DMA_TODEVICE 1 1024 #define PCI_DMA_FROMDEVICE 2 1025 #define PCI_DMA_NONE 3 1026 1027 #define pci_pool dma_pool 1028 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 1029 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 1030 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 1031 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 1032 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 1033 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 1034 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1035 _size, _vaddr, _dma_handle) 1036 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 1037 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1038 _sg, _nents, (enum dma_data_direction)_dir) 1039 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 1040 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1041 (_ptr), (_size), (enum dma_data_direction)_dir) 1042 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 1043 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1044 _addr, _size, (enum dma_data_direction)_dir) 1045 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 1046 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1047 _sg, _nents, (enum dma_data_direction)_dir) 1048 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 1049 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 1050 _offset, _size, (enum dma_data_direction)_dir) 1051 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 1052 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1053 _dma_address, _size, (enum dma_data_direction)_dir) 1054 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1055 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1056 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1057 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1058 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1059 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1060 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1061 #define pci_unmap_addr dma_unmap_addr 1062 #define pci_unmap_addr_set dma_unmap_addr_set 1063 #define pci_unmap_len dma_unmap_len 1064 #define pci_unmap_len_set dma_unmap_len_set 1065 1066 typedef unsigned int __bitwise pci_channel_state_t; 1067 typedef unsigned int __bitwise pci_ers_result_t; 1068 1069 enum pci_channel_state { 1070 pci_channel_io_normal = 1, 1071 pci_channel_io_frozen = 2, 1072 pci_channel_io_perm_failure = 3, 1073 }; 1074 1075 enum pci_ers_result { 1076 PCI_ERS_RESULT_NONE = 1, 1077 PCI_ERS_RESULT_CAN_RECOVER = 2, 1078 PCI_ERS_RESULT_NEED_RESET = 3, 1079 PCI_ERS_RESULT_DISCONNECT = 4, 1080 PCI_ERS_RESULT_RECOVERED = 5, 1081 }; 1082 1083 /* PCI bus error event callbacks */ 1084 struct pci_error_handlers { 1085 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1086 enum pci_channel_state error); 1087 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1088 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1089 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1090 void (*resume)(struct pci_dev *dev); 1091 }; 1092 1093 /* FreeBSD does not support SRIOV - yet */ 1094 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1095 { 1096 return dev; 1097 } 1098 1099 static inline bool pci_is_pcie(struct pci_dev *dev) 1100 { 1101 return !!pci_pcie_cap(dev); 1102 } 1103 1104 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1105 { 1106 int pos; 1107 u16 reg16; 1108 1109 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1110 if (!pos) 1111 return 0; 1112 1113 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1114 1115 return reg16; 1116 } 1117 1118 static inline int pci_pcie_type(struct pci_dev *dev) 1119 { 1120 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1121 } 1122 1123 static inline int pcie_cap_version(struct pci_dev *dev) 1124 { 1125 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1126 } 1127 1128 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1129 { 1130 int type = pci_pcie_type(dev); 1131 1132 return pcie_cap_version(dev) > 1 || 1133 type == PCI_EXP_TYPE_ROOT_PORT || 1134 type == PCI_EXP_TYPE_ENDPOINT || 1135 type == PCI_EXP_TYPE_LEG_END; 1136 } 1137 1138 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1139 { 1140 return true; 1141 } 1142 1143 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1144 { 1145 int type = pci_pcie_type(dev); 1146 1147 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1148 (type == PCI_EXP_TYPE_DOWNSTREAM && 1149 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1150 } 1151 1152 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1153 { 1154 int type = pci_pcie_type(dev); 1155 1156 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1157 type == PCI_EXP_TYPE_RC_EC; 1158 } 1159 1160 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1161 { 1162 if (!pci_is_pcie(dev)) 1163 return false; 1164 1165 switch (pos) { 1166 case PCI_EXP_FLAGS_TYPE: 1167 return true; 1168 case PCI_EXP_DEVCAP: 1169 case PCI_EXP_DEVCTL: 1170 case PCI_EXP_DEVSTA: 1171 return pcie_cap_has_devctl(dev); 1172 case PCI_EXP_LNKCAP: 1173 case PCI_EXP_LNKCTL: 1174 case PCI_EXP_LNKSTA: 1175 return pcie_cap_has_lnkctl(dev); 1176 case PCI_EXP_SLTCAP: 1177 case PCI_EXP_SLTCTL: 1178 case PCI_EXP_SLTSTA: 1179 return pcie_cap_has_sltctl(dev); 1180 case PCI_EXP_RTCTL: 1181 case PCI_EXP_RTCAP: 1182 case PCI_EXP_RTSTA: 1183 return pcie_cap_has_rtctl(dev); 1184 case PCI_EXP_DEVCAP2: 1185 case PCI_EXP_DEVCTL2: 1186 case PCI_EXP_LNKCAP2: 1187 case PCI_EXP_LNKCTL2: 1188 case PCI_EXP_LNKSTA2: 1189 return pcie_cap_version(dev) > 1; 1190 default: 1191 return false; 1192 } 1193 } 1194 1195 static inline int 1196 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1197 { 1198 if (pos & 3) 1199 return -EINVAL; 1200 1201 if (!pcie_capability_reg_implemented(dev, pos)) 1202 return -EINVAL; 1203 1204 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1205 } 1206 1207 static inline int 1208 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1209 { 1210 if (pos & 3) 1211 return -EINVAL; 1212 1213 if (!pcie_capability_reg_implemented(dev, pos)) 1214 return -EINVAL; 1215 1216 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1217 } 1218 1219 static inline int 1220 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1221 { 1222 if (pos & 1) 1223 return -EINVAL; 1224 1225 if (!pcie_capability_reg_implemented(dev, pos)) 1226 return 0; 1227 1228 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1229 } 1230 1231 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1232 enum pci_bus_speed *speed, enum pcie_link_width *width) 1233 { 1234 *speed = PCI_SPEED_UNKNOWN; 1235 *width = PCIE_LNK_WIDTH_UNKNOWN; 1236 return (0); 1237 } 1238 1239 static inline int 1240 pci_num_vf(struct pci_dev *dev) 1241 { 1242 return (0); 1243 } 1244 1245 static inline enum pci_bus_speed 1246 pcie_get_speed_cap(struct pci_dev *dev) 1247 { 1248 device_t root; 1249 uint32_t lnkcap, lnkcap2; 1250 int error, pos; 1251 1252 root = device_get_parent(dev->dev.bsddev); 1253 if (root == NULL) 1254 return (PCI_SPEED_UNKNOWN); 1255 root = device_get_parent(root); 1256 if (root == NULL) 1257 return (PCI_SPEED_UNKNOWN); 1258 root = device_get_parent(root); 1259 if (root == NULL) 1260 return (PCI_SPEED_UNKNOWN); 1261 1262 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1263 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1264 return (PCI_SPEED_UNKNOWN); 1265 1266 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1267 return (PCI_SPEED_UNKNOWN); 1268 1269 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1270 1271 if (lnkcap2) { /* PCIe r3.0-compliant */ 1272 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1273 return (PCIE_SPEED_2_5GT); 1274 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1275 return (PCIE_SPEED_5_0GT); 1276 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1277 return (PCIE_SPEED_8_0GT); 1278 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1279 return (PCIE_SPEED_16_0GT); 1280 } else { /* pre-r3.0 */ 1281 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1282 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1283 return (PCIE_SPEED_2_5GT); 1284 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1285 return (PCIE_SPEED_5_0GT); 1286 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1287 return (PCIE_SPEED_8_0GT); 1288 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1289 return (PCIE_SPEED_16_0GT); 1290 } 1291 return (PCI_SPEED_UNKNOWN); 1292 } 1293 1294 static inline enum pcie_link_width 1295 pcie_get_width_cap(struct pci_dev *dev) 1296 { 1297 uint32_t lnkcap; 1298 1299 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1300 if (lnkcap) 1301 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1302 1303 return (PCIE_LNK_WIDTH_UNKNOWN); 1304 } 1305 1306 static inline int 1307 pcie_get_mps(struct pci_dev *dev) 1308 { 1309 return (pci_get_max_payload(dev->dev.bsddev)); 1310 } 1311 1312 static inline uint32_t 1313 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1314 { 1315 1316 switch(spd) { 1317 case PCIE_SPEED_16_0GT: 1318 return (16000 * 128 / 130); 1319 case PCIE_SPEED_8_0GT: 1320 return (8000 * 128 / 130); 1321 case PCIE_SPEED_5_0GT: 1322 return (5000 * 8 / 10); 1323 case PCIE_SPEED_2_5GT: 1324 return (2500 * 8 / 10); 1325 default: 1326 return (0); 1327 } 1328 } 1329 1330 static inline uint32_t 1331 pcie_bandwidth_available(struct pci_dev *pdev, 1332 struct pci_dev **limiting, 1333 enum pci_bus_speed *speed, 1334 enum pcie_link_width *width) 1335 { 1336 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1337 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1338 1339 if (speed) 1340 *speed = nspeed; 1341 if (width) 1342 *width = nwidth; 1343 1344 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1345 } 1346 1347 static inline struct pci_dev * 1348 pcie_find_root_port(struct pci_dev *pdev) 1349 { 1350 device_t root; 1351 1352 if (pdev->root != NULL) 1353 return (pdev->root); 1354 1355 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1356 if (root == NULL) 1357 return (NULL); 1358 1359 pdev->root = lkpinew_pci_dev(root); 1360 return (pdev->root); 1361 } 1362 1363 /* This is needed when people rip out the device "HotPlug". */ 1364 static inline void 1365 pci_lock_rescan_remove(void) 1366 { 1367 } 1368 1369 static inline void 1370 pci_unlock_rescan_remove(void) 1371 { 1372 } 1373 1374 static __inline void 1375 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1376 { 1377 } 1378 1379 /* 1380 * The following functions can be used to attach/detach the LinuxKPI's 1381 * PCI device runtime. The pci_driver and pci_device_id pointer is 1382 * allowed to be NULL. Other pointers must be all valid. 1383 * The pci_dev structure should be zero-initialized before passed 1384 * to the linux_pci_attach_device function. 1385 */ 1386 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1387 const struct pci_device_id *, struct pci_dev *); 1388 extern int linux_pci_detach_device(struct pci_dev *); 1389 1390 static inline int 1391 pci_dev_present(const struct pci_device_id *cur) 1392 { 1393 while (cur != NULL && (cur->vendor || cur->device)) { 1394 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1395 return (1); 1396 } 1397 cur++; 1398 } 1399 return (0); 1400 } 1401 1402 static inline bool 1403 pci_is_root_bus(struct pci_bus *pbus) 1404 { 1405 1406 return (pbus->self == NULL); 1407 } 1408 1409 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1410 unsigned int bus, unsigned int devfn); 1411 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1412 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1413 1414 static inline int 1415 pci_domain_nr(struct pci_bus *pbus) 1416 { 1417 1418 return (pbus->domain); 1419 } 1420 1421 static inline int 1422 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1423 int pos, uint32_t *val, int len) 1424 { 1425 1426 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1427 return (0); 1428 } 1429 1430 static inline int 1431 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1432 { 1433 uint32_t tmp; 1434 int ret; 1435 1436 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1437 *val = (u16)tmp; 1438 return (ret); 1439 } 1440 1441 static inline int 1442 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1443 { 1444 uint32_t tmp; 1445 int ret; 1446 1447 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1448 *val = (u8)tmp; 1449 return (ret); 1450 } 1451 1452 static inline int 1453 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1454 uint32_t val, int size) 1455 { 1456 1457 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1458 return (0); 1459 } 1460 1461 static inline int 1462 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1463 uint8_t val) 1464 { 1465 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1466 } 1467 1468 static inline int 1469 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1470 uint16_t val) 1471 { 1472 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1473 } 1474 1475 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1476 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1477 1478 /* -------------------------------------------------------------------------- */ 1479 1480 static inline int 1481 pcim_enable_device(struct pci_dev *pdev) 1482 { 1483 struct pci_devres *dr; 1484 int error; 1485 1486 /* Here we cannot run through the pdev->managed check. */ 1487 dr = lkpi_pci_devres_get_alloc(pdev); 1488 if (dr == NULL) 1489 return (-ENOMEM); 1490 1491 /* If resources were enabled before do not do it again. */ 1492 if (dr->enable_io) 1493 return (0); 1494 1495 error = pci_enable_device(pdev); 1496 if (error == 0) 1497 dr->enable_io = true; 1498 1499 /* This device is not managed. */ 1500 pdev->managed = true; 1501 1502 return (error); 1503 } 1504 1505 static inline struct pcim_iomap_devres * 1506 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev) 1507 { 1508 struct pcim_iomap_devres *dr; 1509 1510 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release, 1511 NULL, NULL); 1512 if (dr == NULL) { 1513 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release, 1514 sizeof(*dr), GFP_KERNEL | __GFP_ZERO); 1515 if (dr != NULL) 1516 lkpi_devres_add(&pdev->dev, dr); 1517 } 1518 1519 if (dr == NULL) 1520 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__); 1521 1522 return (dr); 1523 } 1524 1525 static inline void __iomem ** 1526 pcim_iomap_table(struct pci_dev *pdev) 1527 { 1528 struct pcim_iomap_devres *dr; 1529 1530 dr = lkpi_pcim_iomap_devres_find(pdev); 1531 if (dr == NULL) 1532 return (NULL); 1533 1534 /* 1535 * If the driver has manually set a flag to be able to request the 1536 * resource to use bus_read/write_<n>, return the shadow table. 1537 */ 1538 if (pdev->want_iomap_res) 1539 return ((void **)dr->res_table); 1540 1541 /* This is the Linux default. */ 1542 return (dr->mmio_table); 1543 } 1544 1545 static inline int 1546 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1547 { 1548 struct pcim_iomap_devres *dr; 1549 void *res; 1550 uint32_t mappings, requests, req_mask; 1551 int bar, error; 1552 1553 dr = lkpi_pcim_iomap_devres_find(pdev); 1554 if (dr == NULL) 1555 return (-ENOMEM); 1556 1557 /* Request all the BARs ("regions") we do not iomap. */ 1558 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1559 for (bar = requests = 0; requests != req_mask; bar++) { 1560 if ((req_mask & (1 << bar)) == 0) 1561 continue; 1562 error = pci_request_region(pdev, bar, name); 1563 if (error != 0 && error != -ENODEV) 1564 goto err; 1565 requests |= (1 << bar); 1566 } 1567 1568 /* Now iomap all the requested (by "mask") ones. */ 1569 for (bar = mappings = 0; mappings != mask; bar++) { 1570 if ((mask & (1 << bar)) == 0) 1571 continue; 1572 1573 /* Request double is not allowed. */ 1574 if (dr->mmio_table[bar] != NULL) { 1575 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1576 __func__, bar, dr->mmio_table[bar]); 1577 goto err; 1578 } 1579 1580 res = _lkpi_pci_iomap(pdev, bar, 0); 1581 if (res == NULL) 1582 goto err; 1583 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1584 dr->res_table[bar] = res; 1585 1586 mappings |= (1 << bar); 1587 } 1588 1589 return (0); 1590 1591 err: 1592 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1593 if ((mappings & (1 << bar)) != 0) { 1594 res = dr->mmio_table[bar]; 1595 if (res == NULL) 1596 continue; 1597 pci_iounmap(pdev, res); 1598 } else if ((requests & (1 << bar)) != 0) { 1599 pci_release_region(pdev, bar); 1600 } 1601 } 1602 1603 return (-EINVAL); 1604 } 1605 1606 /* This is a FreeBSD extension so we can use bus_*(). */ 1607 static inline void 1608 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1609 { 1610 pdev->want_iomap_res = true; 1611 } 1612 1613 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1614