1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2025 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 #include <linux/device/driver.h> 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_private.h> 49 50 #include <machine/resource.h> 51 52 #include <linux/list.h> 53 #include <linux/dmapool.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/compiler.h> 56 #include <linux/errno.h> 57 #include <asm/atomic.h> 58 #include <asm/memtype.h> 59 #include <linux/device.h> 60 #include <linux/pci_ids.h> 61 #include <linux/pm.h> 62 #include <linux/interrupt.h> 63 64 /* 65 * <linux/ioport.h> should be included here, like Linux, but we can't have that 66 * because Linux `struct resource` definition would conflict with FreeBSD 67 * native definition. 68 * 69 * At least the amdgpu DRM driver (amdgpu_isp.c at the time of this writing) 70 * relies on this indirect include to get the definition of Linux `struct 71 * resource`. As a workaround, we include <linux/ioport.h> from 72 * <linux/mfd/core.h>. 73 */ 74 75 #include <linux/kernel.h> /* pr_debug */ 76 77 struct pci_device_id { 78 uint32_t vendor; 79 uint32_t device; 80 uint32_t subvendor; 81 uint32_t subdevice; 82 uint32_t class; 83 uint32_t class_mask; 84 uintptr_t driver_data; 85 }; 86 87 #define MODULE_DEVICE_TABLE_BUS_pci(_bus, _table) \ 88 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 89 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 90 91 #define PCI_ANY_ID -1U 92 93 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 94 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 95 #define PCI_FUNC(devfn) ((devfn) & 0x07) 96 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 97 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 98 99 #define PCI_VDEVICE(_vendor, _device) \ 100 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 101 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 102 #define PCI_DEVICE(_vendor, _device) \ 103 .vendor = (_vendor), .device = (_device), \ 104 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 105 106 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 107 108 #define PCI_STD_NUM_BARS 6 109 #define PCI_BASE_ADDRESS_0 PCIR_BARS 110 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 111 #define PCI_VENDOR_ID PCIR_VENDOR 112 #define PCI_DEVICE_ID PCIR_DEVICE 113 #define PCI_COMMAND PCIR_COMMAND 114 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 115 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 116 #define PCI_PRIMARY_BUS PCIR_PRIBUS_1 117 #define PCI_SECONDARY_BUS PCIR_SECBUS_1 118 #define PCI_SUBORDINATE_BUS PCIR_SUBBUS_1 119 #define PCI_SEC_LATENCY_TIMER PCIR_SECLAT_1 120 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 121 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 122 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 123 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 124 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 125 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 126 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 127 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 128 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 129 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 130 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 131 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 132 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 133 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 134 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 135 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 136 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 137 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 138 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 139 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 140 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 141 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 142 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 143 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 144 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 145 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 146 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 147 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 148 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 149 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 150 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 151 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 152 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 153 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 154 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 155 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 156 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 157 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 158 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 159 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 160 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 161 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 162 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 163 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 164 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 165 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 166 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 167 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 168 #define PCI_EXP_LNKCTL2_TLS 0x000f 169 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 170 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 171 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 172 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 173 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 174 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 175 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 176 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 177 178 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 179 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 180 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 181 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 182 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 183 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 184 185 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 186 #define PCI_EXP_DEVSTA_TRPND 0x0020 187 188 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 189 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 190 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 191 192 enum pci_bus_speed { 193 PCI_SPEED_UNKNOWN = -1, 194 PCIE_SPEED_2_5GT, 195 PCIE_SPEED_5_0GT, 196 PCIE_SPEED_8_0GT, 197 PCIE_SPEED_16_0GT, 198 PCIE_SPEED_32_0GT, 199 PCIE_SPEED_64_0GT, 200 }; 201 202 enum pcie_link_width { 203 PCIE_LNK_WIDTH_RESRV = 0x00, 204 PCIE_LNK_X1 = 0x01, 205 PCIE_LNK_X2 = 0x02, 206 PCIE_LNK_X4 = 0x04, 207 PCIE_LNK_X8 = 0x08, 208 PCIE_LNK_X12 = 0x0c, 209 PCIE_LNK_X16 = 0x10, 210 PCIE_LNK_X32 = 0x20, 211 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 212 }; 213 214 #define PCIE_LINK_STATE_L0S 0x00000001 215 #define PCIE_LINK_STATE_L1 0x00000002 216 #define PCIE_LINK_STATE_CLKPM 0x00000004 217 218 typedef int pci_power_t; 219 220 #define PCI_D0 PCI_POWERSTATE_D0 221 #define PCI_D1 PCI_POWERSTATE_D1 222 #define PCI_D2 PCI_POWERSTATE_D2 223 #define PCI_D3hot PCI_POWERSTATE_D3_HOT 224 #define PCI_D3cold PCI_POWERSTATE_D3_COLD 225 226 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 227 228 extern const char *pci_power_names[6]; 229 230 #define PCI_ERR_UNCOR_STATUS PCIR_AER_UC_STATUS 231 #define PCI_ERR_COR_STATUS PCIR_AER_COR_STATUS 232 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 233 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 234 235 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 236 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 237 238 #define PCI_L1SS_CTL1 0x8 239 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 240 241 #define PCI_IRQ_INTX 0x01 242 #define PCI_IRQ_MSI 0x02 243 #define PCI_IRQ_MSIX 0x04 244 #define PCI_IRQ_AFFINITY 0x08 245 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_INTX) 246 247 #if defined(LINUXKPI_VERSION) && (LINUXKPI_VERSION <= 61000) 248 #define PCI_IRQ_LEGACY PCI_IRQ_INTX 249 #endif 250 251 /* 252 * Linux PCI code uses `PCI_SET_ERROR_RESPONSE()` to indicate to the caller of 253 * a `pci_read_*()` function that the read failed. An example of failure is 254 * whether the device was disconnected. It is a bit weird because Linux 255 * `pci_read_*()` can return an error value, as the read value is stored in a 256 * integer passed by pointer. 257 * 258 * We don't set PCI_ERROR_RESPONSE anywhere as of this commit, but the DRM 259 * drivers started to use `PCI_POSSIBLE_ERROR()`. 260 */ 261 #define PCI_ERROR_RESPONSE (~0ULL) 262 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 263 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 264 265 struct pci_dev; 266 267 struct pci_driver { 268 struct list_head node; 269 char *name; 270 const struct pci_device_id *id_table; 271 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 272 void (*remove)(struct pci_dev *dev); 273 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 274 int (*resume) (struct pci_dev *dev); /* Device woken up */ 275 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 276 driver_t bsddriver; 277 devclass_t bsdclass; 278 struct device_driver driver; 279 const struct pci_error_handlers *err_handler; 280 bool isdrm; 281 int bsd_probe_return; 282 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 283 const nvlist_t *pf_config); 284 void (*bsd_iov_uninit)(device_t dev); 285 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 286 const nvlist_t *vf_config); 287 }; 288 289 struct pci_bus { 290 struct pci_dev *self; 291 /* struct pci_bus *parent */ 292 int domain; 293 int number; 294 }; 295 296 extern struct list_head pci_drivers; 297 extern struct list_head pci_devices; 298 extern spinlock_t pci_lock; 299 300 #define __devexit_p(x) x 301 302 #define module_pci_driver(_drv) \ 303 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver) 304 305 struct msi_msg { 306 uint32_t data; 307 }; 308 309 struct pci_msi_desc { 310 struct { 311 bool is_64; 312 } msi_attrib; 313 }; 314 315 struct msi_desc { 316 struct msi_msg msg; 317 struct pci_msi_desc pci; 318 }; 319 320 struct msix_entry { 321 int entry; 322 int vector; 323 }; 324 325 /* 326 * If we find drivers accessing this from multiple KPIs we may have to 327 * refcount objects of this structure. 328 */ 329 struct resource; 330 struct pci_mmio_region { 331 TAILQ_ENTRY(pci_mmio_region) next; 332 struct resource *res; 333 int rid; 334 int type; 335 }; 336 337 struct pci_dev { 338 struct device dev; 339 struct list_head links; 340 struct pci_driver *pdrv; 341 struct pci_bus *bus; 342 struct pci_dev *root; 343 pci_power_t current_state; 344 uint16_t device; 345 uint16_t vendor; 346 uint16_t subsystem_vendor; 347 uint16_t subsystem_device; 348 unsigned int irq; 349 unsigned int devfn; 350 uint32_t class; 351 uint8_t revision; 352 uint8_t msi_cap; 353 uint8_t msix_cap; 354 bool managed; /* devres "pcim_*(). */ 355 bool want_iomap_res; 356 bool msi_enabled; 357 bool msix_enabled; 358 phys_addr_t rom; 359 size_t romlen; 360 struct msi_desc **msi_desc; 361 char *path_name; 362 spinlock_t pcie_cap_lock; 363 364 TAILQ_HEAD(, pci_mmio_region) mmio; 365 }; 366 367 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 368 unsigned int flags); 369 bool pci_device_is_present(struct pci_dev *pdev); 370 371 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 372 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 373 void *linuxkpi_pci_iomap_range(struct pci_dev *, int, 374 unsigned long, unsigned long); 375 void *linuxkpi_pci_iomap(struct pci_dev *, int, unsigned long); 376 void *linuxkpi_pcim_iomap(struct pci_dev *, int, unsigned long); 377 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 378 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 379 const char *name); 380 int linuxkpi_pci_request_region(struct pci_dev *, int, const char *); 381 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 382 int linuxkpi_pcim_request_all_regions(struct pci_dev *, const char *); 383 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 384 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 385 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 386 int nreq); 387 388 /* Internal helper function(s). */ 389 struct pci_dev *lkpinew_pci_dev(device_t); 390 void lkpi_pci_devres_release(struct device *, void *); 391 struct pci_dev *lkpi_pci_get_device(uint32_t, uint32_t, struct pci_dev *); 392 struct msi_desc *lkpi_pci_msi_desc_alloc(unsigned int); 393 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 394 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 395 396 #define pci_err(pdev, fmt, ...) \ 397 dev_err(&(pdev)->dev, fmt, ##__VA_ARGS__) 398 #define pci_info(pdev, fmt, ...) \ 399 dev_info(&(pdev)->dev, fmt, ##__VA_ARGS__) 400 401 static inline bool 402 dev_is_pci(struct device *dev) 403 { 404 return (is_pci_device(dev->bsddev)); 405 } 406 407 static inline uint16_t 408 pci_dev_id(struct pci_dev *pdev) 409 { 410 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 411 } 412 413 static inline int 414 pci_resource_type(struct pci_dev *pdev, int bar) 415 { 416 struct pci_map *pm; 417 418 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 419 if (!pm) 420 return (-1); 421 422 if (PCI_BAR_IO(pm->pm_value)) 423 return (SYS_RES_IOPORT); 424 else 425 return (SYS_RES_MEMORY); 426 } 427 428 /* 429 * All drivers just seem to want to inspect the type not flags. 430 */ 431 static inline int 432 pci_resource_flags(struct pci_dev *pdev, int bar) 433 { 434 int type; 435 436 type = pci_resource_type(pdev, bar); 437 if (type < 0) 438 return (0); 439 return (1 << type); 440 } 441 442 static inline int 443 pci_select_bars(struct pci_dev *pdev, unsigned long flags) 444 { 445 int bars, bar; 446 447 bars = 0; 448 /* We only support BARs here; Linux may support more types. */ 449 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 450 int bar_flags; 451 452 bar_flags = pci_resource_flags(pdev, bar); 453 if ((bar_flags & flags) != 0) 454 bars |= (1 << bar); 455 } 456 457 return (bars); 458 } 459 460 static inline const char * 461 pci_name(struct pci_dev *d) 462 { 463 return d->path_name; 464 } 465 466 static inline void * 467 pci_get_drvdata(struct pci_dev *pdev) 468 { 469 470 return dev_get_drvdata(&pdev->dev); 471 } 472 473 static inline void 474 pci_set_drvdata(struct pci_dev *pdev, void *data) 475 { 476 477 dev_set_drvdata(&pdev->dev, data); 478 } 479 480 static inline struct pci_dev * 481 pci_dev_get(struct pci_dev *pdev) 482 { 483 484 if (pdev != NULL) 485 get_device(&pdev->dev); 486 return (pdev); 487 } 488 489 static __inline void 490 pci_dev_put(struct pci_dev *pdev) 491 { 492 493 if (pdev != NULL) 494 put_device(&pdev->dev); 495 } 496 497 static inline int 498 pci_enable_device(struct pci_dev *pdev) 499 { 500 501 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 502 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 503 return (0); 504 } 505 506 static inline void 507 pci_disable_device(struct pci_dev *pdev) 508 { 509 510 pci_disable_busmaster(pdev->dev.bsddev); 511 } 512 513 static inline int 514 pci_set_master(struct pci_dev *pdev) 515 { 516 517 pci_enable_busmaster(pdev->dev.bsddev); 518 return (0); 519 } 520 521 static inline int 522 pci_set_power_state(struct pci_dev *pdev, int state) 523 { 524 525 pci_set_powerstate(pdev->dev.bsddev, state); 526 return (0); 527 } 528 529 static inline int 530 pci_clear_master(struct pci_dev *pdev) 531 { 532 533 pci_disable_busmaster(pdev->dev.bsddev); 534 return (0); 535 } 536 537 static inline bool 538 pci_is_root_bus(struct pci_bus *pbus) 539 { 540 541 return (pbus->self == NULL); 542 } 543 544 static inline struct pci_dev * 545 pci_upstream_bridge(struct pci_dev *pdev) 546 { 547 548 if (pci_is_root_bus(pdev->bus)) 549 return (NULL); 550 551 /* 552 * If we do not have a (proper) "upstream bridge" set, e.g., we point 553 * to ourselves, try to handle this case on the fly like we do 554 * for pcie_find_root_port(). 555 */ 556 if (pdev == pdev->bus->self) { 557 device_t bridge; 558 559 /* 560 * In the case of DRM drivers, the passed device is a child of 561 * `vgapci`. We want to start the lookup from `vgapci`, so the 562 * parent of the passed `drmn`. 563 * 564 * We can use the `isdrm` flag to determine this. 565 */ 566 bridge = pdev->dev.bsddev; 567 if (pdev->pdrv != NULL && pdev->pdrv->isdrm) 568 bridge = device_get_parent(bridge); 569 if (bridge == NULL) 570 goto done; 571 572 bridge = device_get_parent(bridge); 573 if (bridge == NULL) 574 goto done; 575 bridge = device_get_parent(bridge); 576 if (bridge == NULL) 577 goto done; 578 if (!is_pci_device(bridge)) 579 goto done; 580 581 /* 582 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 583 * for it so it can be returned. 584 */ 585 pdev->bus->self = lkpinew_pci_dev(bridge); 586 } 587 done: 588 return (pdev->bus->self); 589 } 590 591 #define pci_request_region(pdev, bar, res_name) \ 592 linuxkpi_pci_request_region(pdev, bar, res_name) 593 #define pci_release_region(pdev, bar) \ 594 linuxkpi_pci_release_region(pdev, bar) 595 #define pci_request_regions(pdev, res_name) \ 596 linuxkpi_pci_request_regions(pdev, res_name) 597 #define pci_release_regions(pdev) \ 598 linuxkpi_pci_release_regions(pdev) 599 #define pcim_request_all_regions(pdev, name) \ 600 linuxkpi_pcim_request_all_regions(pdev, name) 601 602 static inline void 603 lkpi_pci_disable_msix(struct pci_dev *pdev) 604 { 605 606 pci_release_msi(pdev->dev.bsddev); 607 608 /* 609 * The MSIX IRQ numbers associated with this PCI device are no 610 * longer valid and might be re-assigned. Make sure 611 * lkpi_pci_find_irq_dev() does no longer see them by 612 * resetting their references to zero: 613 */ 614 pdev->dev.irq_start = 0; 615 pdev->dev.irq_end = 0; 616 pdev->msix_enabled = false; 617 } 618 /* Only for consistency. No conflict on that one. */ 619 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 620 621 static inline void 622 lkpi_pci_disable_msi(struct pci_dev *pdev) 623 { 624 625 pci_release_msi(pdev->dev.bsddev); 626 627 pdev->dev.irq_start = 0; 628 pdev->dev.irq_end = 0; 629 pdev->irq = pdev->dev.irq; 630 pdev->msi_enabled = false; 631 } 632 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 633 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 634 635 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 636 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 637 638 static inline bus_addr_t 639 pci_bus_address(struct pci_dev *pdev, int bar) 640 { 641 642 return (pci_resource_start(pdev, bar)); 643 } 644 645 #define PCI_CAP_ID_EXP PCIY_EXPRESS 646 #define PCI_CAP_ID_PCIX PCIY_PCIX 647 #define PCI_CAP_ID_AGP PCIY_AGP 648 #define PCI_CAP_ID_PM PCIY_PMG 649 650 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 651 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 652 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 653 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 654 #define PCI_EXP_LNKSTA PCIER_LINK_STA 655 656 static inline int 657 pci_find_capability(struct pci_dev *pdev, int capid) 658 { 659 int reg; 660 661 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 662 return (0); 663 return (reg); 664 } 665 666 static inline int pci_pcie_cap(struct pci_dev *dev) 667 { 668 return pci_find_capability(dev, PCI_CAP_ID_EXP); 669 } 670 671 static inline int 672 pci_find_ext_capability(struct pci_dev *pdev, int capid) 673 { 674 int reg; 675 676 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 677 return (0); 678 return (reg); 679 } 680 681 static __inline bool 682 pci_pme_capable(struct pci_dev *pdev, pci_power_t state) 683 { 684 return (pci_has_pme(pdev->dev.bsddev, state)); 685 } 686 687 static inline int 688 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 689 { 690 691 if (!pci_enable_aspm) 692 return (-EPERM); 693 694 return (-ENXIO); 695 } 696 697 static inline int 698 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 699 { 700 701 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 702 return (0); 703 } 704 705 static inline int 706 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 707 { 708 709 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 710 return (0); 711 } 712 713 static inline int 714 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 715 { 716 717 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 718 return (0); 719 } 720 721 static inline int 722 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 723 { 724 725 pci_write_config(pdev->dev.bsddev, where, val, 1); 726 return (0); 727 } 728 729 static inline int 730 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 731 { 732 733 pci_write_config(pdev->dev.bsddev, where, val, 2); 734 return (0); 735 } 736 737 static inline int 738 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 739 { 740 741 pci_write_config(pdev->dev.bsddev, where, val, 4); 742 return (0); 743 } 744 745 int linux_pci_register_driver(struct pci_driver *pdrv); 746 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 747 void linux_pci_unregister_driver(struct pci_driver *pdrv); 748 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 749 750 #define pci_register_driver(pdrv) \ 751 linux_pci_register_driver(pdrv) 752 #define pci_unregister_driver(pdrv) \ 753 linux_pci_unregister_driver(pdrv) 754 755 /* 756 * Enable msix, positive errors indicate actual number of available 757 * vectors. Negative errors are failures. 758 * 759 * NB: define added to prevent this definition of pci_enable_msix from 760 * clashing with the native FreeBSD version. 761 */ 762 #define pci_enable_msix(...) \ 763 linuxkpi_pci_enable_msix(__VA_ARGS__) 764 765 #define pci_enable_msix_range(...) \ 766 linux_pci_enable_msix_range(__VA_ARGS__) 767 768 static inline int 769 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 770 int minvec, int maxvec) 771 { 772 int nvec = maxvec; 773 int rc; 774 775 if (maxvec < minvec) 776 return (-ERANGE); 777 778 do { 779 rc = pci_enable_msix(dev, entries, nvec); 780 if (rc < 0) { 781 return (rc); 782 } else if (rc > 0) { 783 if (rc < minvec) 784 return (-ENOSPC); 785 nvec = rc; 786 } 787 } while (rc); 788 return (nvec); 789 } 790 791 #define pci_enable_msi(pdev) \ 792 linux_pci_enable_msi(pdev) 793 794 static inline int 795 pci_enable_msi(struct pci_dev *pdev) 796 { 797 798 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 799 } 800 801 static inline int 802 pci_channel_offline(struct pci_dev *pdev) 803 { 804 805 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 806 } 807 808 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 809 { 810 return -ENODEV; 811 } 812 813 static inline void pci_disable_sriov(struct pci_dev *dev) 814 { 815 } 816 817 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \ 818 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) 819 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 820 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 821 #define pcim_iomap(pdev, bar, maxlen) \ 822 linuxkpi_pcim_iomap(pdev, bar, maxlen) 823 #define pci_iounmap(pdev, res) \ 824 linuxkpi_pci_iounmap(pdev, res) 825 826 static inline void 827 lkpi_pci_save_state(struct pci_dev *pdev) 828 { 829 830 pci_save_state(pdev->dev.bsddev); 831 } 832 833 static inline void 834 lkpi_pci_restore_state(struct pci_dev *pdev) 835 { 836 837 pci_restore_state(pdev->dev.bsddev); 838 } 839 840 #define pci_save_state(dev) lkpi_pci_save_state(dev) 841 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 842 843 static inline int 844 linuxkpi_pci_enable_wake(struct pci_dev *pdev, pci_power_t state, bool ena) 845 { 846 /* 847 * We do not currently support this in device.h either to 848 * check if the device is allowed to wake up in first place. 849 */ 850 pr_debug("%s: TODO\n", __func__); 851 return (0); 852 } 853 #define pci_enable_wake(dev, state, ena) \ 854 linuxkpi_pci_enable_wake(dev, state, ena) 855 856 static inline int 857 pci_reset_function(struct pci_dev *pdev) 858 { 859 860 return (-ENOSYS); 861 } 862 863 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 864 const struct pci_device_id _table[] __devinitdata 865 866 /* XXX This should not be necessary. */ 867 #define pcix_set_mmrbc(d, v) 0 868 #define pcix_get_max_mmrbc(d) 0 869 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 870 871 #define PCI_DMA_BIDIRECTIONAL 0 872 #define PCI_DMA_TODEVICE 1 873 #define PCI_DMA_FROMDEVICE 2 874 #define PCI_DMA_NONE 3 875 876 #define pci_pool dma_pool 877 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 878 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 879 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 880 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 881 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 882 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 883 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 884 _size, _vaddr, _dma_handle) 885 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 886 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 887 _sg, _nents, (enum dma_data_direction)_dir) 888 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 889 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 890 (_ptr), (_size), (enum dma_data_direction)_dir) 891 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 892 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 893 _addr, _size, (enum dma_data_direction)_dir) 894 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 895 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 896 _sg, _nents, (enum dma_data_direction)_dir) 897 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 898 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 899 _offset, _size, (enum dma_data_direction)_dir) 900 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 901 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 902 _dma_address, _size, (enum dma_data_direction)_dir) 903 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 904 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 905 dma_mapping_error(&(_pdev)->dev, _dma_addr) 906 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 907 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 908 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 909 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 910 #define pci_unmap_addr dma_unmap_addr 911 #define pci_unmap_addr_set dma_unmap_addr_set 912 #define pci_unmap_len dma_unmap_len 913 #define pci_unmap_len_set dma_unmap_len_set 914 915 void *linuxkpi_pci_map_rom(struct pci_dev *pdev, size_t *size); 916 void linuxkpi_pci_unmap_rom(struct pci_dev *pdev, void *rom); 917 #define pci_map_rom(pdev, size) linuxkpi_pci_map_rom(pdev, size) 918 #define pci_unmap_rom(pdev, rom) linuxkpi_pci_unmap_rom(pdev, rom) 919 920 typedef unsigned int __bitwise pci_channel_state_t; 921 typedef unsigned int __bitwise pci_ers_result_t; 922 923 enum pci_channel_state { 924 pci_channel_io_normal = 1, 925 pci_channel_io_frozen = 2, 926 pci_channel_io_perm_failure = 3, 927 }; 928 929 enum pci_ers_result { 930 PCI_ERS_RESULT_NONE = 1, 931 PCI_ERS_RESULT_CAN_RECOVER = 2, 932 PCI_ERS_RESULT_NEED_RESET = 3, 933 PCI_ERS_RESULT_DISCONNECT = 4, 934 PCI_ERS_RESULT_RECOVERED = 5, 935 }; 936 937 /* PCI bus error event callbacks */ 938 struct pci_error_handlers { 939 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 940 enum pci_channel_state error); 941 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 942 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 943 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 944 void (*resume)(struct pci_dev *dev); 945 void (*reset_prepare)(struct pci_dev *); 946 void (*reset_done)(struct pci_dev *); 947 }; 948 949 /* FreeBSD does not support SRIOV - yet */ 950 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 951 { 952 return dev; 953 } 954 955 static inline bool pci_is_pcie(struct pci_dev *dev) 956 { 957 return !!pci_pcie_cap(dev); 958 } 959 960 static inline u16 pcie_flags_reg(struct pci_dev *dev) 961 { 962 int pos; 963 u16 reg16; 964 965 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 966 if (!pos) 967 return 0; 968 969 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 970 971 return reg16; 972 } 973 974 static inline int pci_pcie_type(struct pci_dev *dev) 975 { 976 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 977 } 978 979 static inline int pcie_cap_version(struct pci_dev *dev) 980 { 981 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 982 } 983 984 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 985 { 986 int type = pci_pcie_type(dev); 987 988 return pcie_cap_version(dev) > 1 || 989 type == PCI_EXP_TYPE_ROOT_PORT || 990 type == PCI_EXP_TYPE_ENDPOINT || 991 type == PCI_EXP_TYPE_LEG_END; 992 } 993 994 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 995 { 996 return true; 997 } 998 999 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1000 { 1001 int type = pci_pcie_type(dev); 1002 1003 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1004 (type == PCI_EXP_TYPE_DOWNSTREAM && 1005 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1006 } 1007 1008 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1009 { 1010 int type = pci_pcie_type(dev); 1011 1012 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1013 type == PCI_EXP_TYPE_RC_EC; 1014 } 1015 1016 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1017 { 1018 if (!pci_is_pcie(dev)) 1019 return false; 1020 1021 switch (pos) { 1022 case PCI_EXP_FLAGS_TYPE: 1023 return true; 1024 case PCI_EXP_DEVCAP: 1025 case PCI_EXP_DEVCTL: 1026 case PCI_EXP_DEVSTA: 1027 return pcie_cap_has_devctl(dev); 1028 case PCI_EXP_LNKCAP: 1029 case PCI_EXP_LNKCTL: 1030 case PCI_EXP_LNKSTA: 1031 return pcie_cap_has_lnkctl(dev); 1032 case PCI_EXP_SLTCAP: 1033 case PCI_EXP_SLTCTL: 1034 case PCI_EXP_SLTSTA: 1035 return pcie_cap_has_sltctl(dev); 1036 case PCI_EXP_RTCTL: 1037 case PCI_EXP_RTCAP: 1038 case PCI_EXP_RTSTA: 1039 return pcie_cap_has_rtctl(dev); 1040 case PCI_EXP_DEVCAP2: 1041 case PCI_EXP_DEVCTL2: 1042 case PCI_EXP_LNKCAP2: 1043 case PCI_EXP_LNKCTL2: 1044 case PCI_EXP_LNKSTA2: 1045 return pcie_cap_version(dev) > 1; 1046 default: 1047 return false; 1048 } 1049 } 1050 1051 static inline int 1052 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1053 { 1054 *dst = 0; 1055 if (pos & 3) 1056 return -EINVAL; 1057 1058 if (!pcie_capability_reg_implemented(dev, pos)) 1059 return -EINVAL; 1060 1061 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1062 } 1063 1064 static inline int 1065 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1066 { 1067 *dst = 0; 1068 if (pos & 3) 1069 return -EINVAL; 1070 1071 if (!pcie_capability_reg_implemented(dev, pos)) 1072 return -EINVAL; 1073 1074 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1075 } 1076 1077 static inline int 1078 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1079 { 1080 if (pos & 1) 1081 return -EINVAL; 1082 1083 if (!pcie_capability_reg_implemented(dev, pos)) 1084 return 0; 1085 1086 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1087 } 1088 1089 static inline int 1090 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1091 uint16_t clear, uint16_t set) 1092 { 1093 int error; 1094 uint16_t v; 1095 1096 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1097 spin_lock(&dev->pcie_cap_lock); 1098 1099 error = pcie_capability_read_word(dev, pos, &v); 1100 if (error == 0) { 1101 v &= ~clear; 1102 v |= set; 1103 error = pcie_capability_write_word(dev, pos, v); 1104 } 1105 1106 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1107 spin_unlock(&dev->pcie_cap_lock); 1108 1109 return (error); 1110 } 1111 1112 static inline int 1113 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1114 { 1115 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1116 } 1117 1118 static inline int 1119 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1120 { 1121 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1122 } 1123 1124 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1125 enum pci_bus_speed *speed, enum pcie_link_width *width) 1126 { 1127 *speed = PCI_SPEED_UNKNOWN; 1128 *width = PCIE_LNK_WIDTH_UNKNOWN; 1129 return (0); 1130 } 1131 1132 static inline int 1133 pci_num_vf(struct pci_dev *dev) 1134 { 1135 return (0); 1136 } 1137 1138 static inline enum pci_bus_speed 1139 pcie_get_speed_cap(struct pci_dev *dev) 1140 { 1141 struct pci_dev *pbus; 1142 device_t root; 1143 uint32_t lnkcap, lnkcap2; 1144 int error, pos; 1145 1146 /* 1147 * We should always be called on a PCI device. 1148 * The only current consumer I could find was amdgpu which either 1149 * calls us directly on a pdev(drmn?) or with the result of 1150 * pci_upstream_bridge(). 1151 * 1152 * Treat "drmn" as special again as it is not a PCI device. 1153 */ 1154 if (dev->pdrv != NULL && dev->pdrv->isdrm) { 1155 pbus = pci_upstream_bridge(dev); 1156 if (pbus == NULL) 1157 return (PCI_SPEED_UNKNOWN); 1158 } else 1159 pbus = dev; 1160 1161 /* "root" may be misleading as it may not be that. */ 1162 root = pbus->dev.bsddev; 1163 1164 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1165 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1166 return (PCI_SPEED_UNKNOWN); 1167 1168 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1169 return (PCI_SPEED_UNKNOWN); 1170 1171 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1172 1173 if (lnkcap2) { /* PCIe r3.0-compliant */ 1174 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1175 return (PCIE_SPEED_2_5GT); 1176 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1177 return (PCIE_SPEED_5_0GT); 1178 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1179 return (PCIE_SPEED_8_0GT); 1180 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1181 return (PCIE_SPEED_16_0GT); 1182 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1183 return (PCIE_SPEED_32_0GT); 1184 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1185 return (PCIE_SPEED_64_0GT); 1186 } else { /* pre-r3.0 */ 1187 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1188 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1189 return (PCIE_SPEED_2_5GT); 1190 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1191 return (PCIE_SPEED_5_0GT); 1192 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1193 return (PCIE_SPEED_8_0GT); 1194 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1195 return (PCIE_SPEED_16_0GT); 1196 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1197 return (PCIE_SPEED_32_0GT); 1198 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1199 return (PCIE_SPEED_64_0GT); 1200 } 1201 return (PCI_SPEED_UNKNOWN); 1202 } 1203 1204 static inline enum pcie_link_width 1205 pcie_get_width_cap(struct pci_dev *dev) 1206 { 1207 uint32_t lnkcap; 1208 1209 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1210 if (lnkcap) 1211 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1212 1213 return (PCIE_LNK_WIDTH_UNKNOWN); 1214 } 1215 1216 static inline int 1217 pcie_get_mps(struct pci_dev *dev) 1218 { 1219 return (pci_get_max_payload(dev->dev.bsddev)); 1220 } 1221 1222 static inline uint32_t 1223 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1224 { 1225 1226 switch(spd) { 1227 case PCIE_SPEED_64_0GT: 1228 return (64000 * 128 / 130); 1229 case PCIE_SPEED_32_0GT: 1230 return (32000 * 128 / 130); 1231 case PCIE_SPEED_16_0GT: 1232 return (16000 * 128 / 130); 1233 case PCIE_SPEED_8_0GT: 1234 return (8000 * 128 / 130); 1235 case PCIE_SPEED_5_0GT: 1236 return (5000 * 8 / 10); 1237 case PCIE_SPEED_2_5GT: 1238 return (2500 * 8 / 10); 1239 default: 1240 return (0); 1241 } 1242 } 1243 1244 static inline uint32_t 1245 pcie_bandwidth_available(struct pci_dev *pdev, 1246 struct pci_dev **limiting, 1247 enum pci_bus_speed *speed, 1248 enum pcie_link_width *width) 1249 { 1250 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1251 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1252 1253 if (speed) 1254 *speed = nspeed; 1255 if (width) 1256 *width = nwidth; 1257 1258 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1259 } 1260 1261 static inline bool 1262 pcie_aspm_enabled(struct pci_dev *pdev) 1263 { 1264 return (false); 1265 } 1266 1267 static inline struct pci_dev * 1268 pcie_find_root_port(struct pci_dev *pdev) 1269 { 1270 device_t root; 1271 1272 if (pdev->root != NULL) 1273 return (pdev->root); 1274 1275 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1276 if (root == NULL) 1277 return (NULL); 1278 1279 pdev->root = lkpinew_pci_dev(root); 1280 return (pdev->root); 1281 } 1282 1283 /* This is needed when people rip out the device "HotPlug". */ 1284 static inline void 1285 pci_lock_rescan_remove(void) 1286 { 1287 } 1288 1289 static inline void 1290 pci_unlock_rescan_remove(void) 1291 { 1292 } 1293 1294 static __inline void 1295 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1296 { 1297 } 1298 1299 static inline int 1300 pci_rescan_bus(struct pci_bus *pbus) 1301 { 1302 device_t *devlist, parent; 1303 int devcount, error; 1304 1305 if (!device_is_attached(pbus->self->dev.bsddev)) 1306 return (0); 1307 /* pci_rescan_method() will work on the pcib (parent). */ 1308 error = BUS_RESCAN(pbus->self->dev.bsddev); 1309 if (error != 0) 1310 return (0); 1311 1312 parent = device_get_parent(pbus->self->dev.bsddev); 1313 error = device_get_children(parent, &devlist, &devcount); 1314 if (error != 0) 1315 return (0); 1316 if (devcount != 0) 1317 free(devlist, M_TEMP); 1318 1319 return (devcount); 1320 } 1321 1322 /* 1323 * The following functions can be used to attach/detach the LinuxKPI's 1324 * PCI device runtime. The pci_driver and pci_device_id pointer is 1325 * allowed to be NULL. Other pointers must be all valid. 1326 * The pci_dev structure should be zero-initialized before passed 1327 * to the linux_pci_attach_device function. 1328 */ 1329 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1330 const struct pci_device_id *, struct pci_dev *); 1331 extern int linux_pci_detach_device(struct pci_dev *); 1332 1333 static inline int 1334 pci_dev_present(const struct pci_device_id *cur) 1335 { 1336 while (cur != NULL && (cur->vendor || cur->device)) { 1337 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1338 return (1); 1339 } 1340 cur++; 1341 } 1342 return (0); 1343 } 1344 1345 static inline bool 1346 pci_dev_is_disconnected(const struct pci_dev *pdev) 1347 { 1348 pr_debug("TODO: %s\n", __func__); 1349 return (false); 1350 } 1351 1352 static inline const struct pci_device_id * 1353 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 1354 { 1355 if (ids == NULL) 1356 return (NULL); 1357 1358 for (; 1359 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0; 1360 ids++) 1361 if ((ids->vendor == PCI_ANY_ID || 1362 ids->vendor == pdev->vendor) && 1363 (ids->device == PCI_ANY_ID || 1364 ids->device == pdev->device) && 1365 (ids->subvendor == PCI_ANY_ID || 1366 ids->subvendor == pdev->subsystem_vendor) && 1367 (ids->subdevice == PCI_ANY_ID || 1368 ids->subdevice == pdev->subsystem_device) && 1369 ((ids->class ^ pdev->class) & ids->class_mask) == 0) 1370 return (ids); 1371 1372 return (NULL); 1373 } 1374 1375 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1376 unsigned int bus, unsigned int devfn); 1377 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1378 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1379 1380 struct pci_dev *lkpi_pci_get_slot(struct pci_bus *, unsigned int); 1381 #ifndef WANT_NATIVE_PCI_GET_SLOT 1382 #define pci_get_slot(_pbus, _devfn) \ 1383 lkpi_pci_get_slot(_pbus, _devfn) 1384 #endif 1385 1386 static inline int 1387 pci_domain_nr(struct pci_bus *pbus) 1388 { 1389 1390 return (pbus->domain); 1391 } 1392 1393 static inline int 1394 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1395 int pos, uint32_t *val, int len) 1396 { 1397 1398 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1399 return (0); 1400 } 1401 1402 static inline int 1403 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1404 { 1405 uint32_t tmp; 1406 int ret; 1407 1408 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1409 *val = (u16)tmp; 1410 return (ret); 1411 } 1412 1413 static inline int 1414 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1415 { 1416 uint32_t tmp; 1417 int ret; 1418 1419 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1420 *val = (u8)tmp; 1421 return (ret); 1422 } 1423 1424 static inline int 1425 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1426 uint32_t val, int size) 1427 { 1428 1429 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1430 return (0); 1431 } 1432 1433 static inline int 1434 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1435 uint8_t val) 1436 { 1437 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1438 } 1439 1440 static inline int 1441 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1442 uint16_t val) 1443 { 1444 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1445 } 1446 1447 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1448 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1449 struct pci_dev *lkpi_pci_get_base_class(unsigned int class, 1450 struct pci_dev *from); 1451 #define pci_get_base_class(class, from) lkpi_pci_get_base_class(class, from) 1452 1453 /* -------------------------------------------------------------------------- */ 1454 1455 #define pcim_enable_device(pdev) \ 1456 linuxkpi_pcim_enable_device(pdev) 1457 #define pcim_iomap_table(pdev) \ 1458 linuxkpi_pcim_iomap_table(pdev) 1459 #define pcim_iomap_regions(pdev, mask, name) \ 1460 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1461 1462 static inline int 1463 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1464 { 1465 uint32_t requests, req_mask; 1466 int bar, error; 1467 1468 /* Request all the BARs ("regions") we do not iomap. */ 1469 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1470 for (bar = requests = 0; requests != req_mask; bar++) { 1471 if ((req_mask & (1 << bar)) == 0) 1472 continue; 1473 error = pci_request_region(pdev, bar, name); 1474 if (error != 0 && error != -ENODEV) 1475 goto err; 1476 requests |= (1 << bar); 1477 } 1478 1479 error = pcim_iomap_regions(pdev, mask, name); 1480 if (error != 0) 1481 goto err; 1482 1483 return (0); 1484 1485 err: 1486 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1487 if ((requests & (1 << bar)) != 0) 1488 pci_release_region(pdev, bar); 1489 } 1490 1491 return (-EINVAL); 1492 } 1493 1494 /* 1495 * We cannot simply re-define pci_get_device() as we would normally do 1496 * and then hide it in linux_pci.c as too many semi-native drivers still 1497 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1498 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1499 */ 1500 static inline struct pci_dev * 1501 linuxkpi_pci_get_device(uint32_t vendor, uint32_t device, struct pci_dev *odev) 1502 { 1503 1504 return (lkpi_pci_get_device(vendor, device, odev)); 1505 } 1506 1507 #define for_each_pci_dev(_pdev) \ 1508 while ((_pdev = linuxkpi_pci_get_device(PCI_ANY_ID, PCI_ANY_ID, _pdev)) != NULL) 1509 1510 /* This is a FreeBSD extension so we can use bus_*(). */ 1511 static inline void 1512 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1513 { 1514 pdev->want_iomap_res = true; 1515 } 1516 1517 static inline bool 1518 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1519 { 1520 1521 return (false); 1522 } 1523 1524 static inline void * 1525 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1526 { 1527 1528 return (NULL); 1529 } 1530 1531 static inline void 1532 pci_ignore_hotplug(struct pci_dev *pdev) 1533 { 1534 } 1535 1536 static inline const char * 1537 pci_power_name(pci_power_t state) 1538 { 1539 int pstate = state + 1; 1540 1541 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1542 return (pci_power_names[pstate]); 1543 else 1544 return (pci_power_names[0]); 1545 } 1546 1547 static inline int 1548 pcie_get_readrq(struct pci_dev *dev) 1549 { 1550 u16 ctl; 1551 1552 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1553 return (-EINVAL); 1554 1555 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1556 } 1557 1558 static inline bool 1559 pci_is_enabled(struct pci_dev *pdev) 1560 { 1561 1562 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1563 PCIM_CMD_BUSMASTEREN) != 0); 1564 } 1565 1566 static inline int 1567 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1568 { 1569 1570 return (0); 1571 } 1572 1573 static inline int 1574 pci_assign_resource(struct pci_dev *pdev, int bar) 1575 { 1576 1577 return (0); 1578 } 1579 1580 static inline int 1581 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1582 { 1583 1584 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1585 if (vector != 0) 1586 return (-EINVAL); 1587 return (pdev->irq); 1588 } 1589 1590 if (pdev->msix_enabled || pdev->msi_enabled) { 1591 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1592 return (-EINVAL); 1593 return (pdev->dev.irq_start + vector); 1594 } 1595 1596 return (-ENXIO); 1597 } 1598 1599 static inline int 1600 pci_msix_vec_count(struct pci_dev *pdev) 1601 { 1602 int avail; 1603 1604 avail = pci_msix_count(pdev->dev.bsddev); 1605 if (avail == 0) 1606 return (-EINVAL); 1607 return (avail); 1608 } 1609 1610 static inline int 1611 pci_wake_from_d3(struct pci_dev *pdev, bool enable) 1612 { 1613 1614 pr_debug("%s: TODO\n", __func__); 1615 return (0); 1616 } 1617 1618 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1619