1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/nv.h> 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <asm/memtype.h> 61 #include <linux/device.h> 62 #include <linux/pci_ids.h> 63 #include <linux/pm.h> 64 65 struct pci_device_id { 66 uint32_t vendor; 67 uint32_t device; 68 uint32_t subvendor; 69 uint32_t subdevice; 70 uint32_t class; 71 uint32_t class_mask; 72 uintptr_t driver_data; 73 }; 74 75 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 76 #define MODULE_DEVICE_TABLE(_bus, _table) \ 77 \ 78 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 79 DEVMETHOD_END \ 80 }; \ 81 \ 82 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 83 "lkpi_" #_bus #_table, \ 84 _ ## _bus ## _ ## _table ## _methods, \ 85 0 \ 86 }; \ 87 \ 88 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 89 0, 0); \ 90 \ 91 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 92 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 93 94 #define PCI_ANY_ID -1U 95 96 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 97 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 98 #define PCI_FUNC(devfn) ((devfn) & 0x07) 99 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 100 101 #define PCI_VDEVICE(_vendor, _device) \ 102 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 103 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 104 #define PCI_DEVICE(_vendor, _device) \ 105 .vendor = (_vendor), .device = (_device), \ 106 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 107 108 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 109 110 #define PCI_STD_NUM_BARS 6 111 #define PCI_VENDOR_ID PCIR_VENDOR 112 #define PCI_DEVICE_ID PCIR_DEVICE 113 #define PCI_COMMAND PCIR_COMMAND 114 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 115 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 116 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 117 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 118 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 119 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 120 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 121 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 122 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 123 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 124 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 125 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 126 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 127 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 128 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 129 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 130 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 131 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 132 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 133 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 134 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 135 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 136 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 137 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 138 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 139 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 140 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 141 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 142 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 143 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 144 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 145 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 146 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 147 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 148 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 149 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 150 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 151 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 152 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 153 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 154 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 155 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 156 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 157 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 158 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 159 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 160 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 161 #define PCI_EXP_LNKCTL2_TLS 0x000f 162 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 163 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 164 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 165 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 166 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 167 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 168 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 169 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 170 171 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 172 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 173 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 174 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 175 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 176 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 177 178 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 179 #define PCI_EXP_DEVSTA_TRPND 0x0020 180 181 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 182 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 183 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 184 185 enum pci_bus_speed { 186 PCI_SPEED_UNKNOWN = -1, 187 PCIE_SPEED_2_5GT, 188 PCIE_SPEED_5_0GT, 189 PCIE_SPEED_8_0GT, 190 PCIE_SPEED_16_0GT, 191 PCIE_SPEED_32_0GT, 192 PCIE_SPEED_64_0GT, 193 }; 194 195 enum pcie_link_width { 196 PCIE_LNK_WIDTH_RESRV = 0x00, 197 PCIE_LNK_X1 = 0x01, 198 PCIE_LNK_X2 = 0x02, 199 PCIE_LNK_X4 = 0x04, 200 PCIE_LNK_X8 = 0x08, 201 PCIE_LNK_X12 = 0x0c, 202 PCIE_LNK_X16 = 0x10, 203 PCIE_LNK_X32 = 0x20, 204 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 205 }; 206 207 #define PCIE_LINK_STATE_L0S 0x00000001 208 #define PCIE_LINK_STATE_L1 0x00000002 209 #define PCIE_LINK_STATE_CLKPM 0x00000004 210 211 typedef int pci_power_t; 212 213 #define PCI_D0 PCI_POWERSTATE_D0 214 #define PCI_D1 PCI_POWERSTATE_D1 215 #define PCI_D2 PCI_POWERSTATE_D2 216 #define PCI_D3hot PCI_POWERSTATE_D3 217 #define PCI_D3cold 4 218 219 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 220 221 extern const char *pci_power_names[6]; 222 223 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 224 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 225 226 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 227 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 228 229 #define PCI_L1SS_CTL1 0x8 230 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 231 232 #define PCI_IRQ_LEGACY 0x01 233 #define PCI_IRQ_MSI 0x02 234 #define PCI_IRQ_MSIX 0x04 235 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 236 237 struct pci_dev; 238 239 struct pci_driver { 240 struct list_head node; 241 char *name; 242 const struct pci_device_id *id_table; 243 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 244 void (*remove)(struct pci_dev *dev); 245 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 246 int (*resume) (struct pci_dev *dev); /* Device woken up */ 247 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 248 driver_t bsddriver; 249 devclass_t bsdclass; 250 struct device_driver driver; 251 const struct pci_error_handlers *err_handler; 252 bool isdrm; 253 int bsd_probe_return; 254 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 255 const nvlist_t *pf_config); 256 void (*bsd_iov_uninit)(device_t dev); 257 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 258 const nvlist_t *vf_config); 259 }; 260 261 struct pci_bus { 262 struct pci_dev *self; 263 /* struct pci_bus *parent */ 264 int domain; 265 int number; 266 }; 267 268 extern struct list_head pci_drivers; 269 extern struct list_head pci_devices; 270 extern spinlock_t pci_lock; 271 272 #define __devexit_p(x) x 273 274 #define module_pci_driver(_driver) \ 275 \ 276 static inline int \ 277 _pci_init(void) \ 278 { \ 279 \ 280 return (linux_pci_register_driver(&_driver)); \ 281 } \ 282 \ 283 static inline void \ 284 _pci_exit(void) \ 285 { \ 286 \ 287 linux_pci_unregister_driver(&_driver); \ 288 } \ 289 \ 290 module_init(_pci_init); \ 291 module_exit(_pci_exit) 292 293 struct msi_msg { 294 uint32_t data; 295 }; 296 297 struct msi_desc { 298 struct msi_msg msg; 299 struct { 300 bool is_64; 301 } msi_attrib; 302 }; 303 304 /* 305 * If we find drivers accessing this from multiple KPIs we may have to 306 * refcount objects of this structure. 307 */ 308 struct pci_mmio_region { 309 TAILQ_ENTRY(pci_mmio_region) next; 310 struct resource *res; 311 int rid; 312 int type; 313 }; 314 315 struct pci_dev { 316 struct device dev; 317 struct list_head links; 318 struct pci_driver *pdrv; 319 struct pci_bus *bus; 320 struct pci_dev *root; 321 pci_power_t current_state; 322 uint16_t device; 323 uint16_t vendor; 324 uint16_t subsystem_vendor; 325 uint16_t subsystem_device; 326 unsigned int irq; 327 unsigned int devfn; 328 uint32_t class; 329 uint8_t revision; 330 uint8_t msi_cap; 331 uint8_t msix_cap; 332 bool managed; /* devres "pcim_*(). */ 333 bool want_iomap_res; 334 bool msi_enabled; 335 bool msix_enabled; 336 phys_addr_t rom; 337 size_t romlen; 338 struct msi_desc **msi_desc; 339 char *path_name; 340 341 TAILQ_HEAD(, pci_mmio_region) mmio; 342 }; 343 344 /* We need some meta-struct to keep track of these for devres. */ 345 struct pci_devres { 346 bool enable_io; 347 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 348 uint8_t region_mask; 349 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 350 }; 351 struct pcim_iomap_devres { 352 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 353 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 354 }; 355 356 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 357 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 358 unsigned int flags); 359 bool pci_device_is_present(struct pci_dev *pdev); 360 361 /* Internal helper function(s). */ 362 struct pci_dev *lkpinew_pci_dev(device_t); 363 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev); 364 void lkpi_pci_devres_release(struct device *, void *); 365 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size); 366 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev); 367 void lkpi_pcim_iomap_table_release(struct device *, void *); 368 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 369 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 370 371 static inline bool 372 dev_is_pci(struct device *dev) 373 { 374 375 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 376 } 377 378 static inline int 379 pci_resource_type(struct pci_dev *pdev, int bar) 380 { 381 struct pci_map *pm; 382 383 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 384 if (!pm) 385 return (-1); 386 387 if (PCI_BAR_IO(pm->pm_value)) 388 return (SYS_RES_IOPORT); 389 else 390 return (SYS_RES_MEMORY); 391 } 392 393 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 394 struct resource_list *rl, int type, int rid); 395 396 static inline struct resource_list_entry * 397 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 398 { 399 struct pci_devinfo *dinfo; 400 struct resource_list *rl; 401 struct resource_list_entry *rle; 402 403 dinfo = device_get_ivars(pdev->dev.bsddev); 404 rl = &dinfo->resources; 405 rle = resource_list_find(rl, type, rid); 406 /* Reserve resources for this BAR if needed. */ 407 if (rle == NULL && reserve_bar) 408 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 409 return (rle); 410 } 411 412 static inline struct resource_list_entry * 413 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 414 { 415 int type; 416 417 type = pci_resource_type(pdev, bar); 418 if (type < 0) 419 return (NULL); 420 bar = PCIR_BAR(bar); 421 return (linux_pci_get_rle(pdev, type, bar, reserve)); 422 } 423 424 static inline struct device * 425 linux_pci_find_irq_dev(unsigned int irq) 426 { 427 struct pci_dev *pdev; 428 struct device *found; 429 430 found = NULL; 431 spin_lock(&pci_lock); 432 list_for_each_entry(pdev, &pci_devices, links) { 433 if (irq == pdev->dev.irq || 434 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 435 found = &pdev->dev; 436 break; 437 } 438 } 439 spin_unlock(&pci_lock); 440 return (found); 441 } 442 443 /* 444 * All drivers just seem to want to inspect the type not flags. 445 */ 446 static inline int 447 pci_resource_flags(struct pci_dev *pdev, int bar) 448 { 449 int type; 450 451 type = pci_resource_type(pdev, bar); 452 if (type < 0) 453 return (0); 454 return (1 << type); 455 } 456 457 static inline const char * 458 pci_name(struct pci_dev *d) 459 { 460 return d->path_name; 461 } 462 463 static inline void * 464 pci_get_drvdata(struct pci_dev *pdev) 465 { 466 467 return dev_get_drvdata(&pdev->dev); 468 } 469 470 static inline void 471 pci_set_drvdata(struct pci_dev *pdev, void *data) 472 { 473 474 dev_set_drvdata(&pdev->dev, data); 475 } 476 477 static inline struct pci_dev * 478 pci_dev_get(struct pci_dev *pdev) 479 { 480 481 if (pdev != NULL) 482 get_device(&pdev->dev); 483 return (pdev); 484 } 485 486 static __inline void 487 pci_dev_put(struct pci_dev *pdev) 488 { 489 490 if (pdev != NULL) 491 put_device(&pdev->dev); 492 } 493 494 static inline int 495 pci_enable_device(struct pci_dev *pdev) 496 { 497 498 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 499 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 500 return (0); 501 } 502 503 static inline void 504 pci_disable_device(struct pci_dev *pdev) 505 { 506 507 pci_disable_busmaster(pdev->dev.bsddev); 508 } 509 510 static inline int 511 pci_set_master(struct pci_dev *pdev) 512 { 513 514 pci_enable_busmaster(pdev->dev.bsddev); 515 return (0); 516 } 517 518 static inline int 519 pci_set_power_state(struct pci_dev *pdev, int state) 520 { 521 522 pci_set_powerstate(pdev->dev.bsddev, state); 523 return (0); 524 } 525 526 static inline int 527 pci_clear_master(struct pci_dev *pdev) 528 { 529 530 pci_disable_busmaster(pdev->dev.bsddev); 531 return (0); 532 } 533 534 static inline bool 535 pci_is_root_bus(struct pci_bus *pbus) 536 { 537 538 return (pbus->self == NULL); 539 } 540 541 static inline struct pci_dev * 542 pci_upstream_bridge(struct pci_dev *pdev) 543 { 544 545 if (pci_is_root_bus(pdev->bus)) 546 return (NULL); 547 548 /* 549 * If we do not have a (proper) "upstream bridge" set, e.g., we point 550 * to ourselves, try to handle this case on the fly like we do 551 * for pcie_find_root_port(). 552 */ 553 if (pdev == pdev->bus->self) { 554 device_t bridge; 555 556 bridge = device_get_parent(pdev->dev.bsddev); 557 if (bridge == NULL) 558 goto done; 559 bridge = device_get_parent(bridge); 560 if (bridge == NULL) 561 goto done; 562 if (device_get_devclass(device_get_parent(bridge)) != 563 devclass_find("pci")) 564 goto done; 565 566 /* 567 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 568 * for it so it can be returned. 569 */ 570 pdev->bus->self = lkpinew_pci_dev(bridge); 571 } 572 done: 573 return (pdev->bus->self); 574 } 575 576 static inline struct pci_devres * 577 lkpi_pci_devres_find(struct pci_dev *pdev) 578 { 579 580 if (!pdev->managed) 581 return (NULL); 582 583 return (lkpi_pci_devres_get_alloc(pdev)); 584 } 585 586 static inline void 587 pci_release_region(struct pci_dev *pdev, int bar) 588 { 589 struct resource_list_entry *rle; 590 struct pci_devres *dr; 591 struct pci_mmio_region *mmio, *p; 592 593 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 594 return; 595 596 /* 597 * As we implicitly track the requests we also need to clear them on 598 * release. Do clear before resource release. 599 */ 600 dr = lkpi_pci_devres_find(pdev); 601 if (dr != NULL) { 602 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 603 " region_table res %p != rel->res %p\n", __func__, pdev, 604 bar, dr->region_table[bar], rle->res)); 605 dr->region_table[bar] = NULL; 606 dr->region_mask &= ~(1 << bar); 607 } 608 609 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 610 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 611 continue; 612 TAILQ_REMOVE(&pdev->mmio, mmio, next); 613 free(mmio, M_DEVBUF); 614 } 615 616 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 617 } 618 619 static inline void 620 pci_release_regions(struct pci_dev *pdev) 621 { 622 int i; 623 624 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 625 pci_release_region(pdev, i); 626 } 627 628 static inline int 629 pci_request_regions(struct pci_dev *pdev, const char *res_name) 630 { 631 int error; 632 int i; 633 634 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 635 error = pci_request_region(pdev, i, res_name); 636 if (error && error != -ENODEV) { 637 pci_release_regions(pdev); 638 return (error); 639 } 640 } 641 return (0); 642 } 643 644 static inline void 645 lkpi_pci_disable_msix(struct pci_dev *pdev) 646 { 647 648 pci_release_msi(pdev->dev.bsddev); 649 650 /* 651 * The MSIX IRQ numbers associated with this PCI device are no 652 * longer valid and might be re-assigned. Make sure 653 * linux_pci_find_irq_dev() does no longer see them by 654 * resetting their references to zero: 655 */ 656 pdev->dev.irq_start = 0; 657 pdev->dev.irq_end = 0; 658 pdev->msix_enabled = false; 659 } 660 /* Only for consistency. No conflict on that one. */ 661 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 662 663 static inline void 664 lkpi_pci_disable_msi(struct pci_dev *pdev) 665 { 666 667 pci_release_msi(pdev->dev.bsddev); 668 669 pdev->dev.irq_start = 0; 670 pdev->dev.irq_end = 0; 671 pdev->irq = pdev->dev.irq; 672 pdev->msi_enabled = false; 673 } 674 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 675 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 676 677 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 678 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 679 680 static inline bus_addr_t 681 pci_bus_address(struct pci_dev *pdev, int bar) 682 { 683 684 return (pci_resource_start(pdev, bar)); 685 } 686 687 #define PCI_CAP_ID_EXP PCIY_EXPRESS 688 #define PCI_CAP_ID_PCIX PCIY_PCIX 689 #define PCI_CAP_ID_AGP PCIY_AGP 690 #define PCI_CAP_ID_PM PCIY_PMG 691 692 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 693 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 694 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 695 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 696 #define PCI_EXP_LNKSTA PCIER_LINK_STA 697 698 static inline int 699 pci_find_capability(struct pci_dev *pdev, int capid) 700 { 701 int reg; 702 703 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 704 return (0); 705 return (reg); 706 } 707 708 static inline int pci_pcie_cap(struct pci_dev *dev) 709 { 710 return pci_find_capability(dev, PCI_CAP_ID_EXP); 711 } 712 713 static inline int 714 pci_find_ext_capability(struct pci_dev *pdev, int capid) 715 { 716 int reg; 717 718 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 719 return (0); 720 return (reg); 721 } 722 723 #define PCIM_PCAP_PME_SHIFT 11 724 static __inline bool 725 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 726 { 727 struct pci_devinfo *dinfo; 728 pcicfgregs *cfg; 729 730 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 731 return (false); 732 733 dinfo = device_get_ivars(pdev->dev.bsddev); 734 cfg = &dinfo->cfg; 735 736 if (cfg->pp.pp_cap == 0) 737 return (false); 738 739 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 740 return (true); 741 742 return (false); 743 } 744 745 static inline int 746 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 747 { 748 749 if (!pci_enable_aspm) 750 return (-EPERM); 751 752 return (-ENXIO); 753 } 754 755 static inline int 756 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 757 { 758 759 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 760 return (0); 761 } 762 763 static inline int 764 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 765 { 766 767 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 768 return (0); 769 } 770 771 static inline int 772 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 773 { 774 775 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 776 return (0); 777 } 778 779 static inline int 780 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 781 { 782 783 pci_write_config(pdev->dev.bsddev, where, val, 1); 784 return (0); 785 } 786 787 static inline int 788 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 789 { 790 791 pci_write_config(pdev->dev.bsddev, where, val, 2); 792 return (0); 793 } 794 795 static inline int 796 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 797 { 798 799 pci_write_config(pdev->dev.bsddev, where, val, 4); 800 return (0); 801 } 802 803 int linux_pci_register_driver(struct pci_driver *pdrv); 804 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 805 void linux_pci_unregister_driver(struct pci_driver *pdrv); 806 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 807 808 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 809 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 810 811 struct msix_entry { 812 int entry; 813 int vector; 814 }; 815 816 /* 817 * Enable msix, positive errors indicate actual number of available 818 * vectors. Negative errors are failures. 819 * 820 * NB: define added to prevent this definition of pci_enable_msix from 821 * clashing with the native FreeBSD version. 822 */ 823 #define pci_enable_msix(...) \ 824 linux_pci_enable_msix(__VA_ARGS__) 825 826 static inline int 827 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 828 { 829 struct resource_list_entry *rle; 830 int error; 831 int avail; 832 int i; 833 834 avail = pci_msix_count(pdev->dev.bsddev); 835 if (avail < nreq) { 836 if (avail == 0) 837 return -EINVAL; 838 return avail; 839 } 840 avail = nreq; 841 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 842 return error; 843 /* 844 * Handle case where "pci_alloc_msix()" may allocate less 845 * interrupts than available and return with no error: 846 */ 847 if (avail < nreq) { 848 pci_release_msi(pdev->dev.bsddev); 849 return avail; 850 } 851 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 852 pdev->dev.irq_start = rle->start; 853 pdev->dev.irq_end = rle->start + avail; 854 for (i = 0; i < nreq; i++) 855 entries[i].vector = pdev->dev.irq_start + i; 856 pdev->msix_enabled = true; 857 return (0); 858 } 859 860 #define pci_enable_msix_range(...) \ 861 linux_pci_enable_msix_range(__VA_ARGS__) 862 863 static inline int 864 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 865 int minvec, int maxvec) 866 { 867 int nvec = maxvec; 868 int rc; 869 870 if (maxvec < minvec) 871 return (-ERANGE); 872 873 do { 874 rc = pci_enable_msix(dev, entries, nvec); 875 if (rc < 0) { 876 return (rc); 877 } else if (rc > 0) { 878 if (rc < minvec) 879 return (-ENOSPC); 880 nvec = rc; 881 } 882 } while (rc); 883 return (nvec); 884 } 885 886 #define pci_enable_msi(pdev) \ 887 linux_pci_enable_msi(pdev) 888 889 static inline int 890 _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec) 891 { 892 struct resource_list_entry *rle; 893 int error; 894 int nvec; 895 896 if (maxvec < minvec) 897 return (-EINVAL); 898 899 nvec = pci_msi_count(pdev->dev.bsddev); 900 if (nvec < 1 || nvec < minvec) 901 return (-ENOSPC); 902 903 nvec = min(nvec, maxvec); 904 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &nvec)) != 0) 905 return error; 906 907 /* Native PCI might only ever ask for 32 vectors. */ 908 if (nvec < minvec) { 909 pci_release_msi(pdev->dev.bsddev); 910 return (-ENOSPC); 911 } 912 913 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 914 pdev->dev.irq_start = rle->start; 915 pdev->dev.irq_end = rle->start + nvec; 916 pdev->irq = rle->start; 917 pdev->msi_enabled = true; 918 return (0); 919 } 920 921 static inline int 922 pci_enable_msi(struct pci_dev *pdev) 923 { 924 925 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 926 } 927 928 static inline int 929 pci_channel_offline(struct pci_dev *pdev) 930 { 931 932 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 933 } 934 935 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 936 { 937 return -ENODEV; 938 } 939 940 static inline void pci_disable_sriov(struct pci_dev *dev) 941 { 942 } 943 944 static inline void * 945 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 946 { 947 struct resource *res; 948 949 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 950 if (res == NULL) 951 return (NULL); 952 /* This is a FreeBSD extension so we can use bus_*(). */ 953 if (pdev->want_iomap_res) 954 return (res); 955 return ((void *)rman_get_bushandle(res)); 956 } 957 958 static inline void 959 pci_iounmap(struct pci_dev *pdev, void *res) 960 { 961 struct pci_mmio_region *mmio, *p; 962 963 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 964 if (res != (void *)rman_get_bushandle(mmio->res)) 965 continue; 966 bus_release_resource(pdev->dev.bsddev, 967 mmio->type, mmio->rid, mmio->res); 968 TAILQ_REMOVE(&pdev->mmio, mmio, next); 969 free(mmio, M_DEVBUF); 970 return; 971 } 972 } 973 974 static inline void 975 lkpi_pci_save_state(struct pci_dev *pdev) 976 { 977 978 pci_save_state(pdev->dev.bsddev); 979 } 980 981 static inline void 982 lkpi_pci_restore_state(struct pci_dev *pdev) 983 { 984 985 pci_restore_state(pdev->dev.bsddev); 986 } 987 988 #define pci_save_state(dev) lkpi_pci_save_state(dev) 989 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 990 991 static inline int 992 pci_reset_function(struct pci_dev *pdev) 993 { 994 995 return (-ENOSYS); 996 } 997 998 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 999 const struct pci_device_id _table[] __devinitdata 1000 1001 /* XXX This should not be necessary. */ 1002 #define pcix_set_mmrbc(d, v) 0 1003 #define pcix_get_max_mmrbc(d) 0 1004 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 1005 1006 #define PCI_DMA_BIDIRECTIONAL 0 1007 #define PCI_DMA_TODEVICE 1 1008 #define PCI_DMA_FROMDEVICE 2 1009 #define PCI_DMA_NONE 3 1010 1011 #define pci_pool dma_pool 1012 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 1013 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 1014 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 1015 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 1016 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 1017 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 1018 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1019 _size, _vaddr, _dma_handle) 1020 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 1021 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1022 _sg, _nents, (enum dma_data_direction)_dir) 1023 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 1024 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1025 (_ptr), (_size), (enum dma_data_direction)_dir) 1026 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 1027 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1028 _addr, _size, (enum dma_data_direction)_dir) 1029 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 1030 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1031 _sg, _nents, (enum dma_data_direction)_dir) 1032 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 1033 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 1034 _offset, _size, (enum dma_data_direction)_dir) 1035 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 1036 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1037 _dma_address, _size, (enum dma_data_direction)_dir) 1038 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1039 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1040 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1041 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1042 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1043 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1044 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1045 #define pci_unmap_addr dma_unmap_addr 1046 #define pci_unmap_addr_set dma_unmap_addr_set 1047 #define pci_unmap_len dma_unmap_len 1048 #define pci_unmap_len_set dma_unmap_len_set 1049 1050 typedef unsigned int __bitwise pci_channel_state_t; 1051 typedef unsigned int __bitwise pci_ers_result_t; 1052 1053 enum pci_channel_state { 1054 pci_channel_io_normal = 1, 1055 pci_channel_io_frozen = 2, 1056 pci_channel_io_perm_failure = 3, 1057 }; 1058 1059 enum pci_ers_result { 1060 PCI_ERS_RESULT_NONE = 1, 1061 PCI_ERS_RESULT_CAN_RECOVER = 2, 1062 PCI_ERS_RESULT_NEED_RESET = 3, 1063 PCI_ERS_RESULT_DISCONNECT = 4, 1064 PCI_ERS_RESULT_RECOVERED = 5, 1065 }; 1066 1067 /* PCI bus error event callbacks */ 1068 struct pci_error_handlers { 1069 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1070 enum pci_channel_state error); 1071 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1072 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1073 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1074 void (*resume)(struct pci_dev *dev); 1075 }; 1076 1077 /* FreeBSD does not support SRIOV - yet */ 1078 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1079 { 1080 return dev; 1081 } 1082 1083 static inline bool pci_is_pcie(struct pci_dev *dev) 1084 { 1085 return !!pci_pcie_cap(dev); 1086 } 1087 1088 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1089 { 1090 int pos; 1091 u16 reg16; 1092 1093 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1094 if (!pos) 1095 return 0; 1096 1097 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1098 1099 return reg16; 1100 } 1101 1102 static inline int pci_pcie_type(struct pci_dev *dev) 1103 { 1104 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1105 } 1106 1107 static inline int pcie_cap_version(struct pci_dev *dev) 1108 { 1109 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1110 } 1111 1112 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1113 { 1114 int type = pci_pcie_type(dev); 1115 1116 return pcie_cap_version(dev) > 1 || 1117 type == PCI_EXP_TYPE_ROOT_PORT || 1118 type == PCI_EXP_TYPE_ENDPOINT || 1119 type == PCI_EXP_TYPE_LEG_END; 1120 } 1121 1122 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1123 { 1124 return true; 1125 } 1126 1127 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1128 { 1129 int type = pci_pcie_type(dev); 1130 1131 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1132 (type == PCI_EXP_TYPE_DOWNSTREAM && 1133 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1134 } 1135 1136 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1137 { 1138 int type = pci_pcie_type(dev); 1139 1140 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1141 type == PCI_EXP_TYPE_RC_EC; 1142 } 1143 1144 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1145 { 1146 if (!pci_is_pcie(dev)) 1147 return false; 1148 1149 switch (pos) { 1150 case PCI_EXP_FLAGS_TYPE: 1151 return true; 1152 case PCI_EXP_DEVCAP: 1153 case PCI_EXP_DEVCTL: 1154 case PCI_EXP_DEVSTA: 1155 return pcie_cap_has_devctl(dev); 1156 case PCI_EXP_LNKCAP: 1157 case PCI_EXP_LNKCTL: 1158 case PCI_EXP_LNKSTA: 1159 return pcie_cap_has_lnkctl(dev); 1160 case PCI_EXP_SLTCAP: 1161 case PCI_EXP_SLTCTL: 1162 case PCI_EXP_SLTSTA: 1163 return pcie_cap_has_sltctl(dev); 1164 case PCI_EXP_RTCTL: 1165 case PCI_EXP_RTCAP: 1166 case PCI_EXP_RTSTA: 1167 return pcie_cap_has_rtctl(dev); 1168 case PCI_EXP_DEVCAP2: 1169 case PCI_EXP_DEVCTL2: 1170 case PCI_EXP_LNKCAP2: 1171 case PCI_EXP_LNKCTL2: 1172 case PCI_EXP_LNKSTA2: 1173 return pcie_cap_version(dev) > 1; 1174 default: 1175 return false; 1176 } 1177 } 1178 1179 static inline int 1180 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1181 { 1182 *dst = 0; 1183 if (pos & 3) 1184 return -EINVAL; 1185 1186 if (!pcie_capability_reg_implemented(dev, pos)) 1187 return -EINVAL; 1188 1189 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1190 } 1191 1192 static inline int 1193 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1194 { 1195 *dst = 0; 1196 if (pos & 3) 1197 return -EINVAL; 1198 1199 if (!pcie_capability_reg_implemented(dev, pos)) 1200 return -EINVAL; 1201 1202 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1203 } 1204 1205 static inline int 1206 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1207 { 1208 if (pos & 1) 1209 return -EINVAL; 1210 1211 if (!pcie_capability_reg_implemented(dev, pos)) 1212 return 0; 1213 1214 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1215 } 1216 1217 static inline int 1218 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1219 { 1220 int error; 1221 uint16_t v; 1222 1223 error = pcie_capability_read_word(dev, pos, &v); 1224 if (error != 0) 1225 return (error); 1226 1227 v |= val; 1228 1229 error = pcie_capability_write_word(dev, pos, v); 1230 return (error); 1231 } 1232 1233 static inline int 1234 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1235 { 1236 int error; 1237 uint16_t v; 1238 1239 error = pcie_capability_read_word(dev, pos, &v); 1240 if (error != 0) 1241 return (error); 1242 1243 v &= ~val; 1244 1245 error = pcie_capability_write_word(dev, pos, v); 1246 return (error); 1247 } 1248 1249 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1250 enum pci_bus_speed *speed, enum pcie_link_width *width) 1251 { 1252 *speed = PCI_SPEED_UNKNOWN; 1253 *width = PCIE_LNK_WIDTH_UNKNOWN; 1254 return (0); 1255 } 1256 1257 static inline int 1258 pci_num_vf(struct pci_dev *dev) 1259 { 1260 return (0); 1261 } 1262 1263 static inline enum pci_bus_speed 1264 pcie_get_speed_cap(struct pci_dev *dev) 1265 { 1266 device_t root; 1267 uint32_t lnkcap, lnkcap2; 1268 int error, pos; 1269 1270 root = device_get_parent(dev->dev.bsddev); 1271 if (root == NULL) 1272 return (PCI_SPEED_UNKNOWN); 1273 root = device_get_parent(root); 1274 if (root == NULL) 1275 return (PCI_SPEED_UNKNOWN); 1276 root = device_get_parent(root); 1277 if (root == NULL) 1278 return (PCI_SPEED_UNKNOWN); 1279 1280 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1281 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1282 return (PCI_SPEED_UNKNOWN); 1283 1284 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1285 return (PCI_SPEED_UNKNOWN); 1286 1287 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1288 1289 if (lnkcap2) { /* PCIe r3.0-compliant */ 1290 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1291 return (PCIE_SPEED_2_5GT); 1292 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1293 return (PCIE_SPEED_5_0GT); 1294 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1295 return (PCIE_SPEED_8_0GT); 1296 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1297 return (PCIE_SPEED_16_0GT); 1298 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1299 return (PCIE_SPEED_32_0GT); 1300 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1301 return (PCIE_SPEED_64_0GT); 1302 } else { /* pre-r3.0 */ 1303 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1304 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1305 return (PCIE_SPEED_2_5GT); 1306 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1307 return (PCIE_SPEED_5_0GT); 1308 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1309 return (PCIE_SPEED_8_0GT); 1310 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1311 return (PCIE_SPEED_16_0GT); 1312 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1313 return (PCIE_SPEED_32_0GT); 1314 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1315 return (PCIE_SPEED_64_0GT); 1316 } 1317 return (PCI_SPEED_UNKNOWN); 1318 } 1319 1320 static inline enum pcie_link_width 1321 pcie_get_width_cap(struct pci_dev *dev) 1322 { 1323 uint32_t lnkcap; 1324 1325 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1326 if (lnkcap) 1327 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1328 1329 return (PCIE_LNK_WIDTH_UNKNOWN); 1330 } 1331 1332 static inline int 1333 pcie_get_mps(struct pci_dev *dev) 1334 { 1335 return (pci_get_max_payload(dev->dev.bsddev)); 1336 } 1337 1338 static inline uint32_t 1339 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1340 { 1341 1342 switch(spd) { 1343 case PCIE_SPEED_64_0GT: 1344 return (64000 * 128 / 130); 1345 case PCIE_SPEED_32_0GT: 1346 return (32000 * 128 / 130); 1347 case PCIE_SPEED_16_0GT: 1348 return (16000 * 128 / 130); 1349 case PCIE_SPEED_8_0GT: 1350 return (8000 * 128 / 130); 1351 case PCIE_SPEED_5_0GT: 1352 return (5000 * 8 / 10); 1353 case PCIE_SPEED_2_5GT: 1354 return (2500 * 8 / 10); 1355 default: 1356 return (0); 1357 } 1358 } 1359 1360 static inline uint32_t 1361 pcie_bandwidth_available(struct pci_dev *pdev, 1362 struct pci_dev **limiting, 1363 enum pci_bus_speed *speed, 1364 enum pcie_link_width *width) 1365 { 1366 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1367 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1368 1369 if (speed) 1370 *speed = nspeed; 1371 if (width) 1372 *width = nwidth; 1373 1374 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1375 } 1376 1377 static inline bool 1378 pcie_aspm_enabled(struct pci_dev *pdev) 1379 { 1380 return (false); 1381 } 1382 1383 static inline struct pci_dev * 1384 pcie_find_root_port(struct pci_dev *pdev) 1385 { 1386 device_t root; 1387 1388 if (pdev->root != NULL) 1389 return (pdev->root); 1390 1391 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1392 if (root == NULL) 1393 return (NULL); 1394 1395 pdev->root = lkpinew_pci_dev(root); 1396 return (pdev->root); 1397 } 1398 1399 /* This is needed when people rip out the device "HotPlug". */ 1400 static inline void 1401 pci_lock_rescan_remove(void) 1402 { 1403 } 1404 1405 static inline void 1406 pci_unlock_rescan_remove(void) 1407 { 1408 } 1409 1410 static __inline void 1411 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1412 { 1413 } 1414 1415 static inline int 1416 pci_rescan_bus(struct pci_bus *pbus) 1417 { 1418 device_t *devlist, parent; 1419 int devcount, error; 1420 1421 if (!device_is_attached(pbus->self->dev.bsddev)) 1422 return (0); 1423 /* pci_rescan_method() will work on the pcib (parent). */ 1424 error = BUS_RESCAN(pbus->self->dev.bsddev); 1425 if (error != 0) 1426 return (0); 1427 1428 parent = device_get_parent(pbus->self->dev.bsddev); 1429 error = device_get_children(parent, &devlist, &devcount); 1430 if (error != 0) 1431 return (0); 1432 if (devcount != 0) 1433 free(devlist, M_TEMP); 1434 1435 return (devcount); 1436 } 1437 1438 /* 1439 * The following functions can be used to attach/detach the LinuxKPI's 1440 * PCI device runtime. The pci_driver and pci_device_id pointer is 1441 * allowed to be NULL. Other pointers must be all valid. 1442 * The pci_dev structure should be zero-initialized before passed 1443 * to the linux_pci_attach_device function. 1444 */ 1445 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1446 const struct pci_device_id *, struct pci_dev *); 1447 extern int linux_pci_detach_device(struct pci_dev *); 1448 1449 static inline int 1450 pci_dev_present(const struct pci_device_id *cur) 1451 { 1452 while (cur != NULL && (cur->vendor || cur->device)) { 1453 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1454 return (1); 1455 } 1456 cur++; 1457 } 1458 return (0); 1459 } 1460 1461 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1462 unsigned int bus, unsigned int devfn); 1463 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1464 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1465 1466 static inline int 1467 pci_domain_nr(struct pci_bus *pbus) 1468 { 1469 1470 return (pbus->domain); 1471 } 1472 1473 static inline int 1474 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1475 int pos, uint32_t *val, int len) 1476 { 1477 1478 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1479 return (0); 1480 } 1481 1482 static inline int 1483 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1484 { 1485 uint32_t tmp; 1486 int ret; 1487 1488 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1489 *val = (u16)tmp; 1490 return (ret); 1491 } 1492 1493 static inline int 1494 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1495 { 1496 uint32_t tmp; 1497 int ret; 1498 1499 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1500 *val = (u8)tmp; 1501 return (ret); 1502 } 1503 1504 static inline int 1505 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1506 uint32_t val, int size) 1507 { 1508 1509 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1510 return (0); 1511 } 1512 1513 static inline int 1514 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1515 uint8_t val) 1516 { 1517 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1518 } 1519 1520 static inline int 1521 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1522 uint16_t val) 1523 { 1524 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1525 } 1526 1527 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1528 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1529 1530 /* -------------------------------------------------------------------------- */ 1531 1532 static inline int 1533 pcim_enable_device(struct pci_dev *pdev) 1534 { 1535 struct pci_devres *dr; 1536 int error; 1537 1538 /* Here we cannot run through the pdev->managed check. */ 1539 dr = lkpi_pci_devres_get_alloc(pdev); 1540 if (dr == NULL) 1541 return (-ENOMEM); 1542 1543 /* If resources were enabled before do not do it again. */ 1544 if (dr->enable_io) 1545 return (0); 1546 1547 error = pci_enable_device(pdev); 1548 if (error == 0) 1549 dr->enable_io = true; 1550 1551 /* This device is not managed. */ 1552 pdev->managed = true; 1553 1554 return (error); 1555 } 1556 1557 static inline void __iomem ** 1558 pcim_iomap_table(struct pci_dev *pdev) 1559 { 1560 struct pcim_iomap_devres *dr; 1561 1562 dr = lkpi_pcim_iomap_devres_find(pdev); 1563 if (dr == NULL) 1564 return (NULL); 1565 1566 /* 1567 * If the driver has manually set a flag to be able to request the 1568 * resource to use bus_read/write_<n>, return the shadow table. 1569 */ 1570 if (pdev->want_iomap_res) 1571 return ((void **)dr->res_table); 1572 1573 /* This is the Linux default. */ 1574 return (dr->mmio_table); 1575 } 1576 1577 static inline int 1578 pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, const char *name) 1579 { 1580 struct pcim_iomap_devres *dr; 1581 void *res; 1582 uint32_t mappings; 1583 int bar; 1584 1585 dr = lkpi_pcim_iomap_devres_find(pdev); 1586 if (dr == NULL) 1587 return (-ENOMEM); 1588 1589 /* Now iomap all the requested (by "mask") ones. */ 1590 for (bar = mappings = 0; mappings != mask; bar++) { 1591 if ((mask & (1 << bar)) == 0) 1592 continue; 1593 1594 /* Request double is not allowed. */ 1595 if (dr->mmio_table[bar] != NULL) { 1596 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1597 __func__, bar, dr->mmio_table[bar]); 1598 goto err; 1599 } 1600 1601 res = _lkpi_pci_iomap(pdev, bar, 0); 1602 if (res == NULL) 1603 goto err; 1604 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1605 dr->res_table[bar] = res; 1606 1607 mappings |= (1 << bar); 1608 } 1609 1610 return (0); 1611 err: 1612 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1613 if ((mappings & (1 << bar)) != 0) { 1614 res = dr->mmio_table[bar]; 1615 if (res == NULL) 1616 continue; 1617 pci_iounmap(pdev, res); 1618 } 1619 } 1620 1621 return (-EINVAL); 1622 } 1623 1624 static inline int 1625 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1626 { 1627 uint32_t requests, req_mask; 1628 int bar, error; 1629 1630 /* Request all the BARs ("regions") we do not iomap. */ 1631 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1632 for (bar = requests = 0; requests != req_mask; bar++) { 1633 if ((req_mask & (1 << bar)) == 0) 1634 continue; 1635 error = pci_request_region(pdev, bar, name); 1636 if (error != 0 && error != -ENODEV) 1637 goto err; 1638 requests |= (1 << bar); 1639 } 1640 1641 error = pcim_iomap_regions(pdev, mask, name); 1642 if (error != 0) 1643 goto err; 1644 1645 return (0); 1646 1647 err: 1648 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1649 if ((requests & (1 << bar)) != 0) 1650 pci_release_region(pdev, bar); 1651 } 1652 1653 return (-EINVAL); 1654 } 1655 1656 /* 1657 * We cannot simply re-define pci_get_device() as we would normally do 1658 * and then hide it in linux_pci.c as too many semi-native drivers still 1659 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1660 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1661 */ 1662 static inline struct pci_dev * 1663 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1664 { 1665 1666 return (lkpi_pci_get_device(vendor, device, odev)); 1667 } 1668 1669 /* This is a FreeBSD extension so we can use bus_*(). */ 1670 static inline void 1671 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1672 { 1673 pdev->want_iomap_res = true; 1674 } 1675 1676 static inline bool 1677 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1678 { 1679 1680 return (false); 1681 } 1682 1683 static inline void * 1684 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1685 { 1686 1687 return (NULL); 1688 } 1689 1690 static inline void 1691 pci_ignore_hotplug(struct pci_dev *pdev) 1692 { 1693 } 1694 1695 static inline const char * 1696 pci_power_name(pci_power_t state) 1697 { 1698 int pstate = state + 1; 1699 1700 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1701 return (pci_power_names[pstate]); 1702 else 1703 return (pci_power_names[0]); 1704 } 1705 1706 static inline int 1707 pcie_get_readrq(struct pci_dev *dev) 1708 { 1709 u16 ctl; 1710 1711 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1712 return (-EINVAL); 1713 1714 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1715 } 1716 1717 static inline bool 1718 pci_is_enabled(struct pci_dev *pdev) 1719 { 1720 1721 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1722 PCIM_CMD_BUSMASTEREN) != 0); 1723 } 1724 1725 static inline int 1726 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1727 { 1728 1729 return (0); 1730 } 1731 1732 static inline int 1733 pci_assign_resource(struct pci_dev *pdev, int bar) 1734 { 1735 1736 return (0); 1737 } 1738 1739 static inline int 1740 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1741 { 1742 1743 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1744 if (vector != 0) 1745 return (-EINVAL); 1746 return (pdev->irq); 1747 } 1748 1749 if (pdev->msix_enabled || pdev->msi_enabled) { 1750 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1751 return (-EINVAL); 1752 return (pdev->dev.irq_start + vector); 1753 } 1754 1755 return (-ENXIO); 1756 } 1757 1758 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1759