1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/nv.h> 41 #include <sys/pciio.h> 42 #include <sys/rman.h> 43 #include <sys/bus.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pci_private.h> 47 48 #include <machine/resource.h> 49 50 #include <linux/list.h> 51 #include <linux/dmapool.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/compiler.h> 54 #include <linux/errno.h> 55 #include <asm/atomic.h> 56 #include <linux/device.h> 57 #include <linux/pci_ids.h> 58 59 struct pci_device_id { 60 uint32_t vendor; 61 uint32_t device; 62 uint32_t subvendor; 63 uint32_t subdevice; 64 uint32_t class; 65 uint32_t class_mask; 66 uintptr_t driver_data; 67 }; 68 69 #define MODULE_DEVICE_TABLE(bus, table) 70 71 #define PCI_ANY_ID -1U 72 73 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 74 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 75 #define PCI_FUNC(devfn) ((devfn) & 0x07) 76 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 77 78 #define PCI_VDEVICE(_vendor, _device) \ 79 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 80 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 81 #define PCI_DEVICE(_vendor, _device) \ 82 .vendor = (_vendor), .device = (_device), \ 83 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 84 85 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 86 87 #define PCI_VENDOR_ID PCIR_DEVVENDOR 88 #define PCI_COMMAND PCIR_COMMAND 89 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 90 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 91 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 92 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 93 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 94 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 95 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 96 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 97 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 98 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 99 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 100 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 101 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 102 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 103 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 104 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 105 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 106 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 107 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 108 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 109 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 110 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 111 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 112 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 113 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 114 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 115 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 116 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 117 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 118 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 119 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 120 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 121 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 122 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 123 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 124 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 125 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 126 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 127 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 128 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 129 130 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 131 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 132 #define PCI_EXP_DEVSTA_TRPND 0x0020 133 134 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 135 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 136 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 137 138 enum pci_bus_speed { 139 PCI_SPEED_UNKNOWN = -1, 140 PCIE_SPEED_2_5GT, 141 PCIE_SPEED_5_0GT, 142 PCIE_SPEED_8_0GT, 143 PCIE_SPEED_16_0GT, 144 }; 145 146 enum pcie_link_width { 147 PCIE_LNK_WIDTH_RESRV = 0x00, 148 PCIE_LNK_X1 = 0x01, 149 PCIE_LNK_X2 = 0x02, 150 PCIE_LNK_X4 = 0x04, 151 PCIE_LNK_X8 = 0x08, 152 PCIE_LNK_X12 = 0x0c, 153 PCIE_LNK_X16 = 0x10, 154 PCIE_LNK_X32 = 0x20, 155 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 156 }; 157 158 #define PCIE_LINK_STATE_L0S 0x00000001 159 #define PCIE_LINK_STATE_L1 0x00000002 160 #define PCIE_LINK_STATE_CLKPM 0x00000004 161 162 typedef int pci_power_t; 163 164 #define PCI_D0 PCI_POWERSTATE_D0 165 #define PCI_D1 PCI_POWERSTATE_D1 166 #define PCI_D2 PCI_POWERSTATE_D2 167 #define PCI_D3hot PCI_POWERSTATE_D3 168 #define PCI_D3cold 4 169 170 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 171 172 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 173 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 174 175 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 176 177 struct pci_dev; 178 179 struct pci_driver { 180 struct list_head links; 181 char *name; 182 const struct pci_device_id *id_table; 183 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 184 void (*remove)(struct pci_dev *dev); 185 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 186 int (*resume) (struct pci_dev *dev); /* Device woken up */ 187 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 188 driver_t bsddriver; 189 devclass_t bsdclass; 190 struct device_driver driver; 191 const struct pci_error_handlers *err_handler; 192 bool isdrm; 193 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 194 const nvlist_t *pf_config); 195 void (*bsd_iov_uninit)(device_t dev); 196 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 197 const nvlist_t *vf_config); 198 }; 199 200 struct pci_bus { 201 struct pci_dev *self; 202 int domain; 203 int number; 204 }; 205 206 extern struct list_head pci_drivers; 207 extern struct list_head pci_devices; 208 extern spinlock_t pci_lock; 209 210 #define __devexit_p(x) x 211 212 struct pci_mmio_region { 213 TAILQ_ENTRY(pci_mmio_region) next; 214 struct resource *res; 215 int rid; 216 int type; 217 }; 218 219 struct pci_dev { 220 struct device dev; 221 struct list_head links; 222 struct pci_driver *pdrv; 223 struct pci_bus *bus; 224 uint16_t device; 225 uint16_t vendor; 226 uint16_t subsystem_vendor; 227 uint16_t subsystem_device; 228 unsigned int irq; 229 unsigned int devfn; 230 uint32_t class; 231 uint8_t revision; 232 bool msi_enabled; 233 phys_addr_t rom; 234 size_t romlen; 235 236 TAILQ_HEAD(, pci_mmio_region) mmio; 237 }; 238 239 static inline struct resource_list_entry * 240 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 241 { 242 struct pci_devinfo *dinfo; 243 struct resource_list *rl; 244 245 dinfo = device_get_ivars(pdev->dev.bsddev); 246 rl = &dinfo->resources; 247 return resource_list_find(rl, type, rid); 248 } 249 250 static inline struct resource_list_entry * 251 linux_pci_get_bar(struct pci_dev *pdev, int bar) 252 { 253 struct resource_list_entry *rle; 254 255 bar = PCIR_BAR(bar); 256 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 257 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 258 return (rle); 259 } 260 261 static inline struct device * 262 linux_pci_find_irq_dev(unsigned int irq) 263 { 264 struct pci_dev *pdev; 265 struct device *found; 266 267 found = NULL; 268 spin_lock(&pci_lock); 269 list_for_each_entry(pdev, &pci_devices, links) { 270 if (irq == pdev->dev.irq || 271 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 272 found = &pdev->dev; 273 break; 274 } 275 } 276 spin_unlock(&pci_lock); 277 return (found); 278 } 279 280 static inline int 281 pci_resource_type(struct pci_dev *pdev, int bar) 282 { 283 struct pci_map *pm; 284 285 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 286 if (!pm) 287 return (-1); 288 289 if (PCI_BAR_IO(pm->pm_value)) 290 return (SYS_RES_IOPORT); 291 else 292 return (SYS_RES_MEMORY); 293 } 294 295 /* 296 * All drivers just seem to want to inspect the type not flags. 297 */ 298 static inline int 299 pci_resource_flags(struct pci_dev *pdev, int bar) 300 { 301 int type; 302 303 type = pci_resource_type(pdev, bar); 304 if (type < 0) 305 return (0); 306 return (1 << type); 307 } 308 309 static inline const char * 310 pci_name(struct pci_dev *d) 311 { 312 313 return device_get_desc(d->dev.bsddev); 314 } 315 316 static inline void * 317 pci_get_drvdata(struct pci_dev *pdev) 318 { 319 320 return dev_get_drvdata(&pdev->dev); 321 } 322 323 static inline void 324 pci_set_drvdata(struct pci_dev *pdev, void *data) 325 { 326 327 dev_set_drvdata(&pdev->dev, data); 328 } 329 330 static __inline void 331 pci_dev_put(struct pci_dev *pdev) 332 { 333 334 if (pdev != NULL) 335 put_device(&pdev->dev); 336 } 337 338 static inline int 339 pci_enable_device(struct pci_dev *pdev) 340 { 341 342 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 343 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 344 return (0); 345 } 346 347 static inline void 348 pci_disable_device(struct pci_dev *pdev) 349 { 350 351 pci_disable_busmaster(pdev->dev.bsddev); 352 } 353 354 static inline int 355 pci_set_master(struct pci_dev *pdev) 356 { 357 358 pci_enable_busmaster(pdev->dev.bsddev); 359 return (0); 360 } 361 362 static inline int 363 pci_set_power_state(struct pci_dev *pdev, int state) 364 { 365 366 pci_set_powerstate(pdev->dev.bsddev, state); 367 return (0); 368 } 369 370 static inline int 371 pci_clear_master(struct pci_dev *pdev) 372 { 373 374 pci_disable_busmaster(pdev->dev.bsddev); 375 return (0); 376 } 377 378 static inline int 379 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 380 { 381 int rid; 382 int type; 383 384 type = pci_resource_type(pdev, bar); 385 if (type < 0) 386 return (-ENODEV); 387 rid = PCIR_BAR(bar); 388 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 389 RF_ACTIVE) == NULL) 390 return (-EINVAL); 391 return (0); 392 } 393 394 static inline void 395 pci_release_region(struct pci_dev *pdev, int bar) 396 { 397 struct resource_list_entry *rle; 398 399 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 400 return; 401 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 402 } 403 404 static inline void 405 pci_release_regions(struct pci_dev *pdev) 406 { 407 int i; 408 409 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 410 pci_release_region(pdev, i); 411 } 412 413 static inline int 414 pci_request_regions(struct pci_dev *pdev, const char *res_name) 415 { 416 int error; 417 int i; 418 419 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 420 error = pci_request_region(pdev, i, res_name); 421 if (error && error != -ENODEV) { 422 pci_release_regions(pdev); 423 return (error); 424 } 425 } 426 return (0); 427 } 428 429 static inline void 430 pci_disable_msix(struct pci_dev *pdev) 431 { 432 433 pci_release_msi(pdev->dev.bsddev); 434 435 /* 436 * The MSIX IRQ numbers associated with this PCI device are no 437 * longer valid and might be re-assigned. Make sure 438 * linux_pci_find_irq_dev() does no longer see them by 439 * resetting their references to zero: 440 */ 441 pdev->dev.irq_start = 0; 442 pdev->dev.irq_end = 0; 443 } 444 445 #define pci_disable_msi(pdev) \ 446 linux_pci_disable_msi(pdev) 447 448 static inline void 449 linux_pci_disable_msi(struct pci_dev *pdev) 450 { 451 452 pci_release_msi(pdev->dev.bsddev); 453 454 pdev->dev.irq_start = 0; 455 pdev->dev.irq_end = 0; 456 pdev->irq = pdev->dev.irq; 457 pdev->msi_enabled = false; 458 } 459 460 #define pci_free_irq_vectors(pdev) \ 461 linux_pci_disable_msi(pdev) 462 463 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 464 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 465 466 static inline bus_addr_t 467 pci_bus_address(struct pci_dev *pdev, int bar) 468 { 469 470 return (pci_resource_start(pdev, bar)); 471 } 472 473 #define PCI_CAP_ID_EXP PCIY_EXPRESS 474 #define PCI_CAP_ID_PCIX PCIY_PCIX 475 #define PCI_CAP_ID_AGP PCIY_AGP 476 #define PCI_CAP_ID_PM PCIY_PMG 477 478 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 479 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 480 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 481 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 482 #define PCI_EXP_LNKSTA PCIER_LINK_STA 483 484 static inline int 485 pci_find_capability(struct pci_dev *pdev, int capid) 486 { 487 int reg; 488 489 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 490 return (0); 491 return (reg); 492 } 493 494 static inline int pci_pcie_cap(struct pci_dev *dev) 495 { 496 return pci_find_capability(dev, PCI_CAP_ID_EXP); 497 } 498 499 static inline int 500 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 501 { 502 503 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 504 return (0); 505 } 506 507 static inline int 508 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 509 { 510 511 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 512 return (0); 513 } 514 515 static inline int 516 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 517 { 518 519 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 520 return (0); 521 } 522 523 static inline int 524 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 525 { 526 527 pci_write_config(pdev->dev.bsddev, where, val, 1); 528 return (0); 529 } 530 531 static inline int 532 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 533 { 534 535 pci_write_config(pdev->dev.bsddev, where, val, 2); 536 return (0); 537 } 538 539 static inline int 540 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 541 { 542 543 pci_write_config(pdev->dev.bsddev, where, val, 4); 544 return (0); 545 } 546 547 int linux_pci_register_driver(struct pci_driver *pdrv); 548 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 549 void linux_pci_unregister_driver(struct pci_driver *pdrv); 550 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 551 552 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 553 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 554 555 struct msix_entry { 556 int entry; 557 int vector; 558 }; 559 560 /* 561 * Enable msix, positive errors indicate actual number of available 562 * vectors. Negative errors are failures. 563 * 564 * NB: define added to prevent this definition of pci_enable_msix from 565 * clashing with the native FreeBSD version. 566 */ 567 #define pci_enable_msix(...) \ 568 linux_pci_enable_msix(__VA_ARGS__) 569 570 static inline int 571 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 572 { 573 struct resource_list_entry *rle; 574 int error; 575 int avail; 576 int i; 577 578 avail = pci_msix_count(pdev->dev.bsddev); 579 if (avail < nreq) { 580 if (avail == 0) 581 return -EINVAL; 582 return avail; 583 } 584 avail = nreq; 585 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 586 return error; 587 /* 588 * Handle case where "pci_alloc_msix()" may allocate less 589 * interrupts than available and return with no error: 590 */ 591 if (avail < nreq) { 592 pci_release_msi(pdev->dev.bsddev); 593 return avail; 594 } 595 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 596 pdev->dev.irq_start = rle->start; 597 pdev->dev.irq_end = rle->start + avail; 598 for (i = 0; i < nreq; i++) 599 entries[i].vector = pdev->dev.irq_start + i; 600 return (0); 601 } 602 603 #define pci_enable_msix_range(...) \ 604 linux_pci_enable_msix_range(__VA_ARGS__) 605 606 static inline int 607 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 608 int minvec, int maxvec) 609 { 610 int nvec = maxvec; 611 int rc; 612 613 if (maxvec < minvec) 614 return (-ERANGE); 615 616 do { 617 rc = pci_enable_msix(dev, entries, nvec); 618 if (rc < 0) { 619 return (rc); 620 } else if (rc > 0) { 621 if (rc < minvec) 622 return (-ENOSPC); 623 nvec = rc; 624 } 625 } while (rc); 626 return (nvec); 627 } 628 629 #define pci_enable_msi(pdev) \ 630 linux_pci_enable_msi(pdev) 631 632 static inline int 633 pci_enable_msi(struct pci_dev *pdev) 634 { 635 struct resource_list_entry *rle; 636 int error; 637 int avail; 638 639 avail = pci_msi_count(pdev->dev.bsddev); 640 if (avail < 1) 641 return -EINVAL; 642 643 avail = 1; /* this function only enable one MSI IRQ */ 644 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 645 return error; 646 647 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 648 pdev->dev.irq_start = rle->start; 649 pdev->dev.irq_end = rle->start + avail; 650 pdev->irq = rle->start; 651 pdev->msi_enabled = true; 652 return (0); 653 } 654 655 static inline int 656 pci_channel_offline(struct pci_dev *pdev) 657 { 658 659 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 660 } 661 662 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 663 { 664 return -ENODEV; 665 } 666 static inline void pci_disable_sriov(struct pci_dev *dev) 667 { 668 } 669 670 static inline void * 671 pci_iomap(struct pci_dev *dev, int mmio_bar, int mmio_size __unused) 672 { 673 struct pci_mmio_region *mmio; 674 675 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 676 mmio->rid = PCIR_BAR(mmio_bar); 677 mmio->type = pci_resource_type(dev, mmio_bar); 678 mmio->res = bus_alloc_resource_any(dev->dev.bsddev, mmio->type, 679 &mmio->rid, RF_ACTIVE); 680 if (mmio->res == NULL) { 681 free(mmio, M_DEVBUF); 682 return (NULL); 683 } 684 TAILQ_INSERT_TAIL(&dev->mmio, mmio, next); 685 686 return ((void *)rman_get_bushandle(mmio->res)); 687 } 688 689 static inline void 690 pci_iounmap(struct pci_dev *dev, void *res) 691 { 692 struct pci_mmio_region *mmio, *p; 693 694 TAILQ_FOREACH_SAFE(mmio, &dev->mmio, next, p) { 695 if (res != (void *)rman_get_bushandle(mmio->res)) 696 continue; 697 bus_release_resource(dev->dev.bsddev, 698 mmio->type, mmio->rid, mmio->res); 699 TAILQ_REMOVE(&dev->mmio, mmio, next); 700 free(mmio, M_DEVBUF); 701 return; 702 } 703 } 704 705 static inline void 706 lkpi_pci_save_state(struct pci_dev *pdev) 707 { 708 709 pci_save_state(pdev->dev.bsddev); 710 } 711 712 static inline void 713 lkpi_pci_restore_state(struct pci_dev *pdev) 714 { 715 716 pci_restore_state(pdev->dev.bsddev); 717 } 718 719 #define pci_save_state(dev) lkpi_pci_save_state(dev) 720 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 721 722 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 723 const struct pci_device_id _table[] __devinitdata 724 725 /* XXX This should not be necessary. */ 726 #define pcix_set_mmrbc(d, v) 0 727 #define pcix_get_max_mmrbc(d) 0 728 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 729 730 #define PCI_DMA_BIDIRECTIONAL 0 731 #define PCI_DMA_TODEVICE 1 732 #define PCI_DMA_FROMDEVICE 2 733 #define PCI_DMA_NONE 3 734 735 #define pci_pool dma_pool 736 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 737 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 738 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 739 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 740 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 741 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 742 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 743 _size, _vaddr, _dma_handle) 744 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 745 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 746 _sg, _nents, (enum dma_data_direction)_dir) 747 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 748 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 749 (_ptr), (_size), (enum dma_data_direction)_dir) 750 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 751 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 752 _addr, _size, (enum dma_data_direction)_dir) 753 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 754 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 755 _sg, _nents, (enum dma_data_direction)_dir) 756 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 757 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 758 _offset, _size, (enum dma_data_direction)_dir) 759 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 760 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 761 _dma_address, _size, (enum dma_data_direction)_dir) 762 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 763 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 764 dma_mapping_error(&(_pdev)->dev, _dma_addr) 765 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 766 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 767 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 768 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 769 #define pci_unmap_addr dma_unmap_addr 770 #define pci_unmap_addr_set dma_unmap_addr_set 771 #define pci_unmap_len dma_unmap_len 772 #define pci_unmap_len_set dma_unmap_len_set 773 774 typedef unsigned int __bitwise pci_channel_state_t; 775 typedef unsigned int __bitwise pci_ers_result_t; 776 777 enum pci_channel_state { 778 pci_channel_io_normal = 1, 779 pci_channel_io_frozen = 2, 780 pci_channel_io_perm_failure = 3, 781 }; 782 783 enum pci_ers_result { 784 PCI_ERS_RESULT_NONE = 1, 785 PCI_ERS_RESULT_CAN_RECOVER = 2, 786 PCI_ERS_RESULT_NEED_RESET = 3, 787 PCI_ERS_RESULT_DISCONNECT = 4, 788 PCI_ERS_RESULT_RECOVERED = 5, 789 }; 790 791 /* PCI bus error event callbacks */ 792 struct pci_error_handlers { 793 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 794 enum pci_channel_state error); 795 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 796 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 797 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 798 void (*resume)(struct pci_dev *dev); 799 }; 800 801 /* FreeBSD does not support SRIOV - yet */ 802 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 803 { 804 return dev; 805 } 806 807 static inline bool pci_is_pcie(struct pci_dev *dev) 808 { 809 return !!pci_pcie_cap(dev); 810 } 811 812 static inline u16 pcie_flags_reg(struct pci_dev *dev) 813 { 814 int pos; 815 u16 reg16; 816 817 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 818 if (!pos) 819 return 0; 820 821 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 822 823 return reg16; 824 } 825 826 static inline int pci_pcie_type(struct pci_dev *dev) 827 { 828 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 829 } 830 831 static inline int pcie_cap_version(struct pci_dev *dev) 832 { 833 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 834 } 835 836 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 837 { 838 int type = pci_pcie_type(dev); 839 840 return pcie_cap_version(dev) > 1 || 841 type == PCI_EXP_TYPE_ROOT_PORT || 842 type == PCI_EXP_TYPE_ENDPOINT || 843 type == PCI_EXP_TYPE_LEG_END; 844 } 845 846 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 847 { 848 return true; 849 } 850 851 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 852 { 853 int type = pci_pcie_type(dev); 854 855 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 856 (type == PCI_EXP_TYPE_DOWNSTREAM && 857 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 858 } 859 860 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 861 { 862 int type = pci_pcie_type(dev); 863 864 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 865 type == PCI_EXP_TYPE_RC_EC; 866 } 867 868 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 869 { 870 if (!pci_is_pcie(dev)) 871 return false; 872 873 switch (pos) { 874 case PCI_EXP_FLAGS_TYPE: 875 return true; 876 case PCI_EXP_DEVCAP: 877 case PCI_EXP_DEVCTL: 878 case PCI_EXP_DEVSTA: 879 return pcie_cap_has_devctl(dev); 880 case PCI_EXP_LNKCAP: 881 case PCI_EXP_LNKCTL: 882 case PCI_EXP_LNKSTA: 883 return pcie_cap_has_lnkctl(dev); 884 case PCI_EXP_SLTCAP: 885 case PCI_EXP_SLTCTL: 886 case PCI_EXP_SLTSTA: 887 return pcie_cap_has_sltctl(dev); 888 case PCI_EXP_RTCTL: 889 case PCI_EXP_RTCAP: 890 case PCI_EXP_RTSTA: 891 return pcie_cap_has_rtctl(dev); 892 case PCI_EXP_DEVCAP2: 893 case PCI_EXP_DEVCTL2: 894 case PCI_EXP_LNKCAP2: 895 case PCI_EXP_LNKCTL2: 896 case PCI_EXP_LNKSTA2: 897 return pcie_cap_version(dev) > 1; 898 default: 899 return false; 900 } 901 } 902 903 static inline int 904 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 905 { 906 if (pos & 3) 907 return -EINVAL; 908 909 if (!pcie_capability_reg_implemented(dev, pos)) 910 return -EINVAL; 911 912 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 913 } 914 915 static inline int 916 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 917 { 918 if (pos & 3) 919 return -EINVAL; 920 921 if (!pcie_capability_reg_implemented(dev, pos)) 922 return -EINVAL; 923 924 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 925 } 926 927 static inline int 928 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 929 { 930 if (pos & 1) 931 return -EINVAL; 932 933 if (!pcie_capability_reg_implemented(dev, pos)) 934 return 0; 935 936 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 937 } 938 939 static inline int pcie_get_minimum_link(struct pci_dev *dev, 940 enum pci_bus_speed *speed, enum pcie_link_width *width) 941 { 942 *speed = PCI_SPEED_UNKNOWN; 943 *width = PCIE_LNK_WIDTH_UNKNOWN; 944 return (0); 945 } 946 947 static inline int 948 pci_num_vf(struct pci_dev *dev) 949 { 950 return (0); 951 } 952 953 static inline enum pci_bus_speed 954 pcie_get_speed_cap(struct pci_dev *dev) 955 { 956 device_t root; 957 uint32_t lnkcap, lnkcap2; 958 int error, pos; 959 960 root = device_get_parent(dev->dev.bsddev); 961 if (root == NULL) 962 return (PCI_SPEED_UNKNOWN); 963 root = device_get_parent(root); 964 if (root == NULL) 965 return (PCI_SPEED_UNKNOWN); 966 root = device_get_parent(root); 967 if (root == NULL) 968 return (PCI_SPEED_UNKNOWN); 969 970 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 971 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 972 return (PCI_SPEED_UNKNOWN); 973 974 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 975 return (PCI_SPEED_UNKNOWN); 976 977 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 978 979 if (lnkcap2) { /* PCIe r3.0-compliant */ 980 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 981 return (PCIE_SPEED_2_5GT); 982 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 983 return (PCIE_SPEED_5_0GT); 984 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 985 return (PCIE_SPEED_8_0GT); 986 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 987 return (PCIE_SPEED_16_0GT); 988 } else { /* pre-r3.0 */ 989 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 990 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 991 return (PCIE_SPEED_2_5GT); 992 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 993 return (PCIE_SPEED_5_0GT); 994 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 995 return (PCIE_SPEED_8_0GT); 996 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 997 return (PCIE_SPEED_16_0GT); 998 } 999 return (PCI_SPEED_UNKNOWN); 1000 } 1001 1002 static inline enum pcie_link_width 1003 pcie_get_width_cap(struct pci_dev *dev) 1004 { 1005 uint32_t lnkcap; 1006 1007 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1008 if (lnkcap) 1009 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1010 1011 return (PCIE_LNK_WIDTH_UNKNOWN); 1012 } 1013 1014 static inline int 1015 pcie_get_mps(struct pci_dev *dev) 1016 { 1017 return (pci_get_max_payload(dev->dev.bsddev)); 1018 } 1019 1020 static inline uint32_t 1021 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1022 { 1023 1024 switch(spd) { 1025 case PCIE_SPEED_16_0GT: 1026 return (16000 * 128 / 130); 1027 case PCIE_SPEED_8_0GT: 1028 return (8000 * 128 / 130); 1029 case PCIE_SPEED_5_0GT: 1030 return (5000 * 8 / 10); 1031 case PCIE_SPEED_2_5GT: 1032 return (2500 * 8 / 10); 1033 default: 1034 return (0); 1035 } 1036 } 1037 1038 static inline uint32_t 1039 pcie_bandwidth_available(struct pci_dev *pdev, 1040 struct pci_dev **limiting, 1041 enum pci_bus_speed *speed, 1042 enum pcie_link_width *width) 1043 { 1044 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1045 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1046 1047 if (speed) 1048 *speed = nspeed; 1049 if (width) 1050 *width = nwidth; 1051 1052 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1053 } 1054 1055 /* 1056 * The following functions can be used to attach/detach the LinuxKPI's 1057 * PCI device runtime. The pci_driver and pci_device_id pointer is 1058 * allowed to be NULL. Other pointers must be all valid. 1059 * The pci_dev structure should be zero-initialized before passed 1060 * to the linux_pci_attach_device function. 1061 */ 1062 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1063 const struct pci_device_id *, struct pci_dev *); 1064 extern int linux_pci_detach_device(struct pci_dev *); 1065 1066 static inline int 1067 pci_dev_present(const struct pci_device_id *cur) 1068 { 1069 while (cur != NULL && (cur->vendor || cur->device)) { 1070 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1071 return (1); 1072 } 1073 cur++; 1074 } 1075 return (0); 1076 } 1077 1078 static inline bool 1079 pci_is_root_bus(struct pci_bus *pbus) 1080 { 1081 1082 return (pbus->self == NULL); 1083 } 1084 1085 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1086 unsigned int bus, unsigned int devfn); 1087 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1088 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1089 1090 static inline int 1091 pci_domain_nr(struct pci_bus *pbus) 1092 { 1093 1094 return (pbus->domain); 1095 } 1096 1097 static inline int 1098 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1099 int pos, uint32_t *val, int len) 1100 { 1101 1102 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1103 return (0); 1104 } 1105 1106 static inline int 1107 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1108 { 1109 uint32_t tmp; 1110 int ret; 1111 1112 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1113 *val = (u16)tmp; 1114 return (ret); 1115 } 1116 1117 static inline int 1118 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1119 { 1120 uint32_t tmp; 1121 int ret; 1122 1123 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1124 *val = (u8)tmp; 1125 return (ret); 1126 } 1127 1128 static inline int 1129 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1130 uint32_t val, int size) 1131 { 1132 1133 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1134 return (0); 1135 } 1136 1137 static inline int 1138 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1139 uint8_t val) 1140 { 1141 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1142 } 1143 1144 static inline int 1145 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1146 uint16_t val) 1147 { 1148 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1149 } 1150 1151 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1152 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1153 1154 #endif /* _LINUX_PCI_H_ */ 1155