1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013, 2014 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/pciio.h> 41 #include <sys/rman.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pci_private.h> 45 46 #include <machine/resource.h> 47 48 #include <linux/list.h> 49 #include <linux/dmapool.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/compiler.h> 52 #include <linux/errno.h> 53 #include <asm/atomic.h> 54 #include <linux/device.h> 55 56 struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class_mask; 62 uintptr_t driver_data; 63 }; 64 65 #define MODULE_DEVICE_TABLE(bus, table) 66 #define PCI_ANY_ID (-1) 67 #define PCI_VENDOR_ID_MELLANOX 0x15b3 68 #define PCI_VENDOR_ID_TOPSPIN 0x1867 69 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 70 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 71 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 72 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 73 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 74 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 75 76 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 77 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 78 #define PCI_FUNC(devfn) ((devfn) & 0x07) 79 80 #define PCI_VDEVICE(_vendor, _device) \ 81 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 82 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 83 #define PCI_DEVICE(_vendor, _device) \ 84 .vendor = (_vendor), .device = (_device), \ 85 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 86 87 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 88 89 #define PCI_VENDOR_ID PCIR_DEVVENDOR 90 #define PCI_COMMAND PCIR_COMMAND 91 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 92 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 93 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 94 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 95 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 96 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 97 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 98 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 99 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 100 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 101 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 102 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 103 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 104 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 105 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 106 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 107 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 108 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 109 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 110 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 111 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 112 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 113 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 114 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 115 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 116 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 117 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 118 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 119 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 120 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 121 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 122 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 123 124 #define IORESOURCE_MEM SYS_RES_MEMORY 125 #define IORESOURCE_IO SYS_RES_IOPORT 126 #define IORESOURCE_IRQ SYS_RES_IRQ 127 128 enum pci_bus_speed { 129 PCI_SPEED_UNKNOWN = -1, 130 PCIE_SPEED_2_5GT, 131 PCIE_SPEED_5_0GT, 132 PCIE_SPEED_8_0GT, 133 }; 134 135 enum pcie_link_width { 136 PCIE_LNK_WIDTH_UNKNOWN = -1, 137 }; 138 139 struct pci_dev; 140 141 struct pci_driver { 142 struct list_head links; 143 char *name; 144 const struct pci_device_id *id_table; 145 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 146 void (*remove)(struct pci_dev *dev); 147 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 148 int (*resume) (struct pci_dev *dev); /* Device woken up */ 149 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 150 driver_t driver; 151 devclass_t bsdclass; 152 const struct pci_error_handlers *err_handler; 153 }; 154 155 extern struct list_head pci_drivers; 156 extern struct list_head pci_devices; 157 extern spinlock_t pci_lock; 158 159 #define __devexit_p(x) x 160 161 struct pci_dev { 162 struct device dev; 163 struct list_head links; 164 struct pci_driver *pdrv; 165 uint64_t dma_mask; 166 uint16_t device; 167 uint16_t vendor; 168 unsigned int irq; 169 unsigned int devfn; 170 u8 revision; 171 }; 172 173 static inline struct resource_list_entry * 174 _pci_get_rle(struct pci_dev *pdev, int type, int rid) 175 { 176 struct pci_devinfo *dinfo; 177 struct resource_list *rl; 178 179 dinfo = device_get_ivars(pdev->dev.bsddev); 180 rl = &dinfo->resources; 181 return resource_list_find(rl, type, rid); 182 } 183 184 static inline struct resource_list_entry * 185 _pci_get_bar(struct pci_dev *pdev, int bar) 186 { 187 struct resource_list_entry *rle; 188 189 bar = PCIR_BAR(bar); 190 if ((rle = _pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 191 rle = _pci_get_rle(pdev, SYS_RES_IOPORT, bar); 192 return (rle); 193 } 194 195 static inline struct device * 196 _pci_find_irq_dev(unsigned int irq) 197 { 198 struct pci_dev *pdev; 199 200 spin_lock(&pci_lock); 201 list_for_each_entry(pdev, &pci_devices, links) { 202 if (irq == pdev->dev.irq) 203 break; 204 if (irq >= pdev->dev.msix && irq < pdev->dev.msix_max) 205 break; 206 } 207 spin_unlock(&pci_lock); 208 if (pdev) 209 return &pdev->dev; 210 return (NULL); 211 } 212 213 static inline unsigned long 214 pci_resource_start(struct pci_dev *pdev, int bar) 215 { 216 struct resource_list_entry *rle; 217 218 if ((rle = _pci_get_bar(pdev, bar)) == NULL) 219 return (0); 220 return rle->start; 221 } 222 223 static inline unsigned long 224 pci_resource_len(struct pci_dev *pdev, int bar) 225 { 226 struct resource_list_entry *rle; 227 228 if ((rle = _pci_get_bar(pdev, bar)) == NULL) 229 return (0); 230 return rle->count; 231 } 232 233 /* 234 * All drivers just seem to want to inspect the type not flags. 235 */ 236 static inline int 237 pci_resource_flags(struct pci_dev *pdev, int bar) 238 { 239 struct resource_list_entry *rle; 240 241 if ((rle = _pci_get_bar(pdev, bar)) == NULL) 242 return (0); 243 return rle->type; 244 } 245 246 static inline const char * 247 pci_name(struct pci_dev *d) 248 { 249 250 return device_get_desc(d->dev.bsddev); 251 } 252 253 static inline void * 254 pci_get_drvdata(struct pci_dev *pdev) 255 { 256 257 return dev_get_drvdata(&pdev->dev); 258 } 259 260 static inline void 261 pci_set_drvdata(struct pci_dev *pdev, void *data) 262 { 263 264 dev_set_drvdata(&pdev->dev, data); 265 } 266 267 static inline int 268 pci_enable_device(struct pci_dev *pdev) 269 { 270 271 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 272 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 273 return (0); 274 } 275 276 static inline void 277 pci_disable_device(struct pci_dev *pdev) 278 { 279 } 280 281 static inline int 282 pci_set_master(struct pci_dev *pdev) 283 { 284 285 pci_enable_busmaster(pdev->dev.bsddev); 286 return (0); 287 } 288 289 static inline int 290 pci_clear_master(struct pci_dev *pdev) 291 { 292 293 pci_disable_busmaster(pdev->dev.bsddev); 294 return (0); 295 } 296 297 static inline int 298 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 299 { 300 int rid; 301 int type; 302 303 type = pci_resource_flags(pdev, bar); 304 if (type == 0) 305 return (-ENODEV); 306 rid = PCIR_BAR(bar); 307 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 308 RF_ACTIVE) == NULL) 309 return (-EINVAL); 310 return (0); 311 } 312 313 static inline void 314 pci_release_region(struct pci_dev *pdev, int bar) 315 { 316 struct resource_list_entry *rle; 317 318 if ((rle = _pci_get_bar(pdev, bar)) == NULL) 319 return; 320 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 321 } 322 323 static inline void 324 pci_release_regions(struct pci_dev *pdev) 325 { 326 int i; 327 328 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 329 pci_release_region(pdev, i); 330 } 331 332 static inline int 333 pci_request_regions(struct pci_dev *pdev, const char *res_name) 334 { 335 int error; 336 int i; 337 338 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 339 error = pci_request_region(pdev, i, res_name); 340 if (error && error != -ENODEV) { 341 pci_release_regions(pdev); 342 return (error); 343 } 344 } 345 return (0); 346 } 347 348 static inline void 349 pci_disable_msix(struct pci_dev *pdev) 350 { 351 352 pci_release_msi(pdev->dev.bsddev); 353 } 354 355 #define PCI_CAP_ID_EXP PCIY_EXPRESS 356 #define PCI_CAP_ID_PCIX PCIY_PCIX 357 358 359 static inline int 360 pci_find_capability(struct pci_dev *pdev, int capid) 361 { 362 int reg; 363 364 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 365 return (0); 366 return (reg); 367 } 368 369 static inline int pci_pcie_cap(struct pci_dev *dev) 370 { 371 return pci_find_capability(dev, PCI_CAP_ID_EXP); 372 } 373 374 375 static inline int 376 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 377 { 378 379 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 380 return (0); 381 } 382 383 static inline int 384 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 385 { 386 387 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 388 return (0); 389 } 390 391 static inline int 392 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 393 { 394 395 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 396 return (0); 397 } 398 399 static inline int 400 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 401 { 402 403 pci_write_config(pdev->dev.bsddev, where, val, 1); 404 return (0); 405 } 406 407 static inline int 408 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 409 { 410 411 pci_write_config(pdev->dev.bsddev, where, val, 2); 412 return (0); 413 } 414 415 static inline int 416 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 417 { 418 419 pci_write_config(pdev->dev.bsddev, where, val, 4); 420 return (0); 421 } 422 423 extern int pci_register_driver(struct pci_driver *pdrv); 424 extern void pci_unregister_driver(struct pci_driver *pdrv); 425 426 struct msix_entry { 427 int entry; 428 int vector; 429 }; 430 431 /* 432 * Enable msix, positive errors indicate actual number of available 433 * vectors. Negative errors are failures. 434 * 435 * NB: define added to prevent this definition of pci_enable_msix from 436 * clashing with the native FreeBSD version. 437 */ 438 #define pci_enable_msix linux_pci_enable_msix 439 static inline int 440 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 441 { 442 struct resource_list_entry *rle; 443 int error; 444 int avail; 445 int i; 446 447 avail = pci_msix_count(pdev->dev.bsddev); 448 if (avail < nreq) { 449 if (avail == 0) 450 return -EINVAL; 451 return avail; 452 } 453 avail = nreq; 454 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 455 return error; 456 /* 457 * Handle case where "pci_alloc_msix()" may allocate less 458 * interrupts than available and return with no error: 459 */ 460 if (avail < nreq) { 461 pci_release_msi(pdev->dev.bsddev); 462 return avail; 463 } 464 rle = _pci_get_rle(pdev, SYS_RES_IRQ, 1); 465 pdev->dev.msix = rle->start; 466 pdev->dev.msix_max = rle->start + avail; 467 for (i = 0; i < nreq; i++) 468 entries[i].vector = pdev->dev.msix + i; 469 return (0); 470 } 471 472 #define pci_enable_msix_range linux_pci_enable_msix_range 473 static inline int 474 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 475 int minvec, int maxvec) 476 { 477 int nvec = maxvec; 478 int rc; 479 480 if (maxvec < minvec) 481 return (-ERANGE); 482 483 do { 484 rc = pci_enable_msix(dev, entries, nvec); 485 if (rc < 0) { 486 return (rc); 487 } else if (rc > 0) { 488 if (rc < minvec) 489 return (-ENOSPC); 490 nvec = rc; 491 } 492 } while (rc); 493 return (nvec); 494 } 495 496 static inline int pci_channel_offline(struct pci_dev *pdev) 497 { 498 return false; 499 } 500 501 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 502 { 503 return -ENODEV; 504 } 505 static inline void pci_disable_sriov(struct pci_dev *dev) 506 { 507 } 508 509 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 510 const struct pci_device_id _table[] __devinitdata 511 512 513 /* XXX This should not be necessary. */ 514 #define pcix_set_mmrbc(d, v) 0 515 #define pcix_get_max_mmrbc(d) 0 516 #define pcie_set_readrq(d, v) 0 517 518 #define PCI_DMA_BIDIRECTIONAL 0 519 #define PCI_DMA_TODEVICE 1 520 #define PCI_DMA_FROMDEVICE 2 521 #define PCI_DMA_NONE 3 522 523 #define pci_pool dma_pool 524 #define pci_pool_destroy dma_pool_destroy 525 #define pci_pool_alloc dma_pool_alloc 526 #define pci_pool_free dma_pool_free 527 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 528 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 529 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 530 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 531 _size, _vaddr, _dma_handle) 532 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 533 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 534 _sg, _nents, (enum dma_data_direction)_dir) 535 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 536 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 537 (_ptr), (_size), (enum dma_data_direction)_dir) 538 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 539 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 540 _addr, _size, (enum dma_data_direction)_dir) 541 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 542 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 543 _sg, _nents, (enum dma_data_direction)_dir) 544 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 545 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 546 _offset, _size, (enum dma_data_direction)_dir) 547 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 548 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 549 _dma_address, _size, (enum dma_data_direction)_dir) 550 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 551 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 552 dma_mapping_error(&(_pdev)->dev, _dma_addr) 553 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 554 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 555 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 556 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 557 #define pci_unmap_addr dma_unmap_addr 558 #define pci_unmap_addr_set dma_unmap_addr_set 559 #define pci_unmap_len dma_unmap_len 560 #define pci_unmap_len_set dma_unmap_len_set 561 562 typedef unsigned int __bitwise pci_channel_state_t; 563 typedef unsigned int __bitwise pci_ers_result_t; 564 565 enum pci_channel_state { 566 pci_channel_io_normal = 1, 567 pci_channel_io_frozen = 2, 568 pci_channel_io_perm_failure = 3, 569 }; 570 571 enum pci_ers_result { 572 PCI_ERS_RESULT_NONE = 1, 573 PCI_ERS_RESULT_CAN_RECOVER = 2, 574 PCI_ERS_RESULT_NEED_RESET = 3, 575 PCI_ERS_RESULT_DISCONNECT = 4, 576 PCI_ERS_RESULT_RECOVERED = 5, 577 }; 578 579 580 /* PCI bus error event callbacks */ 581 struct pci_error_handlers { 582 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 583 enum pci_channel_state error); 584 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 585 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 586 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 587 void (*resume)(struct pci_dev *dev); 588 }; 589 590 /* FreeBSD does not support SRIOV - yet */ 591 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 592 { 593 return dev; 594 } 595 596 static inline bool pci_is_pcie(struct pci_dev *dev) 597 { 598 return !!pci_pcie_cap(dev); 599 } 600 601 static inline u16 pcie_flags_reg(struct pci_dev *dev) 602 { 603 int pos; 604 u16 reg16; 605 606 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 607 if (!pos) 608 return 0; 609 610 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 611 612 return reg16; 613 } 614 615 616 static inline int pci_pcie_type(struct pci_dev *dev) 617 { 618 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 619 } 620 621 static inline int pcie_cap_version(struct pci_dev *dev) 622 { 623 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 624 } 625 626 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 627 { 628 int type = pci_pcie_type(dev); 629 630 return pcie_cap_version(dev) > 1 || 631 type == PCI_EXP_TYPE_ROOT_PORT || 632 type == PCI_EXP_TYPE_ENDPOINT || 633 type == PCI_EXP_TYPE_LEG_END; 634 } 635 636 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 637 { 638 return true; 639 } 640 641 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 642 { 643 int type = pci_pcie_type(dev); 644 645 return pcie_cap_version(dev) > 1 || 646 type == PCI_EXP_TYPE_ROOT_PORT || 647 (type == PCI_EXP_TYPE_DOWNSTREAM && 648 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 649 } 650 651 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 652 { 653 int type = pci_pcie_type(dev); 654 655 return pcie_cap_version(dev) > 1 || 656 type == PCI_EXP_TYPE_ROOT_PORT || 657 type == PCI_EXP_TYPE_RC_EC; 658 } 659 660 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 661 { 662 if (!pci_is_pcie(dev)) 663 return false; 664 665 switch (pos) { 666 case PCI_EXP_FLAGS_TYPE: 667 return true; 668 case PCI_EXP_DEVCAP: 669 case PCI_EXP_DEVCTL: 670 case PCI_EXP_DEVSTA: 671 return pcie_cap_has_devctl(dev); 672 case PCI_EXP_LNKCAP: 673 case PCI_EXP_LNKCTL: 674 case PCI_EXP_LNKSTA: 675 return pcie_cap_has_lnkctl(dev); 676 case PCI_EXP_SLTCAP: 677 case PCI_EXP_SLTCTL: 678 case PCI_EXP_SLTSTA: 679 return pcie_cap_has_sltctl(dev); 680 case PCI_EXP_RTCTL: 681 case PCI_EXP_RTCAP: 682 case PCI_EXP_RTSTA: 683 return pcie_cap_has_rtctl(dev); 684 case PCI_EXP_DEVCAP2: 685 case PCI_EXP_DEVCTL2: 686 case PCI_EXP_LNKCAP2: 687 case PCI_EXP_LNKCTL2: 688 case PCI_EXP_LNKSTA2: 689 return pcie_cap_version(dev) > 1; 690 default: 691 return false; 692 } 693 } 694 695 static inline int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 696 { 697 if (pos & 3) 698 return -EINVAL; 699 700 if (!pcie_capability_reg_implemented(dev, pos)) 701 return -EINVAL; 702 703 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 704 } 705 706 static inline int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 707 { 708 if (pos & 1) 709 return -EINVAL; 710 711 if (!pcie_capability_reg_implemented(dev, pos)) 712 return 0; 713 714 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 715 } 716 717 static inline int pcie_get_minimum_link(struct pci_dev *dev, 718 enum pci_bus_speed *speed, enum pcie_link_width *width) 719 { 720 *speed = PCI_SPEED_UNKNOWN; 721 *width = PCIE_LNK_WIDTH_UNKNOWN; 722 return (0); 723 } 724 725 static inline int 726 pci_num_vf(struct pci_dev *dev) 727 { 728 return (0); 729 } 730 731 #endif /* _LINUX_PCI_H_ */ 732