1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/module.h> 43 #include <sys/nv.h> 44 #include <sys/pciio.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pci_private.h> 48 49 #include <machine/resource.h> 50 51 #include <linux/list.h> 52 #include <linux/dmapool.h> 53 #include <linux/dma-mapping.h> 54 #include <linux/compiler.h> 55 #include <linux/errno.h> 56 #include <asm/atomic.h> 57 #include <asm/memtype.h> 58 #include <linux/device.h> 59 #include <linux/pci_ids.h> 60 #include <linux/pm.h> 61 62 struct pci_device_id { 63 uint32_t vendor; 64 uint32_t device; 65 uint32_t subvendor; 66 uint32_t subdevice; 67 uint32_t class; 68 uint32_t class_mask; 69 uintptr_t driver_data; 70 }; 71 72 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 73 #define MODULE_DEVICE_TABLE(_bus, _table) \ 74 \ 75 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 76 DEVMETHOD_END \ 77 }; \ 78 \ 79 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 80 "lkpi_" #_bus #_table, \ 81 _ ## _bus ## _ ## _table ## _methods, \ 82 0 \ 83 }; \ 84 \ 85 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 86 0, 0); \ 87 \ 88 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 89 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 90 91 #define PCI_ANY_ID -1U 92 93 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 94 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 95 #define PCI_FUNC(devfn) ((devfn) & 0x07) 96 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 97 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn)) 98 99 #define PCI_VDEVICE(_vendor, _device) \ 100 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 101 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 102 #define PCI_DEVICE(_vendor, _device) \ 103 .vendor = (_vendor), .device = (_device), \ 104 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 105 106 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 107 108 #define PCI_STD_NUM_BARS 6 109 #define PCI_BASE_ADDRESS_0 PCIR_BARS 110 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 111 #define PCI_VENDOR_ID PCIR_VENDOR 112 #define PCI_DEVICE_ID PCIR_DEVICE 113 #define PCI_COMMAND PCIR_COMMAND 114 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 115 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 116 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 117 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 118 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 119 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 120 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 121 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 122 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 123 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 124 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 125 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 126 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 127 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 128 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 129 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 130 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 131 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 132 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 133 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 134 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 135 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 136 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 137 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 138 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 139 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 140 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 141 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 142 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 143 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 144 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 145 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 146 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 147 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 148 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 149 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 150 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 151 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 152 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 153 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 154 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 155 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 156 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 157 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 158 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 159 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 160 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 161 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 162 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 163 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 164 #define PCI_EXP_LNKCTL2_TLS 0x000f 165 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 166 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 167 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 168 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 169 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 170 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 171 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 172 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 173 174 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 175 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 176 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 177 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 178 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 179 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 180 181 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 182 #define PCI_EXP_DEVSTA_TRPND 0x0020 183 184 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 185 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 186 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 187 188 enum pci_bus_speed { 189 PCI_SPEED_UNKNOWN = -1, 190 PCIE_SPEED_2_5GT, 191 PCIE_SPEED_5_0GT, 192 PCIE_SPEED_8_0GT, 193 PCIE_SPEED_16_0GT, 194 PCIE_SPEED_32_0GT, 195 PCIE_SPEED_64_0GT, 196 }; 197 198 enum pcie_link_width { 199 PCIE_LNK_WIDTH_RESRV = 0x00, 200 PCIE_LNK_X1 = 0x01, 201 PCIE_LNK_X2 = 0x02, 202 PCIE_LNK_X4 = 0x04, 203 PCIE_LNK_X8 = 0x08, 204 PCIE_LNK_X12 = 0x0c, 205 PCIE_LNK_X16 = 0x10, 206 PCIE_LNK_X32 = 0x20, 207 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 208 }; 209 210 #define PCIE_LINK_STATE_L0S 0x00000001 211 #define PCIE_LINK_STATE_L1 0x00000002 212 #define PCIE_LINK_STATE_CLKPM 0x00000004 213 214 typedef int pci_power_t; 215 216 #define PCI_D0 PCI_POWERSTATE_D0 217 #define PCI_D1 PCI_POWERSTATE_D1 218 #define PCI_D2 PCI_POWERSTATE_D2 219 #define PCI_D3hot PCI_POWERSTATE_D3 220 #define PCI_D3cold 4 221 222 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 223 224 extern const char *pci_power_names[6]; 225 226 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 227 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 228 229 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 230 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 231 232 #define PCI_L1SS_CTL1 0x8 233 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 234 235 #define PCI_IRQ_LEGACY 0x01 236 #define PCI_IRQ_MSI 0x02 237 #define PCI_IRQ_MSIX 0x04 238 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 239 240 struct pci_dev; 241 242 struct pci_driver { 243 struct list_head node; 244 char *name; 245 const struct pci_device_id *id_table; 246 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 247 void (*remove)(struct pci_dev *dev); 248 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 249 int (*resume) (struct pci_dev *dev); /* Device woken up */ 250 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 251 driver_t bsddriver; 252 devclass_t bsdclass; 253 struct device_driver driver; 254 const struct pci_error_handlers *err_handler; 255 bool isdrm; 256 int bsd_probe_return; 257 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 258 const nvlist_t *pf_config); 259 void (*bsd_iov_uninit)(device_t dev); 260 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 261 const nvlist_t *vf_config); 262 }; 263 264 struct pci_bus { 265 struct pci_dev *self; 266 /* struct pci_bus *parent */ 267 int domain; 268 int number; 269 }; 270 271 extern struct list_head pci_drivers; 272 extern struct list_head pci_devices; 273 extern spinlock_t pci_lock; 274 275 #define __devexit_p(x) x 276 277 #define module_pci_driver(_driver) \ 278 \ 279 static inline int \ 280 _pci_init(void) \ 281 { \ 282 \ 283 return (linux_pci_register_driver(&_driver)); \ 284 } \ 285 \ 286 static inline void \ 287 _pci_exit(void) \ 288 { \ 289 \ 290 linux_pci_unregister_driver(&_driver); \ 291 } \ 292 \ 293 module_init(_pci_init); \ 294 module_exit(_pci_exit) 295 296 struct msi_msg { 297 uint32_t data; 298 }; 299 300 struct pci_msi_desc { 301 struct { 302 bool is_64; 303 } msi_attrib; 304 }; 305 306 struct msi_desc { 307 struct msi_msg msg; 308 struct pci_msi_desc pci; 309 }; 310 311 struct msix_entry { 312 int entry; 313 int vector; 314 }; 315 316 /* 317 * If we find drivers accessing this from multiple KPIs we may have to 318 * refcount objects of this structure. 319 */ 320 struct resource; 321 struct pci_mmio_region { 322 TAILQ_ENTRY(pci_mmio_region) next; 323 struct resource *res; 324 int rid; 325 int type; 326 }; 327 328 struct pci_dev { 329 struct device dev; 330 struct list_head links; 331 struct pci_driver *pdrv; 332 struct pci_bus *bus; 333 struct pci_dev *root; 334 pci_power_t current_state; 335 uint16_t device; 336 uint16_t vendor; 337 uint16_t subsystem_vendor; 338 uint16_t subsystem_device; 339 unsigned int irq; 340 unsigned int devfn; 341 uint32_t class; 342 uint8_t revision; 343 uint8_t msi_cap; 344 uint8_t msix_cap; 345 bool managed; /* devres "pcim_*(). */ 346 bool want_iomap_res; 347 bool msi_enabled; 348 bool msix_enabled; 349 phys_addr_t rom; 350 size_t romlen; 351 struct msi_desc **msi_desc; 352 char *path_name; 353 spinlock_t pcie_cap_lock; 354 355 TAILQ_HEAD(, pci_mmio_region) mmio; 356 }; 357 358 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 359 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 360 unsigned int flags); 361 bool pci_device_is_present(struct pci_dev *pdev); 362 363 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 364 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 365 void *linuxkpi_pci_iomap_range(struct pci_dev *pdev, int mmio_bar, 366 unsigned long mmio_off, unsigned long mmio_size); 367 void *linuxkpi_pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size); 368 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 369 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 370 const char *name); 371 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 372 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 373 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 374 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 375 int nreq); 376 377 /* Internal helper function(s). */ 378 struct pci_dev *lkpinew_pci_dev(device_t); 379 void lkpi_pci_devres_release(struct device *, void *); 380 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 381 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 382 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 383 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 384 385 static inline bool 386 dev_is_pci(struct device *dev) 387 { 388 389 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 390 } 391 392 static inline uint16_t 393 pci_dev_id(struct pci_dev *pdev) 394 { 395 return (PCI_DEVID(pdev->bus->number, pdev->devfn)); 396 } 397 398 static inline int 399 pci_resource_type(struct pci_dev *pdev, int bar) 400 { 401 struct pci_map *pm; 402 403 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 404 if (!pm) 405 return (-1); 406 407 if (PCI_BAR_IO(pm->pm_value)) 408 return (SYS_RES_IOPORT); 409 else 410 return (SYS_RES_MEMORY); 411 } 412 413 /* 414 * All drivers just seem to want to inspect the type not flags. 415 */ 416 static inline int 417 pci_resource_flags(struct pci_dev *pdev, int bar) 418 { 419 int type; 420 421 type = pci_resource_type(pdev, bar); 422 if (type < 0) 423 return (0); 424 return (1 << type); 425 } 426 427 static inline const char * 428 pci_name(struct pci_dev *d) 429 { 430 return d->path_name; 431 } 432 433 static inline void * 434 pci_get_drvdata(struct pci_dev *pdev) 435 { 436 437 return dev_get_drvdata(&pdev->dev); 438 } 439 440 static inline void 441 pci_set_drvdata(struct pci_dev *pdev, void *data) 442 { 443 444 dev_set_drvdata(&pdev->dev, data); 445 } 446 447 static inline struct pci_dev * 448 pci_dev_get(struct pci_dev *pdev) 449 { 450 451 if (pdev != NULL) 452 get_device(&pdev->dev); 453 return (pdev); 454 } 455 456 static __inline void 457 pci_dev_put(struct pci_dev *pdev) 458 { 459 460 if (pdev != NULL) 461 put_device(&pdev->dev); 462 } 463 464 static inline int 465 pci_enable_device(struct pci_dev *pdev) 466 { 467 468 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 469 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 470 return (0); 471 } 472 473 static inline void 474 pci_disable_device(struct pci_dev *pdev) 475 { 476 477 pci_disable_busmaster(pdev->dev.bsddev); 478 } 479 480 static inline int 481 pci_set_master(struct pci_dev *pdev) 482 { 483 484 pci_enable_busmaster(pdev->dev.bsddev); 485 return (0); 486 } 487 488 static inline int 489 pci_set_power_state(struct pci_dev *pdev, int state) 490 { 491 492 pci_set_powerstate(pdev->dev.bsddev, state); 493 return (0); 494 } 495 496 static inline int 497 pci_clear_master(struct pci_dev *pdev) 498 { 499 500 pci_disable_busmaster(pdev->dev.bsddev); 501 return (0); 502 } 503 504 static inline bool 505 pci_is_root_bus(struct pci_bus *pbus) 506 { 507 508 return (pbus->self == NULL); 509 } 510 511 static inline struct pci_dev * 512 pci_upstream_bridge(struct pci_dev *pdev) 513 { 514 515 if (pci_is_root_bus(pdev->bus)) 516 return (NULL); 517 518 /* 519 * If we do not have a (proper) "upstream bridge" set, e.g., we point 520 * to ourselves, try to handle this case on the fly like we do 521 * for pcie_find_root_port(). 522 */ 523 if (pdev == pdev->bus->self) { 524 device_t bridge; 525 526 bridge = device_get_parent(pdev->dev.bsddev); 527 if (bridge == NULL) 528 goto done; 529 bridge = device_get_parent(bridge); 530 if (bridge == NULL) 531 goto done; 532 if (device_get_devclass(device_get_parent(bridge)) != 533 devclass_find("pci")) 534 goto done; 535 536 /* 537 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 538 * for it so it can be returned. 539 */ 540 pdev->bus->self = lkpinew_pci_dev(bridge); 541 } 542 done: 543 return (pdev->bus->self); 544 } 545 546 #define pci_release_region(pdev, bar) linuxkpi_pci_release_region(pdev, bar) 547 #define pci_release_regions(pdev) linuxkpi_pci_release_regions(pdev) 548 #define pci_request_regions(pdev, res_name) \ 549 linuxkpi_pci_request_regions(pdev, res_name) 550 551 static inline void 552 lkpi_pci_disable_msix(struct pci_dev *pdev) 553 { 554 555 pci_release_msi(pdev->dev.bsddev); 556 557 /* 558 * The MSIX IRQ numbers associated with this PCI device are no 559 * longer valid and might be re-assigned. Make sure 560 * lkpi_pci_find_irq_dev() does no longer see them by 561 * resetting their references to zero: 562 */ 563 pdev->dev.irq_start = 0; 564 pdev->dev.irq_end = 0; 565 pdev->msix_enabled = false; 566 } 567 /* Only for consistency. No conflict on that one. */ 568 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 569 570 static inline void 571 lkpi_pci_disable_msi(struct pci_dev *pdev) 572 { 573 574 pci_release_msi(pdev->dev.bsddev); 575 576 pdev->dev.irq_start = 0; 577 pdev->dev.irq_end = 0; 578 pdev->irq = pdev->dev.irq; 579 pdev->msi_enabled = false; 580 } 581 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 582 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 583 584 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 585 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 586 587 static inline bus_addr_t 588 pci_bus_address(struct pci_dev *pdev, int bar) 589 { 590 591 return (pci_resource_start(pdev, bar)); 592 } 593 594 #define PCI_CAP_ID_EXP PCIY_EXPRESS 595 #define PCI_CAP_ID_PCIX PCIY_PCIX 596 #define PCI_CAP_ID_AGP PCIY_AGP 597 #define PCI_CAP_ID_PM PCIY_PMG 598 599 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 600 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 601 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 602 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 603 #define PCI_EXP_LNKSTA PCIER_LINK_STA 604 605 static inline int 606 pci_find_capability(struct pci_dev *pdev, int capid) 607 { 608 int reg; 609 610 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 611 return (0); 612 return (reg); 613 } 614 615 static inline int pci_pcie_cap(struct pci_dev *dev) 616 { 617 return pci_find_capability(dev, PCI_CAP_ID_EXP); 618 } 619 620 static inline int 621 pci_find_ext_capability(struct pci_dev *pdev, int capid) 622 { 623 int reg; 624 625 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 626 return (0); 627 return (reg); 628 } 629 630 #define PCIM_PCAP_PME_SHIFT 11 631 static __inline bool 632 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 633 { 634 struct pci_devinfo *dinfo; 635 pcicfgregs *cfg; 636 637 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 638 return (false); 639 640 dinfo = device_get_ivars(pdev->dev.bsddev); 641 cfg = &dinfo->cfg; 642 643 if (cfg->pp.pp_cap == 0) 644 return (false); 645 646 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 647 return (true); 648 649 return (false); 650 } 651 652 static inline int 653 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 654 { 655 656 if (!pci_enable_aspm) 657 return (-EPERM); 658 659 return (-ENXIO); 660 } 661 662 static inline int 663 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 664 { 665 666 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 667 return (0); 668 } 669 670 static inline int 671 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 672 { 673 674 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 675 return (0); 676 } 677 678 static inline int 679 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 680 { 681 682 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 683 return (0); 684 } 685 686 static inline int 687 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 688 { 689 690 pci_write_config(pdev->dev.bsddev, where, val, 1); 691 return (0); 692 } 693 694 static inline int 695 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 696 { 697 698 pci_write_config(pdev->dev.bsddev, where, val, 2); 699 return (0); 700 } 701 702 static inline int 703 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 704 { 705 706 pci_write_config(pdev->dev.bsddev, where, val, 4); 707 return (0); 708 } 709 710 int linux_pci_register_driver(struct pci_driver *pdrv); 711 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 712 void linux_pci_unregister_driver(struct pci_driver *pdrv); 713 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 714 715 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 716 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 717 718 /* 719 * Enable msix, positive errors indicate actual number of available 720 * vectors. Negative errors are failures. 721 * 722 * NB: define added to prevent this definition of pci_enable_msix from 723 * clashing with the native FreeBSD version. 724 */ 725 #define pci_enable_msix(...) linuxkpi_pci_enable_msix(__VA_ARGS__) 726 727 #define pci_enable_msix_range(...) \ 728 linux_pci_enable_msix_range(__VA_ARGS__) 729 730 static inline int 731 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 732 int minvec, int maxvec) 733 { 734 int nvec = maxvec; 735 int rc; 736 737 if (maxvec < minvec) 738 return (-ERANGE); 739 740 do { 741 rc = pci_enable_msix(dev, entries, nvec); 742 if (rc < 0) { 743 return (rc); 744 } else if (rc > 0) { 745 if (rc < minvec) 746 return (-ENOSPC); 747 nvec = rc; 748 } 749 } while (rc); 750 return (nvec); 751 } 752 753 #define pci_enable_msi(pdev) \ 754 linux_pci_enable_msi(pdev) 755 756 static inline int 757 pci_enable_msi(struct pci_dev *pdev) 758 { 759 760 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 761 } 762 763 static inline int 764 pci_channel_offline(struct pci_dev *pdev) 765 { 766 767 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 768 } 769 770 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 771 { 772 return -ENODEV; 773 } 774 775 static inline void pci_disable_sriov(struct pci_dev *dev) 776 { 777 } 778 779 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \ 780 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) 781 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 782 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 783 #define pci_iounmap(pdev, res) linuxkpi_pci_iounmap(pdev, res) 784 785 static inline void 786 lkpi_pci_save_state(struct pci_dev *pdev) 787 { 788 789 pci_save_state(pdev->dev.bsddev); 790 } 791 792 static inline void 793 lkpi_pci_restore_state(struct pci_dev *pdev) 794 { 795 796 pci_restore_state(pdev->dev.bsddev); 797 } 798 799 #define pci_save_state(dev) lkpi_pci_save_state(dev) 800 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 801 802 static inline int 803 pci_reset_function(struct pci_dev *pdev) 804 { 805 806 return (-ENOSYS); 807 } 808 809 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 810 const struct pci_device_id _table[] __devinitdata 811 812 /* XXX This should not be necessary. */ 813 #define pcix_set_mmrbc(d, v) 0 814 #define pcix_get_max_mmrbc(d) 0 815 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 816 817 #define PCI_DMA_BIDIRECTIONAL 0 818 #define PCI_DMA_TODEVICE 1 819 #define PCI_DMA_FROMDEVICE 2 820 #define PCI_DMA_NONE 3 821 822 #define pci_pool dma_pool 823 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 824 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 825 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 826 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 827 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 828 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 829 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 830 _size, _vaddr, _dma_handle) 831 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 832 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 833 _sg, _nents, (enum dma_data_direction)_dir) 834 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 835 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 836 (_ptr), (_size), (enum dma_data_direction)_dir) 837 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 838 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 839 _addr, _size, (enum dma_data_direction)_dir) 840 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 841 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 842 _sg, _nents, (enum dma_data_direction)_dir) 843 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 844 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 845 _offset, _size, (enum dma_data_direction)_dir) 846 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 847 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 848 _dma_address, _size, (enum dma_data_direction)_dir) 849 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 850 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 851 dma_mapping_error(&(_pdev)->dev, _dma_addr) 852 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 853 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 854 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 855 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 856 #define pci_unmap_addr dma_unmap_addr 857 #define pci_unmap_addr_set dma_unmap_addr_set 858 #define pci_unmap_len dma_unmap_len 859 #define pci_unmap_len_set dma_unmap_len_set 860 861 typedef unsigned int __bitwise pci_channel_state_t; 862 typedef unsigned int __bitwise pci_ers_result_t; 863 864 enum pci_channel_state { 865 pci_channel_io_normal = 1, 866 pci_channel_io_frozen = 2, 867 pci_channel_io_perm_failure = 3, 868 }; 869 870 enum pci_ers_result { 871 PCI_ERS_RESULT_NONE = 1, 872 PCI_ERS_RESULT_CAN_RECOVER = 2, 873 PCI_ERS_RESULT_NEED_RESET = 3, 874 PCI_ERS_RESULT_DISCONNECT = 4, 875 PCI_ERS_RESULT_RECOVERED = 5, 876 }; 877 878 /* PCI bus error event callbacks */ 879 struct pci_error_handlers { 880 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 881 enum pci_channel_state error); 882 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 883 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 884 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 885 void (*resume)(struct pci_dev *dev); 886 }; 887 888 /* FreeBSD does not support SRIOV - yet */ 889 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 890 { 891 return dev; 892 } 893 894 static inline bool pci_is_pcie(struct pci_dev *dev) 895 { 896 return !!pci_pcie_cap(dev); 897 } 898 899 static inline u16 pcie_flags_reg(struct pci_dev *dev) 900 { 901 int pos; 902 u16 reg16; 903 904 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 905 if (!pos) 906 return 0; 907 908 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 909 910 return reg16; 911 } 912 913 static inline int pci_pcie_type(struct pci_dev *dev) 914 { 915 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 916 } 917 918 static inline int pcie_cap_version(struct pci_dev *dev) 919 { 920 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 921 } 922 923 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 924 { 925 int type = pci_pcie_type(dev); 926 927 return pcie_cap_version(dev) > 1 || 928 type == PCI_EXP_TYPE_ROOT_PORT || 929 type == PCI_EXP_TYPE_ENDPOINT || 930 type == PCI_EXP_TYPE_LEG_END; 931 } 932 933 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 934 { 935 return true; 936 } 937 938 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 939 { 940 int type = pci_pcie_type(dev); 941 942 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 943 (type == PCI_EXP_TYPE_DOWNSTREAM && 944 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 945 } 946 947 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 948 { 949 int type = pci_pcie_type(dev); 950 951 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 952 type == PCI_EXP_TYPE_RC_EC; 953 } 954 955 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 956 { 957 if (!pci_is_pcie(dev)) 958 return false; 959 960 switch (pos) { 961 case PCI_EXP_FLAGS_TYPE: 962 return true; 963 case PCI_EXP_DEVCAP: 964 case PCI_EXP_DEVCTL: 965 case PCI_EXP_DEVSTA: 966 return pcie_cap_has_devctl(dev); 967 case PCI_EXP_LNKCAP: 968 case PCI_EXP_LNKCTL: 969 case PCI_EXP_LNKSTA: 970 return pcie_cap_has_lnkctl(dev); 971 case PCI_EXP_SLTCAP: 972 case PCI_EXP_SLTCTL: 973 case PCI_EXP_SLTSTA: 974 return pcie_cap_has_sltctl(dev); 975 case PCI_EXP_RTCTL: 976 case PCI_EXP_RTCAP: 977 case PCI_EXP_RTSTA: 978 return pcie_cap_has_rtctl(dev); 979 case PCI_EXP_DEVCAP2: 980 case PCI_EXP_DEVCTL2: 981 case PCI_EXP_LNKCAP2: 982 case PCI_EXP_LNKCTL2: 983 case PCI_EXP_LNKSTA2: 984 return pcie_cap_version(dev) > 1; 985 default: 986 return false; 987 } 988 } 989 990 static inline int 991 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 992 { 993 *dst = 0; 994 if (pos & 3) 995 return -EINVAL; 996 997 if (!pcie_capability_reg_implemented(dev, pos)) 998 return -EINVAL; 999 1000 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1001 } 1002 1003 static inline int 1004 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1005 { 1006 *dst = 0; 1007 if (pos & 3) 1008 return -EINVAL; 1009 1010 if (!pcie_capability_reg_implemented(dev, pos)) 1011 return -EINVAL; 1012 1013 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1014 } 1015 1016 static inline int 1017 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1018 { 1019 if (pos & 1) 1020 return -EINVAL; 1021 1022 if (!pcie_capability_reg_implemented(dev, pos)) 1023 return 0; 1024 1025 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1026 } 1027 1028 static inline int 1029 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1030 uint16_t clear, uint16_t set) 1031 { 1032 int error; 1033 uint16_t v; 1034 1035 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1036 spin_lock(&dev->pcie_cap_lock); 1037 1038 error = pcie_capability_read_word(dev, pos, &v); 1039 if (error == 0) { 1040 v &= ~clear; 1041 v |= set; 1042 error = pcie_capability_write_word(dev, pos, v); 1043 } 1044 1045 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1046 spin_unlock(&dev->pcie_cap_lock); 1047 1048 return (error); 1049 } 1050 1051 static inline int 1052 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1053 { 1054 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1055 } 1056 1057 static inline int 1058 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1059 { 1060 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1061 } 1062 1063 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1064 enum pci_bus_speed *speed, enum pcie_link_width *width) 1065 { 1066 *speed = PCI_SPEED_UNKNOWN; 1067 *width = PCIE_LNK_WIDTH_UNKNOWN; 1068 return (0); 1069 } 1070 1071 static inline int 1072 pci_num_vf(struct pci_dev *dev) 1073 { 1074 return (0); 1075 } 1076 1077 static inline enum pci_bus_speed 1078 pcie_get_speed_cap(struct pci_dev *dev) 1079 { 1080 device_t root; 1081 uint32_t lnkcap, lnkcap2; 1082 int error, pos; 1083 1084 root = device_get_parent(dev->dev.bsddev); 1085 if (root == NULL) 1086 return (PCI_SPEED_UNKNOWN); 1087 root = device_get_parent(root); 1088 if (root == NULL) 1089 return (PCI_SPEED_UNKNOWN); 1090 root = device_get_parent(root); 1091 if (root == NULL) 1092 return (PCI_SPEED_UNKNOWN); 1093 1094 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1095 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1096 return (PCI_SPEED_UNKNOWN); 1097 1098 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1099 return (PCI_SPEED_UNKNOWN); 1100 1101 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1102 1103 if (lnkcap2) { /* PCIe r3.0-compliant */ 1104 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1105 return (PCIE_SPEED_2_5GT); 1106 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1107 return (PCIE_SPEED_5_0GT); 1108 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1109 return (PCIE_SPEED_8_0GT); 1110 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1111 return (PCIE_SPEED_16_0GT); 1112 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1113 return (PCIE_SPEED_32_0GT); 1114 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1115 return (PCIE_SPEED_64_0GT); 1116 } else { /* pre-r3.0 */ 1117 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1118 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1119 return (PCIE_SPEED_2_5GT); 1120 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1121 return (PCIE_SPEED_5_0GT); 1122 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1123 return (PCIE_SPEED_8_0GT); 1124 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1125 return (PCIE_SPEED_16_0GT); 1126 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1127 return (PCIE_SPEED_32_0GT); 1128 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1129 return (PCIE_SPEED_64_0GT); 1130 } 1131 return (PCI_SPEED_UNKNOWN); 1132 } 1133 1134 static inline enum pcie_link_width 1135 pcie_get_width_cap(struct pci_dev *dev) 1136 { 1137 uint32_t lnkcap; 1138 1139 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1140 if (lnkcap) 1141 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1142 1143 return (PCIE_LNK_WIDTH_UNKNOWN); 1144 } 1145 1146 static inline int 1147 pcie_get_mps(struct pci_dev *dev) 1148 { 1149 return (pci_get_max_payload(dev->dev.bsddev)); 1150 } 1151 1152 static inline uint32_t 1153 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1154 { 1155 1156 switch(spd) { 1157 case PCIE_SPEED_64_0GT: 1158 return (64000 * 128 / 130); 1159 case PCIE_SPEED_32_0GT: 1160 return (32000 * 128 / 130); 1161 case PCIE_SPEED_16_0GT: 1162 return (16000 * 128 / 130); 1163 case PCIE_SPEED_8_0GT: 1164 return (8000 * 128 / 130); 1165 case PCIE_SPEED_5_0GT: 1166 return (5000 * 8 / 10); 1167 case PCIE_SPEED_2_5GT: 1168 return (2500 * 8 / 10); 1169 default: 1170 return (0); 1171 } 1172 } 1173 1174 static inline uint32_t 1175 pcie_bandwidth_available(struct pci_dev *pdev, 1176 struct pci_dev **limiting, 1177 enum pci_bus_speed *speed, 1178 enum pcie_link_width *width) 1179 { 1180 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1181 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1182 1183 if (speed) 1184 *speed = nspeed; 1185 if (width) 1186 *width = nwidth; 1187 1188 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1189 } 1190 1191 static inline bool 1192 pcie_aspm_enabled(struct pci_dev *pdev) 1193 { 1194 return (false); 1195 } 1196 1197 static inline struct pci_dev * 1198 pcie_find_root_port(struct pci_dev *pdev) 1199 { 1200 device_t root; 1201 1202 if (pdev->root != NULL) 1203 return (pdev->root); 1204 1205 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1206 if (root == NULL) 1207 return (NULL); 1208 1209 pdev->root = lkpinew_pci_dev(root); 1210 return (pdev->root); 1211 } 1212 1213 /* This is needed when people rip out the device "HotPlug". */ 1214 static inline void 1215 pci_lock_rescan_remove(void) 1216 { 1217 } 1218 1219 static inline void 1220 pci_unlock_rescan_remove(void) 1221 { 1222 } 1223 1224 static __inline void 1225 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1226 { 1227 } 1228 1229 static inline int 1230 pci_rescan_bus(struct pci_bus *pbus) 1231 { 1232 device_t *devlist, parent; 1233 int devcount, error; 1234 1235 if (!device_is_attached(pbus->self->dev.bsddev)) 1236 return (0); 1237 /* pci_rescan_method() will work on the pcib (parent). */ 1238 error = BUS_RESCAN(pbus->self->dev.bsddev); 1239 if (error != 0) 1240 return (0); 1241 1242 parent = device_get_parent(pbus->self->dev.bsddev); 1243 error = device_get_children(parent, &devlist, &devcount); 1244 if (error != 0) 1245 return (0); 1246 if (devcount != 0) 1247 free(devlist, M_TEMP); 1248 1249 return (devcount); 1250 } 1251 1252 /* 1253 * The following functions can be used to attach/detach the LinuxKPI's 1254 * PCI device runtime. The pci_driver and pci_device_id pointer is 1255 * allowed to be NULL. Other pointers must be all valid. 1256 * The pci_dev structure should be zero-initialized before passed 1257 * to the linux_pci_attach_device function. 1258 */ 1259 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1260 const struct pci_device_id *, struct pci_dev *); 1261 extern int linux_pci_detach_device(struct pci_dev *); 1262 1263 static inline int 1264 pci_dev_present(const struct pci_device_id *cur) 1265 { 1266 while (cur != NULL && (cur->vendor || cur->device)) { 1267 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1268 return (1); 1269 } 1270 cur++; 1271 } 1272 return (0); 1273 } 1274 1275 static inline const struct pci_device_id * 1276 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev) 1277 { 1278 if (ids == NULL) 1279 return (NULL); 1280 1281 for (; 1282 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0; 1283 ids++) 1284 if ((ids->vendor == PCI_ANY_ID || 1285 ids->vendor == pdev->vendor) && 1286 (ids->device == PCI_ANY_ID || 1287 ids->device == pdev->device) && 1288 (ids->subvendor == PCI_ANY_ID || 1289 ids->subvendor == pdev->subsystem_vendor) && 1290 (ids->subdevice == PCI_ANY_ID || 1291 ids->subdevice == pdev->subsystem_device) && 1292 ((ids->class ^ pdev->class) & ids->class_mask) == 0) 1293 return (ids); 1294 1295 return (NULL); 1296 } 1297 1298 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1299 unsigned int bus, unsigned int devfn); 1300 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1301 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1302 1303 static inline int 1304 pci_domain_nr(struct pci_bus *pbus) 1305 { 1306 1307 return (pbus->domain); 1308 } 1309 1310 static inline int 1311 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1312 int pos, uint32_t *val, int len) 1313 { 1314 1315 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1316 return (0); 1317 } 1318 1319 static inline int 1320 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1321 { 1322 uint32_t tmp; 1323 int ret; 1324 1325 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1326 *val = (u16)tmp; 1327 return (ret); 1328 } 1329 1330 static inline int 1331 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1332 { 1333 uint32_t tmp; 1334 int ret; 1335 1336 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1337 *val = (u8)tmp; 1338 return (ret); 1339 } 1340 1341 static inline int 1342 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1343 uint32_t val, int size) 1344 { 1345 1346 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1347 return (0); 1348 } 1349 1350 static inline int 1351 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1352 uint8_t val) 1353 { 1354 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1355 } 1356 1357 static inline int 1358 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1359 uint16_t val) 1360 { 1361 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1362 } 1363 1364 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1365 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1366 1367 /* -------------------------------------------------------------------------- */ 1368 1369 #define pcim_enable_device(pdev) linuxkpi_pcim_enable_device(pdev) 1370 #define pcim_iomap_table(pdev) linuxkpi_pcim_iomap_table(pdev) 1371 #define pcim_iomap_regions(pdev, mask, name) \ 1372 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1373 1374 static inline int 1375 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1376 { 1377 uint32_t requests, req_mask; 1378 int bar, error; 1379 1380 /* Request all the BARs ("regions") we do not iomap. */ 1381 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1382 for (bar = requests = 0; requests != req_mask; bar++) { 1383 if ((req_mask & (1 << bar)) == 0) 1384 continue; 1385 error = pci_request_region(pdev, bar, name); 1386 if (error != 0 && error != -ENODEV) 1387 goto err; 1388 requests |= (1 << bar); 1389 } 1390 1391 error = pcim_iomap_regions(pdev, mask, name); 1392 if (error != 0) 1393 goto err; 1394 1395 return (0); 1396 1397 err: 1398 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1399 if ((requests & (1 << bar)) != 0) 1400 pci_release_region(pdev, bar); 1401 } 1402 1403 return (-EINVAL); 1404 } 1405 1406 /* 1407 * We cannot simply re-define pci_get_device() as we would normally do 1408 * and then hide it in linux_pci.c as too many semi-native drivers still 1409 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1410 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1411 */ 1412 static inline struct pci_dev * 1413 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1414 { 1415 1416 return (lkpi_pci_get_device(vendor, device, odev)); 1417 } 1418 1419 /* This is a FreeBSD extension so we can use bus_*(). */ 1420 static inline void 1421 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1422 { 1423 pdev->want_iomap_res = true; 1424 } 1425 1426 static inline bool 1427 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1428 { 1429 1430 return (false); 1431 } 1432 1433 static inline void * 1434 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1435 { 1436 1437 return (NULL); 1438 } 1439 1440 static inline void 1441 pci_ignore_hotplug(struct pci_dev *pdev) 1442 { 1443 } 1444 1445 static inline const char * 1446 pci_power_name(pci_power_t state) 1447 { 1448 int pstate = state + 1; 1449 1450 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1451 return (pci_power_names[pstate]); 1452 else 1453 return (pci_power_names[0]); 1454 } 1455 1456 static inline int 1457 pcie_get_readrq(struct pci_dev *dev) 1458 { 1459 u16 ctl; 1460 1461 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1462 return (-EINVAL); 1463 1464 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1465 } 1466 1467 static inline bool 1468 pci_is_enabled(struct pci_dev *pdev) 1469 { 1470 1471 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1472 PCIM_CMD_BUSMASTEREN) != 0); 1473 } 1474 1475 static inline int 1476 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1477 { 1478 1479 return (0); 1480 } 1481 1482 static inline int 1483 pci_assign_resource(struct pci_dev *pdev, int bar) 1484 { 1485 1486 return (0); 1487 } 1488 1489 static inline int 1490 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1491 { 1492 1493 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1494 if (vector != 0) 1495 return (-EINVAL); 1496 return (pdev->irq); 1497 } 1498 1499 if (pdev->msix_enabled || pdev->msi_enabled) { 1500 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1501 return (-EINVAL); 1502 return (pdev->dev.irq_start + vector); 1503 } 1504 1505 return (-ENXIO); 1506 } 1507 1508 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1509