1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUX_PCI_H_ 36 #define _LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <sys/rman.h> 47 #include <sys/bus.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 #define MODULE_DEVICE_TABLE(bus, table) 74 75 #define PCI_ANY_ID -1U 76 77 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 78 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 79 #define PCI_FUNC(devfn) ((devfn) & 0x07) 80 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 81 82 #define PCI_VDEVICE(_vendor, _device) \ 83 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 84 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 85 #define PCI_DEVICE(_vendor, _device) \ 86 .vendor = (_vendor), .device = (_device), \ 87 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 88 89 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 90 91 #define PCI_VENDOR_ID PCIR_DEVVENDOR 92 #define PCI_COMMAND PCIR_COMMAND 93 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 94 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 95 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 96 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 97 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 98 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 99 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 100 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 101 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 102 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 103 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 104 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 105 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 106 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 107 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 108 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 109 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 110 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 111 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 112 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 113 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 114 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 115 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 116 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 117 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 118 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 119 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 120 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 121 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 122 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 123 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 124 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 125 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 126 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 127 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 128 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 129 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 130 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 131 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 132 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 133 134 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 135 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 136 #define PCI_EXP_DEVSTA_TRPND 0x0020 137 138 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 139 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 140 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 141 142 enum pci_bus_speed { 143 PCI_SPEED_UNKNOWN = -1, 144 PCIE_SPEED_2_5GT, 145 PCIE_SPEED_5_0GT, 146 PCIE_SPEED_8_0GT, 147 PCIE_SPEED_16_0GT, 148 }; 149 150 enum pcie_link_width { 151 PCIE_LNK_WIDTH_RESRV = 0x00, 152 PCIE_LNK_X1 = 0x01, 153 PCIE_LNK_X2 = 0x02, 154 PCIE_LNK_X4 = 0x04, 155 PCIE_LNK_X8 = 0x08, 156 PCIE_LNK_X12 = 0x0c, 157 PCIE_LNK_X16 = 0x10, 158 PCIE_LNK_X32 = 0x20, 159 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 160 }; 161 162 #define PCIE_LINK_STATE_L0S 0x00000001 163 #define PCIE_LINK_STATE_L1 0x00000002 164 #define PCIE_LINK_STATE_CLKPM 0x00000004 165 166 typedef int pci_power_t; 167 168 #define PCI_D0 PCI_POWERSTATE_D0 169 #define PCI_D1 PCI_POWERSTATE_D1 170 #define PCI_D2 PCI_POWERSTATE_D2 171 #define PCI_D3hot PCI_POWERSTATE_D3 172 #define PCI_D3cold 4 173 174 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 175 176 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 177 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 178 179 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 180 181 struct pci_dev; 182 183 struct pci_driver { 184 struct list_head links; 185 char *name; 186 const struct pci_device_id *id_table; 187 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 188 void (*remove)(struct pci_dev *dev); 189 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 190 int (*resume) (struct pci_dev *dev); /* Device woken up */ 191 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 192 driver_t bsddriver; 193 devclass_t bsdclass; 194 struct device_driver driver; 195 const struct pci_error_handlers *err_handler; 196 bool isdrm; 197 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 198 const nvlist_t *pf_config); 199 void (*bsd_iov_uninit)(device_t dev); 200 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 201 const nvlist_t *vf_config); 202 }; 203 204 struct pci_bus { 205 struct pci_dev *self; 206 int domain; 207 int number; 208 }; 209 210 extern struct list_head pci_drivers; 211 extern struct list_head pci_devices; 212 extern spinlock_t pci_lock; 213 214 #define __devexit_p(x) x 215 216 /* 217 * If we find drivers accessing this from multiple KPIs we may have to 218 * refcount objects of this structure. 219 */ 220 struct pci_mmio_region { 221 TAILQ_ENTRY(pci_mmio_region) next; 222 struct resource *res; 223 int rid; 224 int type; 225 }; 226 227 struct pci_dev { 228 struct device dev; 229 struct list_head links; 230 struct pci_driver *pdrv; 231 struct pci_bus *bus; 232 struct pci_dev *root; 233 uint16_t device; 234 uint16_t vendor; 235 uint16_t subsystem_vendor; 236 uint16_t subsystem_device; 237 unsigned int irq; 238 unsigned int devfn; 239 uint32_t class; 240 uint8_t revision; 241 bool managed; /* devres "pcim_*(). */ 242 bool want_iomap_res; 243 bool msi_enabled; 244 bool msix_enabled; 245 phys_addr_t rom; 246 size_t romlen; 247 248 TAILQ_HEAD(, pci_mmio_region) mmio; 249 }; 250 251 /* We need some meta-struct to keep track of these for devres. */ 252 struct pci_devres { 253 bool enable_io; 254 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 255 uint8_t region_mask; 256 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 257 }; 258 struct pcim_iomap_devres { 259 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 260 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 261 }; 262 263 /* Internal helper function(s). */ 264 struct pci_dev *lkpinew_pci_dev(device_t); 265 void lkpi_pci_devres_release(struct device *, void *); 266 void lkpi_pcim_iomap_table_release(struct device *, void *); 267 268 static inline int 269 pci_resource_type(struct pci_dev *pdev, int bar) 270 { 271 struct pci_map *pm; 272 273 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 274 if (!pm) 275 return (-1); 276 277 if (PCI_BAR_IO(pm->pm_value)) 278 return (SYS_RES_IOPORT); 279 else 280 return (SYS_RES_MEMORY); 281 } 282 283 static inline struct resource_list_entry * 284 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 285 { 286 struct pci_devinfo *dinfo; 287 struct resource_list *rl; 288 289 dinfo = device_get_ivars(pdev->dev.bsddev); 290 rl = &dinfo->resources; 291 return resource_list_find(rl, type, rid); 292 } 293 294 static inline struct resource_list_entry * 295 linux_pci_get_bar(struct pci_dev *pdev, int bar) 296 { 297 int type; 298 299 type = pci_resource_type(pdev, bar); 300 if (type < 0) 301 return (NULL); 302 bar = PCIR_BAR(bar); 303 return (linux_pci_get_rle(pdev, type, bar)); 304 } 305 306 static inline struct device * 307 linux_pci_find_irq_dev(unsigned int irq) 308 { 309 struct pci_dev *pdev; 310 struct device *found; 311 312 found = NULL; 313 spin_lock(&pci_lock); 314 list_for_each_entry(pdev, &pci_devices, links) { 315 if (irq == pdev->dev.irq || 316 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 317 found = &pdev->dev; 318 break; 319 } 320 } 321 spin_unlock(&pci_lock); 322 return (found); 323 } 324 325 /* 326 * All drivers just seem to want to inspect the type not flags. 327 */ 328 static inline int 329 pci_resource_flags(struct pci_dev *pdev, int bar) 330 { 331 int type; 332 333 type = pci_resource_type(pdev, bar); 334 if (type < 0) 335 return (0); 336 return (1 << type); 337 } 338 339 static inline const char * 340 pci_name(struct pci_dev *d) 341 { 342 343 return device_get_desc(d->dev.bsddev); 344 } 345 346 static inline void * 347 pci_get_drvdata(struct pci_dev *pdev) 348 { 349 350 return dev_get_drvdata(&pdev->dev); 351 } 352 353 static inline void 354 pci_set_drvdata(struct pci_dev *pdev, void *data) 355 { 356 357 dev_set_drvdata(&pdev->dev, data); 358 } 359 360 static inline struct pci_dev * 361 pci_dev_get(struct pci_dev *pdev) 362 { 363 364 if (pdev != NULL) 365 get_device(&pdev->dev); 366 return (pdev); 367 } 368 369 static __inline void 370 pci_dev_put(struct pci_dev *pdev) 371 { 372 373 if (pdev != NULL) 374 put_device(&pdev->dev); 375 } 376 377 static inline int 378 pci_enable_device(struct pci_dev *pdev) 379 { 380 381 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 382 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 383 return (0); 384 } 385 386 static inline void 387 pci_disable_device(struct pci_dev *pdev) 388 { 389 390 pci_disable_busmaster(pdev->dev.bsddev); 391 } 392 393 static inline int 394 pci_set_master(struct pci_dev *pdev) 395 { 396 397 pci_enable_busmaster(pdev->dev.bsddev); 398 return (0); 399 } 400 401 static inline int 402 pci_set_power_state(struct pci_dev *pdev, int state) 403 { 404 405 pci_set_powerstate(pdev->dev.bsddev, state); 406 return (0); 407 } 408 409 static inline int 410 pci_clear_master(struct pci_dev *pdev) 411 { 412 413 pci_disable_busmaster(pdev->dev.bsddev); 414 return (0); 415 } 416 417 static inline struct pci_devres * 418 lkpi_pci_devres_get_alloc(struct pci_dev *pdev) 419 { 420 struct pci_devres *dr; 421 422 dr = lkpi_devres_find(&pdev->dev, lkpi_pci_devres_release, NULL, NULL); 423 if (dr == NULL) { 424 dr = lkpi_devres_alloc(lkpi_pci_devres_release, sizeof(*dr), 425 GFP_KERNEL | __GFP_ZERO); 426 if (dr != NULL) 427 lkpi_devres_add(&pdev->dev, dr); 428 } 429 430 return (dr); 431 } 432 static inline struct pci_devres * 433 lkpi_pci_devres_find(struct pci_dev *pdev) 434 { 435 436 if (!pdev->managed) 437 return (NULL); 438 439 return (lkpi_pci_devres_get_alloc(pdev)); 440 } 441 442 static inline int 443 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 444 { 445 struct resource *res; 446 struct pci_devres *dr; 447 struct pci_mmio_region *mmio; 448 int rid; 449 int type; 450 451 type = pci_resource_type(pdev, bar); 452 if (type < 0) 453 return (-ENODEV); 454 rid = PCIR_BAR(bar); 455 res = bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 456 RF_ACTIVE|RF_SHAREABLE); 457 if (res == NULL) { 458 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 459 "bar %d type %d rid %d\n", 460 __func__, bar, type, PCIR_BAR(bar)); 461 return (-ENODEV); 462 } 463 464 /* 465 * It seems there is an implicit devres tracking on these if the device 466 * is managed; otherwise the resources are not automatiaclly freed on 467 * FreeBSD/LinuxKPI tough they should be/are expected to be by Linux 468 * drivers. 469 */ 470 dr = lkpi_pci_devres_find(pdev); 471 if (dr != NULL) { 472 dr->region_mask |= (1 << bar); 473 dr->region_table[bar] = res; 474 } 475 476 /* Even if the device is not managed we need to track it for iomap. */ 477 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 478 mmio->rid = PCIR_BAR(bar); 479 mmio->type = type; 480 mmio->res = res; 481 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 482 483 return (0); 484 } 485 486 static inline void 487 pci_release_region(struct pci_dev *pdev, int bar) 488 { 489 struct resource_list_entry *rle; 490 struct pci_devres *dr; 491 struct pci_mmio_region *mmio, *p; 492 493 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 494 return; 495 496 /* 497 * As we implicitly track the requests we also need to clear them on 498 * release. Do clear before resource release. 499 */ 500 dr = lkpi_pci_devres_find(pdev); 501 if (dr != NULL) { 502 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 503 " region_table res %p != rel->res %p\n", __func__, pdev, 504 bar, dr->region_table[bar], rle->res)); 505 dr->region_table[bar] = NULL; 506 dr->region_mask &= ~(1 << bar); 507 } 508 509 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 510 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 511 continue; 512 TAILQ_REMOVE(&pdev->mmio, mmio, next); 513 free(mmio, M_DEVBUF); 514 } 515 516 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 517 } 518 519 static inline void 520 pci_release_regions(struct pci_dev *pdev) 521 { 522 int i; 523 524 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 525 pci_release_region(pdev, i); 526 } 527 528 static inline int 529 pci_request_regions(struct pci_dev *pdev, const char *res_name) 530 { 531 int error; 532 int i; 533 534 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 535 error = pci_request_region(pdev, i, res_name); 536 if (error && error != -ENODEV) { 537 pci_release_regions(pdev); 538 return (error); 539 } 540 } 541 return (0); 542 } 543 544 static inline void 545 lkpi_pci_disable_msix(struct pci_dev *pdev) 546 { 547 548 pci_release_msi(pdev->dev.bsddev); 549 550 /* 551 * The MSIX IRQ numbers associated with this PCI device are no 552 * longer valid and might be re-assigned. Make sure 553 * linux_pci_find_irq_dev() does no longer see them by 554 * resetting their references to zero: 555 */ 556 pdev->dev.irq_start = 0; 557 pdev->dev.irq_end = 0; 558 pdev->msix_enabled = false; 559 } 560 /* Only for consistency. No conflict on that one. */ 561 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 562 563 static inline void 564 lkpi_pci_disable_msi(struct pci_dev *pdev) 565 { 566 567 pci_release_msi(pdev->dev.bsddev); 568 569 pdev->dev.irq_start = 0; 570 pdev->dev.irq_end = 0; 571 pdev->irq = pdev->dev.irq; 572 pdev->msi_enabled = false; 573 } 574 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 575 576 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 577 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 578 579 static inline bus_addr_t 580 pci_bus_address(struct pci_dev *pdev, int bar) 581 { 582 583 return (pci_resource_start(pdev, bar)); 584 } 585 586 #define PCI_CAP_ID_EXP PCIY_EXPRESS 587 #define PCI_CAP_ID_PCIX PCIY_PCIX 588 #define PCI_CAP_ID_AGP PCIY_AGP 589 #define PCI_CAP_ID_PM PCIY_PMG 590 591 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 592 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 593 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 594 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 595 #define PCI_EXP_LNKSTA PCIER_LINK_STA 596 597 static inline int 598 pci_find_capability(struct pci_dev *pdev, int capid) 599 { 600 int reg; 601 602 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 603 return (0); 604 return (reg); 605 } 606 607 static inline int pci_pcie_cap(struct pci_dev *dev) 608 { 609 return pci_find_capability(dev, PCI_CAP_ID_EXP); 610 } 611 612 static inline int 613 pci_find_ext_capability(struct pci_dev *pdev, int capid) 614 { 615 int reg; 616 617 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 618 return (0); 619 return (reg); 620 } 621 622 #define PCIM_PCAP_PME_SHIFT 11 623 static __inline bool 624 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 625 { 626 struct pci_devinfo *dinfo; 627 pcicfgregs *cfg; 628 629 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 630 return (false); 631 632 dinfo = device_get_ivars(pdev->dev.bsddev); 633 cfg = &dinfo->cfg; 634 635 if (cfg->pp.pp_cap == 0) 636 return (false); 637 638 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 639 return (true); 640 641 return (false); 642 } 643 644 static inline int 645 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 646 { 647 648 if (!pci_enable_aspm) 649 return (-EPERM); 650 651 return (-ENXIO); 652 } 653 654 static inline int 655 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 656 { 657 658 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 659 return (0); 660 } 661 662 static inline int 663 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 664 { 665 666 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 667 return (0); 668 } 669 670 static inline int 671 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 672 { 673 674 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 675 return (0); 676 } 677 678 static inline int 679 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 680 { 681 682 pci_write_config(pdev->dev.bsddev, where, val, 1); 683 return (0); 684 } 685 686 static inline int 687 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 688 { 689 690 pci_write_config(pdev->dev.bsddev, where, val, 2); 691 return (0); 692 } 693 694 static inline int 695 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 696 { 697 698 pci_write_config(pdev->dev.bsddev, where, val, 4); 699 return (0); 700 } 701 702 int linux_pci_register_driver(struct pci_driver *pdrv); 703 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 704 void linux_pci_unregister_driver(struct pci_driver *pdrv); 705 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 706 707 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 708 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 709 710 struct msix_entry { 711 int entry; 712 int vector; 713 }; 714 715 /* 716 * Enable msix, positive errors indicate actual number of available 717 * vectors. Negative errors are failures. 718 * 719 * NB: define added to prevent this definition of pci_enable_msix from 720 * clashing with the native FreeBSD version. 721 */ 722 #define pci_enable_msix(...) \ 723 linux_pci_enable_msix(__VA_ARGS__) 724 725 static inline int 726 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 727 { 728 struct resource_list_entry *rle; 729 int error; 730 int avail; 731 int i; 732 733 avail = pci_msix_count(pdev->dev.bsddev); 734 if (avail < nreq) { 735 if (avail == 0) 736 return -EINVAL; 737 return avail; 738 } 739 avail = nreq; 740 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 741 return error; 742 /* 743 * Handle case where "pci_alloc_msix()" may allocate less 744 * interrupts than available and return with no error: 745 */ 746 if (avail < nreq) { 747 pci_release_msi(pdev->dev.bsddev); 748 return avail; 749 } 750 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 751 pdev->dev.irq_start = rle->start; 752 pdev->dev.irq_end = rle->start + avail; 753 for (i = 0; i < nreq; i++) 754 entries[i].vector = pdev->dev.irq_start + i; 755 pdev->msix_enabled = true; 756 return (0); 757 } 758 759 #define pci_enable_msix_range(...) \ 760 linux_pci_enable_msix_range(__VA_ARGS__) 761 762 static inline int 763 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 764 int minvec, int maxvec) 765 { 766 int nvec = maxvec; 767 int rc; 768 769 if (maxvec < minvec) 770 return (-ERANGE); 771 772 do { 773 rc = pci_enable_msix(dev, entries, nvec); 774 if (rc < 0) { 775 return (rc); 776 } else if (rc > 0) { 777 if (rc < minvec) 778 return (-ENOSPC); 779 nvec = rc; 780 } 781 } while (rc); 782 return (nvec); 783 } 784 785 #define pci_enable_msi(pdev) \ 786 linux_pci_enable_msi(pdev) 787 788 static inline int 789 pci_enable_msi(struct pci_dev *pdev) 790 { 791 struct resource_list_entry *rle; 792 int error; 793 int avail; 794 795 avail = pci_msi_count(pdev->dev.bsddev); 796 if (avail < 1) 797 return -EINVAL; 798 799 avail = 1; /* this function only enable one MSI IRQ */ 800 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 801 return error; 802 803 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 804 pdev->dev.irq_start = rle->start; 805 pdev->dev.irq_end = rle->start + avail; 806 pdev->irq = rle->start; 807 pdev->msi_enabled = true; 808 return (0); 809 } 810 811 static inline int 812 pci_channel_offline(struct pci_dev *pdev) 813 { 814 815 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 816 } 817 818 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 819 { 820 return -ENODEV; 821 } 822 static inline void pci_disable_sriov(struct pci_dev *dev) 823 { 824 } 825 826 static inline struct resource * 827 _lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size __unused) 828 { 829 struct pci_mmio_region *mmio, *p; 830 int type; 831 832 type = pci_resource_type(pdev, bar); 833 if (type < 0) { 834 device_printf(pdev->dev.bsddev, "%s: bar %d type %d\n", 835 __func__, bar, type); 836 return (NULL); 837 } 838 839 /* 840 * Check for duplicate mappings. 841 * This can happen if a driver calls pci_request_region() first. 842 */ 843 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 844 if (mmio->type == type && mmio->rid == PCIR_BAR(bar)) { 845 return (mmio->res); 846 } 847 } 848 849 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 850 mmio->rid = PCIR_BAR(bar); 851 mmio->type = type; 852 mmio->res = bus_alloc_resource_any(pdev->dev.bsddev, mmio->type, 853 &mmio->rid, RF_ACTIVE|RF_SHAREABLE); 854 if (mmio->res == NULL) { 855 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 856 "bar %d type %d rid %d\n", 857 __func__, bar, type, PCIR_BAR(bar)); 858 free(mmio, M_DEVBUF); 859 return (NULL); 860 } 861 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 862 863 return (mmio->res); 864 } 865 866 static inline void * 867 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 868 { 869 struct resource *res; 870 871 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 872 if (res == NULL) 873 return (NULL); 874 /* This is a FreeBSD extension so we can use bus_*(). */ 875 if (pdev->want_iomap_res) 876 return (res); 877 return ((void *)rman_get_bushandle(res)); 878 } 879 880 static inline void 881 pci_iounmap(struct pci_dev *pdev, void *res) 882 { 883 struct pci_mmio_region *mmio, *p; 884 885 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 886 if (res != (void *)rman_get_bushandle(mmio->res)) 887 continue; 888 bus_release_resource(pdev->dev.bsddev, 889 mmio->type, mmio->rid, mmio->res); 890 TAILQ_REMOVE(&pdev->mmio, mmio, next); 891 free(mmio, M_DEVBUF); 892 return; 893 } 894 } 895 896 static inline void 897 lkpi_pci_save_state(struct pci_dev *pdev) 898 { 899 900 pci_save_state(pdev->dev.bsddev); 901 } 902 903 static inline void 904 lkpi_pci_restore_state(struct pci_dev *pdev) 905 { 906 907 pci_restore_state(pdev->dev.bsddev); 908 } 909 910 #define pci_save_state(dev) lkpi_pci_save_state(dev) 911 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 912 913 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 914 const struct pci_device_id _table[] __devinitdata 915 916 /* XXX This should not be necessary. */ 917 #define pcix_set_mmrbc(d, v) 0 918 #define pcix_get_max_mmrbc(d) 0 919 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 920 921 #define PCI_DMA_BIDIRECTIONAL 0 922 #define PCI_DMA_TODEVICE 1 923 #define PCI_DMA_FROMDEVICE 2 924 #define PCI_DMA_NONE 3 925 926 #define pci_pool dma_pool 927 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 928 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 929 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 930 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 931 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 932 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 933 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 934 _size, _vaddr, _dma_handle) 935 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 936 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 937 _sg, _nents, (enum dma_data_direction)_dir) 938 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 939 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 940 (_ptr), (_size), (enum dma_data_direction)_dir) 941 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 942 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 943 _addr, _size, (enum dma_data_direction)_dir) 944 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 945 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 946 _sg, _nents, (enum dma_data_direction)_dir) 947 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 948 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 949 _offset, _size, (enum dma_data_direction)_dir) 950 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 951 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 952 _dma_address, _size, (enum dma_data_direction)_dir) 953 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 954 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 955 dma_mapping_error(&(_pdev)->dev, _dma_addr) 956 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 957 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 958 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 959 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 960 #define pci_unmap_addr dma_unmap_addr 961 #define pci_unmap_addr_set dma_unmap_addr_set 962 #define pci_unmap_len dma_unmap_len 963 #define pci_unmap_len_set dma_unmap_len_set 964 965 typedef unsigned int __bitwise pci_channel_state_t; 966 typedef unsigned int __bitwise pci_ers_result_t; 967 968 enum pci_channel_state { 969 pci_channel_io_normal = 1, 970 pci_channel_io_frozen = 2, 971 pci_channel_io_perm_failure = 3, 972 }; 973 974 enum pci_ers_result { 975 PCI_ERS_RESULT_NONE = 1, 976 PCI_ERS_RESULT_CAN_RECOVER = 2, 977 PCI_ERS_RESULT_NEED_RESET = 3, 978 PCI_ERS_RESULT_DISCONNECT = 4, 979 PCI_ERS_RESULT_RECOVERED = 5, 980 }; 981 982 /* PCI bus error event callbacks */ 983 struct pci_error_handlers { 984 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 985 enum pci_channel_state error); 986 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 987 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 988 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 989 void (*resume)(struct pci_dev *dev); 990 }; 991 992 /* FreeBSD does not support SRIOV - yet */ 993 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 994 { 995 return dev; 996 } 997 998 static inline bool pci_is_pcie(struct pci_dev *dev) 999 { 1000 return !!pci_pcie_cap(dev); 1001 } 1002 1003 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1004 { 1005 int pos; 1006 u16 reg16; 1007 1008 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1009 if (!pos) 1010 return 0; 1011 1012 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1013 1014 return reg16; 1015 } 1016 1017 static inline int pci_pcie_type(struct pci_dev *dev) 1018 { 1019 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1020 } 1021 1022 static inline int pcie_cap_version(struct pci_dev *dev) 1023 { 1024 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1025 } 1026 1027 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1028 { 1029 int type = pci_pcie_type(dev); 1030 1031 return pcie_cap_version(dev) > 1 || 1032 type == PCI_EXP_TYPE_ROOT_PORT || 1033 type == PCI_EXP_TYPE_ENDPOINT || 1034 type == PCI_EXP_TYPE_LEG_END; 1035 } 1036 1037 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1038 { 1039 return true; 1040 } 1041 1042 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1043 { 1044 int type = pci_pcie_type(dev); 1045 1046 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1047 (type == PCI_EXP_TYPE_DOWNSTREAM && 1048 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1049 } 1050 1051 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1052 { 1053 int type = pci_pcie_type(dev); 1054 1055 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1056 type == PCI_EXP_TYPE_RC_EC; 1057 } 1058 1059 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1060 { 1061 if (!pci_is_pcie(dev)) 1062 return false; 1063 1064 switch (pos) { 1065 case PCI_EXP_FLAGS_TYPE: 1066 return true; 1067 case PCI_EXP_DEVCAP: 1068 case PCI_EXP_DEVCTL: 1069 case PCI_EXP_DEVSTA: 1070 return pcie_cap_has_devctl(dev); 1071 case PCI_EXP_LNKCAP: 1072 case PCI_EXP_LNKCTL: 1073 case PCI_EXP_LNKSTA: 1074 return pcie_cap_has_lnkctl(dev); 1075 case PCI_EXP_SLTCAP: 1076 case PCI_EXP_SLTCTL: 1077 case PCI_EXP_SLTSTA: 1078 return pcie_cap_has_sltctl(dev); 1079 case PCI_EXP_RTCTL: 1080 case PCI_EXP_RTCAP: 1081 case PCI_EXP_RTSTA: 1082 return pcie_cap_has_rtctl(dev); 1083 case PCI_EXP_DEVCAP2: 1084 case PCI_EXP_DEVCTL2: 1085 case PCI_EXP_LNKCAP2: 1086 case PCI_EXP_LNKCTL2: 1087 case PCI_EXP_LNKSTA2: 1088 return pcie_cap_version(dev) > 1; 1089 default: 1090 return false; 1091 } 1092 } 1093 1094 static inline int 1095 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1096 { 1097 if (pos & 3) 1098 return -EINVAL; 1099 1100 if (!pcie_capability_reg_implemented(dev, pos)) 1101 return -EINVAL; 1102 1103 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1104 } 1105 1106 static inline int 1107 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1108 { 1109 if (pos & 3) 1110 return -EINVAL; 1111 1112 if (!pcie_capability_reg_implemented(dev, pos)) 1113 return -EINVAL; 1114 1115 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1116 } 1117 1118 static inline int 1119 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1120 { 1121 if (pos & 1) 1122 return -EINVAL; 1123 1124 if (!pcie_capability_reg_implemented(dev, pos)) 1125 return 0; 1126 1127 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1128 } 1129 1130 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1131 enum pci_bus_speed *speed, enum pcie_link_width *width) 1132 { 1133 *speed = PCI_SPEED_UNKNOWN; 1134 *width = PCIE_LNK_WIDTH_UNKNOWN; 1135 return (0); 1136 } 1137 1138 static inline int 1139 pci_num_vf(struct pci_dev *dev) 1140 { 1141 return (0); 1142 } 1143 1144 static inline enum pci_bus_speed 1145 pcie_get_speed_cap(struct pci_dev *dev) 1146 { 1147 device_t root; 1148 uint32_t lnkcap, lnkcap2; 1149 int error, pos; 1150 1151 root = device_get_parent(dev->dev.bsddev); 1152 if (root == NULL) 1153 return (PCI_SPEED_UNKNOWN); 1154 root = device_get_parent(root); 1155 if (root == NULL) 1156 return (PCI_SPEED_UNKNOWN); 1157 root = device_get_parent(root); 1158 if (root == NULL) 1159 return (PCI_SPEED_UNKNOWN); 1160 1161 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1162 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1163 return (PCI_SPEED_UNKNOWN); 1164 1165 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1166 return (PCI_SPEED_UNKNOWN); 1167 1168 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1169 1170 if (lnkcap2) { /* PCIe r3.0-compliant */ 1171 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1172 return (PCIE_SPEED_2_5GT); 1173 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1174 return (PCIE_SPEED_5_0GT); 1175 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1176 return (PCIE_SPEED_8_0GT); 1177 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1178 return (PCIE_SPEED_16_0GT); 1179 } else { /* pre-r3.0 */ 1180 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1181 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1182 return (PCIE_SPEED_2_5GT); 1183 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1184 return (PCIE_SPEED_5_0GT); 1185 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1186 return (PCIE_SPEED_8_0GT); 1187 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1188 return (PCIE_SPEED_16_0GT); 1189 } 1190 return (PCI_SPEED_UNKNOWN); 1191 } 1192 1193 static inline enum pcie_link_width 1194 pcie_get_width_cap(struct pci_dev *dev) 1195 { 1196 uint32_t lnkcap; 1197 1198 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1199 if (lnkcap) 1200 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1201 1202 return (PCIE_LNK_WIDTH_UNKNOWN); 1203 } 1204 1205 static inline int 1206 pcie_get_mps(struct pci_dev *dev) 1207 { 1208 return (pci_get_max_payload(dev->dev.bsddev)); 1209 } 1210 1211 static inline uint32_t 1212 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1213 { 1214 1215 switch(spd) { 1216 case PCIE_SPEED_16_0GT: 1217 return (16000 * 128 / 130); 1218 case PCIE_SPEED_8_0GT: 1219 return (8000 * 128 / 130); 1220 case PCIE_SPEED_5_0GT: 1221 return (5000 * 8 / 10); 1222 case PCIE_SPEED_2_5GT: 1223 return (2500 * 8 / 10); 1224 default: 1225 return (0); 1226 } 1227 } 1228 1229 static inline uint32_t 1230 pcie_bandwidth_available(struct pci_dev *pdev, 1231 struct pci_dev **limiting, 1232 enum pci_bus_speed *speed, 1233 enum pcie_link_width *width) 1234 { 1235 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1236 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1237 1238 if (speed) 1239 *speed = nspeed; 1240 if (width) 1241 *width = nwidth; 1242 1243 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1244 } 1245 1246 static inline struct pci_dev * 1247 pcie_find_root_port(struct pci_dev *pdev) 1248 { 1249 device_t root; 1250 1251 if (pdev->root != NULL) 1252 return (pdev->root); 1253 1254 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1255 if (root == NULL) 1256 return (NULL); 1257 1258 pdev->root = lkpinew_pci_dev(root); 1259 return (pdev->root); 1260 } 1261 1262 /* This is needed when people rip out the device "HotPlug". */ 1263 static inline void 1264 pci_lock_rescan_remove(void) 1265 { 1266 } 1267 1268 static inline void 1269 pci_unlock_rescan_remove(void) 1270 { 1271 } 1272 1273 static __inline void 1274 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1275 { 1276 } 1277 1278 /* 1279 * The following functions can be used to attach/detach the LinuxKPI's 1280 * PCI device runtime. The pci_driver and pci_device_id pointer is 1281 * allowed to be NULL. Other pointers must be all valid. 1282 * The pci_dev structure should be zero-initialized before passed 1283 * to the linux_pci_attach_device function. 1284 */ 1285 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1286 const struct pci_device_id *, struct pci_dev *); 1287 extern int linux_pci_detach_device(struct pci_dev *); 1288 1289 static inline int 1290 pci_dev_present(const struct pci_device_id *cur) 1291 { 1292 while (cur != NULL && (cur->vendor || cur->device)) { 1293 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1294 return (1); 1295 } 1296 cur++; 1297 } 1298 return (0); 1299 } 1300 1301 static inline bool 1302 pci_is_root_bus(struct pci_bus *pbus) 1303 { 1304 1305 return (pbus->self == NULL); 1306 } 1307 1308 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1309 unsigned int bus, unsigned int devfn); 1310 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1311 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1312 1313 static inline int 1314 pci_domain_nr(struct pci_bus *pbus) 1315 { 1316 1317 return (pbus->domain); 1318 } 1319 1320 static inline int 1321 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1322 int pos, uint32_t *val, int len) 1323 { 1324 1325 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1326 return (0); 1327 } 1328 1329 static inline int 1330 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1331 { 1332 uint32_t tmp; 1333 int ret; 1334 1335 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1336 *val = (u16)tmp; 1337 return (ret); 1338 } 1339 1340 static inline int 1341 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1342 { 1343 uint32_t tmp; 1344 int ret; 1345 1346 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1347 *val = (u8)tmp; 1348 return (ret); 1349 } 1350 1351 static inline int 1352 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1353 uint32_t val, int size) 1354 { 1355 1356 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1357 return (0); 1358 } 1359 1360 static inline int 1361 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1362 uint8_t val) 1363 { 1364 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1365 } 1366 1367 static inline int 1368 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1369 uint16_t val) 1370 { 1371 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1372 } 1373 1374 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1375 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1376 1377 /* -------------------------------------------------------------------------- */ 1378 1379 static inline int 1380 pcim_enable_device(struct pci_dev *pdev) 1381 { 1382 struct pci_devres *dr; 1383 int error; 1384 1385 /* Here we cannot run through the pdev->managed check. */ 1386 dr = lkpi_pci_devres_get_alloc(pdev); 1387 if (dr == NULL) 1388 return (-ENOMEM); 1389 1390 /* If resources were enabled before do not do it again. */ 1391 if (dr->enable_io) 1392 return (0); 1393 1394 error = pci_enable_device(pdev); 1395 if (error == 0) 1396 dr->enable_io = true; 1397 1398 /* This device is not managed. */ 1399 pdev->managed = true; 1400 1401 return (error); 1402 } 1403 1404 static inline struct pcim_iomap_devres * 1405 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev) 1406 { 1407 struct pcim_iomap_devres *dr; 1408 1409 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release, 1410 NULL, NULL); 1411 if (dr == NULL) { 1412 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release, 1413 sizeof(*dr), GFP_KERNEL | __GFP_ZERO); 1414 if (dr != NULL) 1415 lkpi_devres_add(&pdev->dev, dr); 1416 } 1417 1418 if (dr == NULL) 1419 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__); 1420 1421 return (dr); 1422 } 1423 1424 static inline void __iomem ** 1425 pcim_iomap_table(struct pci_dev *pdev) 1426 { 1427 struct pcim_iomap_devres *dr; 1428 1429 dr = lkpi_pcim_iomap_devres_find(pdev); 1430 if (dr == NULL) 1431 return (NULL); 1432 1433 /* 1434 * If the driver has manually set a flag to be able to request the 1435 * resource to use bus_read/write_<n>, return the shadow table. 1436 */ 1437 if (pdev->want_iomap_res) 1438 return ((void **)dr->res_table); 1439 1440 /* This is the Linux default. */ 1441 return (dr->mmio_table); 1442 } 1443 1444 static inline int 1445 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1446 { 1447 struct pcim_iomap_devres *dr; 1448 void *res; 1449 uint32_t mappings, requests, req_mask; 1450 int bar, error; 1451 1452 dr = lkpi_pcim_iomap_devres_find(pdev); 1453 if (dr == NULL) 1454 return (-ENOMEM); 1455 1456 /* Request all the BARs ("regions") we do not iomap. */ 1457 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1458 for (bar = requests = 0; requests != req_mask; bar++) { 1459 if ((req_mask & (1 << bar)) == 0) 1460 continue; 1461 error = pci_request_region(pdev, bar, name); 1462 if (error != 0 && error != -ENODEV) 1463 goto err; 1464 requests |= (1 << bar); 1465 } 1466 1467 /* Now iomap all the requested (by "mask") ones. */ 1468 for (bar = mappings = 0; mappings != mask; bar++) { 1469 if ((mask & (1 << bar)) == 0) 1470 continue; 1471 1472 /* Request double is not allowed. */ 1473 if (dr->mmio_table[bar] != NULL) { 1474 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1475 __func__, bar, dr->mmio_table[bar]); 1476 goto err; 1477 } 1478 1479 res = _lkpi_pci_iomap(pdev, bar, 0); 1480 if (res == NULL) 1481 goto err; 1482 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1483 dr->res_table[bar] = res; 1484 1485 mappings |= (1 << bar); 1486 } 1487 1488 return (0); 1489 1490 err: 1491 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1492 if ((mappings & (1 << bar)) != 0) { 1493 res = dr->mmio_table[bar]; 1494 if (res == NULL) 1495 continue; 1496 pci_iounmap(pdev, res); 1497 } else if ((requests & (1 << bar)) != 0) { 1498 pci_release_region(pdev, bar); 1499 } 1500 } 1501 1502 return (-EINVAL); 1503 } 1504 1505 /* This is a FreeBSD extension so we can use bus_*(). */ 1506 static inline void 1507 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1508 { 1509 pdev->want_iomap_res = true; 1510 } 1511 1512 #endif /* _LINUX_PCI_H_ */ 1513