xref: /freebsd/sys/compat/linuxkpi/common/include/linux/pci.h (revision 2f513db72b034fd5ef7f080b11be5c711c15186a)
1 /*-
2  * Copyright (c) 2010 Isilon Systems, Inc.
3  * Copyright (c) 2010 iX Systems, Inc.
4  * Copyright (c) 2010 Panasas, Inc.
5  * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice unmodified, this list of conditions, and the following
13  *    disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  *
29  * $FreeBSD$
30  */
31 #ifndef	_LINUX_PCI_H_
32 #define	_LINUX_PCI_H_
33 
34 #define	CONFIG_PCI_MSI
35 
36 #include <linux/types.h>
37 
38 #include <sys/param.h>
39 #include <sys/bus.h>
40 #include <sys/pciio.h>
41 #include <sys/rman.h>
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pci_private.h>
45 
46 #include <machine/resource.h>
47 
48 #include <linux/list.h>
49 #include <linux/dmapool.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/compiler.h>
52 #include <linux/errno.h>
53 #include <asm/atomic.h>
54 #include <linux/device.h>
55 
56 struct pci_device_id {
57 	uint32_t	vendor;
58 	uint32_t	device;
59 	uint32_t	subvendor;
60 	uint32_t	subdevice;
61 	uint32_t	class;
62 	uint32_t	class_mask;
63 	uintptr_t	driver_data;
64 };
65 
66 #define	MODULE_DEVICE_TABLE(bus, table)
67 
68 #define	PCI_BASE_CLASS_DISPLAY		0x03
69 #define	PCI_CLASS_DISPLAY_VGA		0x0300
70 #define	PCI_CLASS_DISPLAY_OTHER		0x0380
71 #define	PCI_BASE_CLASS_BRIDGE		0x06
72 #define	PCI_CLASS_BRIDGE_ISA		0x0601
73 
74 #define	PCI_ANY_ID			-1U
75 #define	PCI_VENDOR_ID_APPLE		0x106b
76 #define	PCI_VENDOR_ID_ASUSTEK		0x1043
77 #define	PCI_VENDOR_ID_ATI		0x1002
78 #define	PCI_VENDOR_ID_DELL		0x1028
79 #define	PCI_VENDOR_ID_HP		0x103c
80 #define	PCI_VENDOR_ID_IBM		0x1014
81 #define	PCI_VENDOR_ID_INTEL		0x8086
82 #define	PCI_VENDOR_ID_MELLANOX			0x15b3
83 #define	PCI_VENDOR_ID_REDHAT_QUMRANET	0x1af4
84 #define	PCI_VENDOR_ID_SERVERWORKS	0x1166
85 #define	PCI_VENDOR_ID_SONY		0x104d
86 #define	PCI_VENDOR_ID_TOPSPIN			0x1867
87 #define	PCI_VENDOR_ID_VIA		0x1106
88 #define	PCI_SUBVENDOR_ID_REDHAT_QUMRANET	0x1af4
89 #define	PCI_DEVICE_ID_ATI_RADEON_QY	0x5159
90 #define	PCI_DEVICE_ID_MELLANOX_TAVOR		0x5a44
91 #define	PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE	0x5a46
92 #define	PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT	0x6278
93 #define	PCI_DEVICE_ID_MELLANOX_ARBEL		0x6282
94 #define	PCI_DEVICE_ID_MELLANOX_SINAI_OLD	0x5e8c
95 #define	PCI_DEVICE_ID_MELLANOX_SINAI		0x6274
96 #define	PCI_SUBDEVICE_ID_QEMU		0x1100
97 
98 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
99 #define PCI_SLOT(devfn)		(((devfn) >> 3) & 0x1f)
100 #define PCI_FUNC(devfn)		((devfn) & 0x07)
101 #define	PCI_BUS_NUM(devfn)	(((devfn) >> 8) & 0xff)
102 
103 #define PCI_VDEVICE(_vendor, _device)					\
104 	    .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device),	\
105 	    .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
106 #define	PCI_DEVICE(_vendor, _device)					\
107 	    .vendor = (_vendor), .device = (_device),			\
108 	    .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
109 
110 #define	to_pci_dev(n)	container_of(n, struct pci_dev, dev)
111 
112 #define	PCI_VENDOR_ID		PCIR_DEVVENDOR
113 #define	PCI_COMMAND		PCIR_COMMAND
114 #define	PCI_EXP_DEVCTL		PCIER_DEVICE_CTL		/* Device Control */
115 #define	PCI_EXP_LNKCTL		PCIER_LINK_CTL			/* Link Control */
116 #define	PCI_EXP_FLAGS_TYPE	PCIEM_FLAGS_TYPE		/* Device/Port type */
117 #define	PCI_EXP_DEVCAP		PCIER_DEVICE_CAP		/* Device capabilities */
118 #define	PCI_EXP_DEVSTA		PCIER_DEVICE_STA		/* Device Status */
119 #define	PCI_EXP_LNKCAP		PCIER_LINK_CAP			/* Link Capabilities */
120 #define	PCI_EXP_LNKSTA		PCIER_LINK_STA			/* Link Status */
121 #define	PCI_EXP_SLTCAP		PCIER_SLOT_CAP			/* Slot Capabilities */
122 #define	PCI_EXP_SLTCTL		PCIER_SLOT_CTL			/* Slot Control */
123 #define	PCI_EXP_SLTSTA		PCIER_SLOT_STA			/* Slot Status */
124 #define	PCI_EXP_RTCTL		PCIER_ROOT_CTL			/* Root Control */
125 #define	PCI_EXP_RTCAP		PCIER_ROOT_CAP			/* Root Capabilities */
126 #define	PCI_EXP_RTSTA		PCIER_ROOT_STA			/* Root Status */
127 #define	PCI_EXP_DEVCAP2		PCIER_DEVICE_CAP2		/* Device Capabilities 2 */
128 #define	PCI_EXP_DEVCTL2		PCIER_DEVICE_CTL2		/* Device Control 2 */
129 #define	PCI_EXP_LNKCAP2		PCIER_LINK_CAP2			/* Link Capabilities 2 */
130 #define	PCI_EXP_LNKCTL2		PCIER_LINK_CTL2			/* Link Control 2 */
131 #define	PCI_EXP_LNKSTA2		PCIER_LINK_STA2			/* Link Status 2 */
132 #define	PCI_EXP_FLAGS		PCIER_FLAGS			/* Capabilities register */
133 #define	PCI_EXP_FLAGS_VERS	PCIEM_FLAGS_VERSION		/* Capability version */
134 #define	PCI_EXP_TYPE_ROOT_PORT	PCIEM_TYPE_ROOT_PORT		/* Root Port */
135 #define	PCI_EXP_TYPE_ENDPOINT	PCIEM_TYPE_ENDPOINT		/* Express Endpoint */
136 #define	PCI_EXP_TYPE_LEG_END	PCIEM_TYPE_LEGACY_ENDPOINT	/* Legacy Endpoint */
137 #define	PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT	/* Downstream Port */
138 #define	PCI_EXP_FLAGS_SLOT	PCIEM_FLAGS_SLOT		/* Slot implemented */
139 #define	PCI_EXP_TYPE_RC_EC	PCIEM_TYPE_ROOT_EC		/* Root Complex Event Collector */
140 #define	PCI_EXP_LNKCAP_SLS_2_5GB 0x01	/* Supported Link Speed 2.5GT/s */
141 #define	PCI_EXP_LNKCAP_SLS_5_0GB 0x02	/* Supported Link Speed 5.0GT/s */
142 #define	PCI_EXP_LNKCAP_SLS_8_0GB 0x04	/* Supported Link Speed 8.0GT/s */
143 #define	PCI_EXP_LNKCAP_SLS_16_0GB 0x08	/* Supported Link Speed 16.0GT/s */
144 #define	PCI_EXP_LNKCAP_MLW	0x03f0	/* Maximum Link Width */
145 #define	PCI_EXP_LNKCAP2_SLS_2_5GB 0x02	/* Supported Link Speed 2.5GT/s */
146 #define	PCI_EXP_LNKCAP2_SLS_5_0GB 0x04	/* Supported Link Speed 5.0GT/s */
147 #define	PCI_EXP_LNKCAP2_SLS_8_0GB 0x08	/* Supported Link Speed 8.0GT/s */
148 #define	PCI_EXP_LNKCAP2_SLS_16_0GB 0x10	/* Supported Link Speed 16.0GT/s */
149 
150 #define PCI_EXP_LNKCTL_HAWD	PCIEM_LINK_CTL_HAWD
151 #define PCI_EXP_LNKCAP_CLKPM	0x00040000
152 #define PCI_EXP_DEVSTA_TRPND	0x0020
153 
154 #define	IORESOURCE_MEM	(1 << SYS_RES_MEMORY)
155 #define	IORESOURCE_IO	(1 << SYS_RES_IOPORT)
156 #define	IORESOURCE_IRQ	(1 << SYS_RES_IRQ)
157 
158 enum pci_bus_speed {
159 	PCI_SPEED_UNKNOWN = -1,
160 	PCIE_SPEED_2_5GT,
161 	PCIE_SPEED_5_0GT,
162 	PCIE_SPEED_8_0GT,
163 	PCIE_SPEED_16_0GT,
164 };
165 
166 enum pcie_link_width {
167 	PCIE_LNK_WIDTH_RESRV	= 0x00,
168 	PCIE_LNK_X1		= 0x01,
169 	PCIE_LNK_X2		= 0x02,
170 	PCIE_LNK_X4		= 0x04,
171 	PCIE_LNK_X8		= 0x08,
172 	PCIE_LNK_X12		= 0x0c,
173 	PCIE_LNK_X16		= 0x10,
174 	PCIE_LNK_X32		= 0x20,
175 	PCIE_LNK_WIDTH_UNKNOWN	= 0xff,
176 };
177 
178 typedef int pci_power_t;
179 
180 #define PCI_D0	PCI_POWERSTATE_D0
181 #define PCI_D1	PCI_POWERSTATE_D1
182 #define PCI_D2	PCI_POWERSTATE_D2
183 #define PCI_D3hot	PCI_POWERSTATE_D3
184 #define PCI_D3cold	4
185 
186 #define PCI_POWER_ERROR	PCI_POWERSTATE_UNKNOWN
187 
188 struct pci_dev;
189 
190 struct pci_driver {
191 	struct list_head		links;
192 	char				*name;
193 	const struct pci_device_id		*id_table;
194 	int  (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
195 	void (*remove)(struct pci_dev *dev);
196 	int  (*suspend) (struct pci_dev *dev, pm_message_t state);	/* Device suspended */
197 	int  (*resume) (struct pci_dev *dev);		/* Device woken up */
198 	void (*shutdown) (struct pci_dev *dev);		/* Device shutdown */
199 	driver_t			bsddriver;
200 	devclass_t			bsdclass;
201 	struct device_driver		driver;
202 	const struct pci_error_handlers       *err_handler;
203 	bool				isdrm;
204 };
205 
206 struct pci_bus {
207 	struct pci_dev	*self;
208 	int		domain;
209 	int		number;
210 };
211 
212 extern struct list_head pci_drivers;
213 extern struct list_head pci_devices;
214 extern spinlock_t pci_lock;
215 
216 #define	__devexit_p(x)	x
217 
218 struct pci_dev {
219 	struct device		dev;
220 	struct list_head	links;
221 	struct pci_driver	*pdrv;
222 	struct pci_bus		*bus;
223 	uint16_t		device;
224 	uint16_t		vendor;
225 	uint16_t		subsystem_vendor;
226 	uint16_t		subsystem_device;
227 	unsigned int		irq;
228 	unsigned int		devfn;
229 	uint32_t		class;
230 	uint8_t			revision;
231 	bool			msi_enabled;
232 };
233 
234 static inline struct resource_list_entry *
235 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid)
236 {
237 	struct pci_devinfo *dinfo;
238 	struct resource_list *rl;
239 
240 	dinfo = device_get_ivars(pdev->dev.bsddev);
241 	rl = &dinfo->resources;
242 	return resource_list_find(rl, type, rid);
243 }
244 
245 static inline struct resource_list_entry *
246 linux_pci_get_bar(struct pci_dev *pdev, int bar)
247 {
248 	struct resource_list_entry *rle;
249 
250 	bar = PCIR_BAR(bar);
251 	if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL)
252 		rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar);
253 	return (rle);
254 }
255 
256 static inline struct device *
257 linux_pci_find_irq_dev(unsigned int irq)
258 {
259 	struct pci_dev *pdev;
260 	struct device *found;
261 
262 	found = NULL;
263 	spin_lock(&pci_lock);
264 	list_for_each_entry(pdev, &pci_devices, links) {
265 		if (irq == pdev->dev.irq ||
266 		    (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) {
267 			found = &pdev->dev;
268 			break;
269 		}
270 	}
271 	spin_unlock(&pci_lock);
272 	return (found);
273 }
274 
275 static inline int
276 pci_resource_type(struct pci_dev *pdev, int bar)
277 {
278 	struct pci_map *pm;
279 
280 	pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar));
281 	if (!pm)
282 		return (-1);
283 
284 	if (PCI_BAR_IO(pm->pm_value))
285 		return (SYS_RES_IOPORT);
286 	else
287 		return (SYS_RES_MEMORY);
288 }
289 
290 /*
291  * All drivers just seem to want to inspect the type not flags.
292  */
293 static inline int
294 pci_resource_flags(struct pci_dev *pdev, int bar)
295 {
296 	int type;
297 
298 	type = pci_resource_type(pdev, bar);
299 	if (type < 0)
300 		return (0);
301 	return (1 << type);
302 }
303 
304 static inline const char *
305 pci_name(struct pci_dev *d)
306 {
307 
308 	return device_get_desc(d->dev.bsddev);
309 }
310 
311 static inline void *
312 pci_get_drvdata(struct pci_dev *pdev)
313 {
314 
315 	return dev_get_drvdata(&pdev->dev);
316 }
317 
318 static inline void
319 pci_set_drvdata(struct pci_dev *pdev, void *data)
320 {
321 
322 	dev_set_drvdata(&pdev->dev, data);
323 }
324 
325 static inline int
326 pci_enable_device(struct pci_dev *pdev)
327 {
328 
329 	pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
330 	pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
331 	return (0);
332 }
333 
334 static inline void
335 pci_disable_device(struct pci_dev *pdev)
336 {
337 
338 	pci_disable_busmaster(pdev->dev.bsddev);
339 }
340 
341 static inline int
342 pci_set_master(struct pci_dev *pdev)
343 {
344 
345 	pci_enable_busmaster(pdev->dev.bsddev);
346 	return (0);
347 }
348 
349 static inline int
350 pci_set_power_state(struct pci_dev *pdev, int state)
351 {
352 
353 	pci_set_powerstate(pdev->dev.bsddev, state);
354 	return (0);
355 }
356 
357 static inline int
358 pci_clear_master(struct pci_dev *pdev)
359 {
360 
361 	pci_disable_busmaster(pdev->dev.bsddev);
362 	return (0);
363 }
364 
365 static inline int
366 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
367 {
368 	int rid;
369 	int type;
370 
371 	type = pci_resource_type(pdev, bar);
372 	if (type < 0)
373 		return (-ENODEV);
374 	rid = PCIR_BAR(bar);
375 	if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid,
376 	    RF_ACTIVE) == NULL)
377 		return (-EINVAL);
378 	return (0);
379 }
380 
381 static inline void
382 pci_release_region(struct pci_dev *pdev, int bar)
383 {
384 	struct resource_list_entry *rle;
385 
386 	if ((rle = linux_pci_get_bar(pdev, bar)) == NULL)
387 		return;
388 	bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res);
389 }
390 
391 static inline void
392 pci_release_regions(struct pci_dev *pdev)
393 {
394 	int i;
395 
396 	for (i = 0; i <= PCIR_MAX_BAR_0; i++)
397 		pci_release_region(pdev, i);
398 }
399 
400 static inline int
401 pci_request_regions(struct pci_dev *pdev, const char *res_name)
402 {
403 	int error;
404 	int i;
405 
406 	for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
407 		error = pci_request_region(pdev, i, res_name);
408 		if (error && error != -ENODEV) {
409 			pci_release_regions(pdev);
410 			return (error);
411 		}
412 	}
413 	return (0);
414 }
415 
416 static inline void
417 pci_disable_msix(struct pci_dev *pdev)
418 {
419 
420 	pci_release_msi(pdev->dev.bsddev);
421 
422 	/*
423 	 * The MSIX IRQ numbers associated with this PCI device are no
424 	 * longer valid and might be re-assigned. Make sure
425 	 * linux_pci_find_irq_dev() does no longer see them by
426 	 * resetting their references to zero:
427 	 */
428 	pdev->dev.irq_start = 0;
429 	pdev->dev.irq_end = 0;
430 }
431 
432 #define	pci_disable_msi(pdev) \
433   linux_pci_disable_msi(pdev)
434 
435 static inline void
436 linux_pci_disable_msi(struct pci_dev *pdev)
437 {
438 
439 	pci_release_msi(pdev->dev.bsddev);
440 
441 	pdev->dev.irq_start = 0;
442 	pdev->dev.irq_end = 0;
443 	pdev->irq = pdev->dev.irq;
444 	pdev->msi_enabled = false;
445 }
446 
447 unsigned long	pci_resource_start(struct pci_dev *pdev, int bar);
448 unsigned long	pci_resource_len(struct pci_dev *pdev, int bar);
449 
450 static inline bus_addr_t
451 pci_bus_address(struct pci_dev *pdev, int bar)
452 {
453 
454 	return (pci_resource_start(pdev, bar));
455 }
456 
457 #define	PCI_CAP_ID_EXP	PCIY_EXPRESS
458 #define	PCI_CAP_ID_PCIX	PCIY_PCIX
459 #define PCI_CAP_ID_AGP  PCIY_AGP
460 #define PCI_CAP_ID_PM   PCIY_PMG
461 
462 #define PCI_EXP_DEVCTL		PCIER_DEVICE_CTL
463 #define PCI_EXP_DEVCTL_PAYLOAD	PCIEM_CTL_MAX_PAYLOAD
464 #define PCI_EXP_DEVCTL_READRQ	PCIEM_CTL_MAX_READ_REQUEST
465 #define PCI_EXP_LNKCTL		PCIER_LINK_CTL
466 #define PCI_EXP_LNKSTA		PCIER_LINK_STA
467 
468 static inline int
469 pci_find_capability(struct pci_dev *pdev, int capid)
470 {
471 	int reg;
472 
473 	if (pci_find_cap(pdev->dev.bsddev, capid, &reg))
474 		return (0);
475 	return (reg);
476 }
477 
478 static inline int pci_pcie_cap(struct pci_dev *dev)
479 {
480 	return pci_find_capability(dev, PCI_CAP_ID_EXP);
481 }
482 
483 
484 static inline int
485 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val)
486 {
487 
488 	*val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);
489 	return (0);
490 }
491 
492 static inline int
493 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val)
494 {
495 
496 	*val = (u16)pci_read_config(pdev->dev.bsddev, where, 2);
497 	return (0);
498 }
499 
500 static inline int
501 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val)
502 {
503 
504 	*val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
505 	return (0);
506 }
507 
508 static inline int
509 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val)
510 {
511 
512 	pci_write_config(pdev->dev.bsddev, where, val, 1);
513 	return (0);
514 }
515 
516 static inline int
517 pci_write_config_word(struct pci_dev *pdev, int where, u16 val)
518 {
519 
520 	pci_write_config(pdev->dev.bsddev, where, val, 2);
521 	return (0);
522 }
523 
524 static inline int
525 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val)
526 {
527 
528 	pci_write_config(pdev->dev.bsddev, where, val, 4);
529 	return (0);
530 }
531 
532 int	linux_pci_register_driver(struct pci_driver *pdrv);
533 int	linux_pci_register_drm_driver(struct pci_driver *pdrv);
534 void	linux_pci_unregister_driver(struct pci_driver *pdrv);
535 void	linux_pci_unregister_drm_driver(struct pci_driver *pdrv);
536 
537 #define	pci_register_driver(pdrv)	linux_pci_register_driver(pdrv)
538 #define	pci_unregister_driver(pdrv)	linux_pci_unregister_driver(pdrv)
539 
540 struct msix_entry {
541 	int entry;
542 	int vector;
543 };
544 
545 /*
546  * Enable msix, positive errors indicate actual number of available
547  * vectors.  Negative errors are failures.
548  *
549  * NB: define added to prevent this definition of pci_enable_msix from
550  * clashing with the native FreeBSD version.
551  */
552 #define	pci_enable_msix(...) \
553   linux_pci_enable_msix(__VA_ARGS__)
554 
555 static inline int
556 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq)
557 {
558 	struct resource_list_entry *rle;
559 	int error;
560 	int avail;
561 	int i;
562 
563 	avail = pci_msix_count(pdev->dev.bsddev);
564 	if (avail < nreq) {
565 		if (avail == 0)
566 			return -EINVAL;
567 		return avail;
568 	}
569 	avail = nreq;
570 	if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0)
571 		return error;
572 	/*
573 	 * Handle case where "pci_alloc_msix()" may allocate less
574 	 * interrupts than available and return with no error:
575 	 */
576 	if (avail < nreq) {
577 		pci_release_msi(pdev->dev.bsddev);
578 		return avail;
579 	}
580 	rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1);
581 	pdev->dev.irq_start = rle->start;
582 	pdev->dev.irq_end = rle->start + avail;
583 	for (i = 0; i < nreq; i++)
584 		entries[i].vector = pdev->dev.irq_start + i;
585 	return (0);
586 }
587 
588 #define	pci_enable_msix_range(...) \
589   linux_pci_enable_msix_range(__VA_ARGS__)
590 
591 static inline int
592 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
593     int minvec, int maxvec)
594 {
595 	int nvec = maxvec;
596 	int rc;
597 
598 	if (maxvec < minvec)
599 		return (-ERANGE);
600 
601 	do {
602 		rc = pci_enable_msix(dev, entries, nvec);
603 		if (rc < 0) {
604 			return (rc);
605 		} else if (rc > 0) {
606 			if (rc < minvec)
607 				return (-ENOSPC);
608 			nvec = rc;
609 		}
610 	} while (rc);
611 	return (nvec);
612 }
613 
614 #define	pci_enable_msi(pdev) \
615   linux_pci_enable_msi(pdev)
616 
617 static inline int
618 pci_enable_msi(struct pci_dev *pdev)
619 {
620 	struct resource_list_entry *rle;
621 	int error;
622 	int avail;
623 
624 	avail = pci_msi_count(pdev->dev.bsddev);
625 	if (avail < 1)
626 		return -EINVAL;
627 
628 	avail = 1;	/* this function only enable one MSI IRQ */
629 	if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0)
630 		return error;
631 
632 	rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1);
633 	pdev->dev.irq_start = rle->start;
634 	pdev->dev.irq_end = rle->start + avail;
635 	pdev->irq = rle->start;
636 	pdev->msi_enabled = true;
637 	return (0);
638 }
639 
640 static inline int
641 pci_channel_offline(struct pci_dev *pdev)
642 {
643 
644 	return (pci_get_vendor(pdev->dev.bsddev) == PCIV_INVALID);
645 }
646 
647 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
648 {
649 	return -ENODEV;
650 }
651 static inline void pci_disable_sriov(struct pci_dev *dev)
652 {
653 }
654 
655 #define DEFINE_PCI_DEVICE_TABLE(_table) \
656 	const struct pci_device_id _table[] __devinitdata
657 
658 
659 /* XXX This should not be necessary. */
660 #define	pcix_set_mmrbc(d, v)	0
661 #define	pcix_get_max_mmrbc(d)	0
662 #define	pcie_set_readrq(d, v)	pci_set_max_read_req(&(d)->dev, (v))
663 
664 #define	PCI_DMA_BIDIRECTIONAL	0
665 #define	PCI_DMA_TODEVICE	1
666 #define	PCI_DMA_FROMDEVICE	2
667 #define	PCI_DMA_NONE		3
668 
669 #define	pci_pool		dma_pool
670 #define	pci_pool_destroy(...)	dma_pool_destroy(__VA_ARGS__)
671 #define	pci_pool_alloc(...)	dma_pool_alloc(__VA_ARGS__)
672 #define	pci_pool_free(...)	dma_pool_free(__VA_ARGS__)
673 #define	pci_pool_create(_name, _pdev, _size, _align, _alloc)		\
674 	    dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc)
675 #define	pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle)		\
676 	    dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev,	\
677 		_size, _vaddr, _dma_handle)
678 #define	pci_map_sg(_hwdev, _sg, _nents, _dir)				\
679 	    dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev),	\
680 		_sg, _nents, (enum dma_data_direction)_dir)
681 #define	pci_map_single(_hwdev, _ptr, _size, _dir)			\
682 	    dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev),	\
683 		(_ptr), (_size), (enum dma_data_direction)_dir)
684 #define	pci_unmap_single(_hwdev, _addr, _size, _dir)			\
685 	    dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev,	\
686 		_addr, _size, (enum dma_data_direction)_dir)
687 #define	pci_unmap_sg(_hwdev, _sg, _nents, _dir)				\
688 	    dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev,	\
689 		_sg, _nents, (enum dma_data_direction)_dir)
690 #define	pci_map_page(_hwdev, _page, _offset, _size, _dir)		\
691 	    dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\
692 		_offset, _size, (enum dma_data_direction)_dir)
693 #define	pci_unmap_page(_hwdev, _dma_address, _size, _dir)		\
694 	    dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev,	\
695 		_dma_address, _size, (enum dma_data_direction)_dir)
696 #define	pci_set_dma_mask(_pdev, mask)	dma_set_mask(&(_pdev)->dev, (mask))
697 #define	pci_dma_mapping_error(_pdev, _dma_addr)				\
698 	    dma_mapping_error(&(_pdev)->dev, _dma_addr)
699 #define	pci_set_consistent_dma_mask(_pdev, _mask)			\
700 	    dma_set_coherent_mask(&(_pdev)->dev, (_mask))
701 #define	DECLARE_PCI_UNMAP_ADDR(x)	DEFINE_DMA_UNMAP_ADDR(x);
702 #define	DECLARE_PCI_UNMAP_LEN(x)	DEFINE_DMA_UNMAP_LEN(x);
703 #define	pci_unmap_addr		dma_unmap_addr
704 #define	pci_unmap_addr_set	dma_unmap_addr_set
705 #define	pci_unmap_len		dma_unmap_len
706 #define	pci_unmap_len_set	dma_unmap_len_set
707 
708 typedef unsigned int __bitwise pci_channel_state_t;
709 typedef unsigned int __bitwise pci_ers_result_t;
710 
711 enum pci_channel_state {
712 	pci_channel_io_normal = 1,
713 	pci_channel_io_frozen = 2,
714 	pci_channel_io_perm_failure = 3,
715 };
716 
717 enum pci_ers_result {
718 	PCI_ERS_RESULT_NONE = 1,
719 	PCI_ERS_RESULT_CAN_RECOVER = 2,
720 	PCI_ERS_RESULT_NEED_RESET = 3,
721 	PCI_ERS_RESULT_DISCONNECT = 4,
722 	PCI_ERS_RESULT_RECOVERED = 5,
723 };
724 
725 
726 /* PCI bus error event callbacks */
727 struct pci_error_handlers {
728 	pci_ers_result_t (*error_detected)(struct pci_dev *dev,
729 	    enum pci_channel_state error);
730 	pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
731 	pci_ers_result_t (*link_reset)(struct pci_dev *dev);
732 	pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
733 	void (*resume)(struct pci_dev *dev);
734 };
735 
736 /* FreeBSD does not support SRIOV - yet */
737 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
738 {
739 	return dev;
740 }
741 
742 static inline bool pci_is_pcie(struct pci_dev *dev)
743 {
744 	return !!pci_pcie_cap(dev);
745 }
746 
747 static inline u16 pcie_flags_reg(struct pci_dev *dev)
748 {
749 	int pos;
750 	u16 reg16;
751 
752 	pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
753 	if (!pos)
754 		return 0;
755 
756 	pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &reg16);
757 
758 	return reg16;
759 }
760 
761 
762 static inline int pci_pcie_type(struct pci_dev *dev)
763 {
764 	return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
765 }
766 
767 static inline int pcie_cap_version(struct pci_dev *dev)
768 {
769 	return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS;
770 }
771 
772 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev)
773 {
774 	int type = pci_pcie_type(dev);
775 
776 	return pcie_cap_version(dev) > 1 ||
777 	       type == PCI_EXP_TYPE_ROOT_PORT ||
778 	       type == PCI_EXP_TYPE_ENDPOINT ||
779 	       type == PCI_EXP_TYPE_LEG_END;
780 }
781 
782 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
783 {
784 		return true;
785 }
786 
787 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev)
788 {
789 	int type = pci_pcie_type(dev);
790 
791 	return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
792 	    (type == PCI_EXP_TYPE_DOWNSTREAM &&
793 	    pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT);
794 }
795 
796 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev)
797 {
798 	int type = pci_pcie_type(dev);
799 
800 	return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
801 	    type == PCI_EXP_TYPE_RC_EC;
802 }
803 
804 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
805 {
806 	if (!pci_is_pcie(dev))
807 		return false;
808 
809 	switch (pos) {
810 	case PCI_EXP_FLAGS_TYPE:
811 		return true;
812 	case PCI_EXP_DEVCAP:
813 	case PCI_EXP_DEVCTL:
814 	case PCI_EXP_DEVSTA:
815 		return pcie_cap_has_devctl(dev);
816 	case PCI_EXP_LNKCAP:
817 	case PCI_EXP_LNKCTL:
818 	case PCI_EXP_LNKSTA:
819 		return pcie_cap_has_lnkctl(dev);
820 	case PCI_EXP_SLTCAP:
821 	case PCI_EXP_SLTCTL:
822 	case PCI_EXP_SLTSTA:
823 		return pcie_cap_has_sltctl(dev);
824 	case PCI_EXP_RTCTL:
825 	case PCI_EXP_RTCAP:
826 	case PCI_EXP_RTSTA:
827 		return pcie_cap_has_rtctl(dev);
828 	case PCI_EXP_DEVCAP2:
829 	case PCI_EXP_DEVCTL2:
830 	case PCI_EXP_LNKCAP2:
831 	case PCI_EXP_LNKCTL2:
832 	case PCI_EXP_LNKSTA2:
833 		return pcie_cap_version(dev) > 1;
834 	default:
835 		return false;
836 	}
837 }
838 
839 static inline int
840 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
841 {
842 	if (pos & 3)
843 		return -EINVAL;
844 
845 	if (!pcie_capability_reg_implemented(dev, pos))
846 		return -EINVAL;
847 
848 	return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
849 }
850 
851 static inline int
852 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
853 {
854 	if (pos & 3)
855 		return -EINVAL;
856 
857 	if (!pcie_capability_reg_implemented(dev, pos))
858 		return -EINVAL;
859 
860 	return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
861 }
862 
863 static inline int
864 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
865 {
866 	if (pos & 1)
867 		return -EINVAL;
868 
869 	if (!pcie_capability_reg_implemented(dev, pos))
870 		return 0;
871 
872 	return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
873 }
874 
875 static inline int pcie_get_minimum_link(struct pci_dev *dev,
876     enum pci_bus_speed *speed, enum pcie_link_width *width)
877 {
878 	*speed = PCI_SPEED_UNKNOWN;
879 	*width = PCIE_LNK_WIDTH_UNKNOWN;
880 	return (0);
881 }
882 
883 static inline int
884 pci_num_vf(struct pci_dev *dev)
885 {
886 	return (0);
887 }
888 
889 static inline enum pci_bus_speed
890 pcie_get_speed_cap(struct pci_dev *dev)
891 {
892 	device_t root;
893 	uint32_t lnkcap, lnkcap2;
894 	int error, pos;
895 
896 	root = device_get_parent(dev->dev.bsddev);
897 	if (root == NULL)
898 		return (PCI_SPEED_UNKNOWN);
899 	root = device_get_parent(root);
900 	if (root == NULL)
901 		return (PCI_SPEED_UNKNOWN);
902 	root = device_get_parent(root);
903 	if (root == NULL)
904 		return (PCI_SPEED_UNKNOWN);
905 
906 	if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA ||
907 	    pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS)
908 		return (PCI_SPEED_UNKNOWN);
909 
910 	if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0)
911 		return (PCI_SPEED_UNKNOWN);
912 
913 	lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4);
914 
915 	if (lnkcap2) {	/* PCIe r3.0-compliant */
916 		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
917 			return (PCIE_SPEED_2_5GT);
918 		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
919 			return (PCIE_SPEED_5_0GT);
920 		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
921 			return (PCIE_SPEED_8_0GT);
922 		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
923 			return (PCIE_SPEED_16_0GT);
924 	} else {	/* pre-r3.0 */
925 		lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4);
926 		if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
927 			return (PCIE_SPEED_2_5GT);
928 		if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
929 			return (PCIE_SPEED_5_0GT);
930 		if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
931 			return (PCIE_SPEED_8_0GT);
932 		if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
933 			return (PCIE_SPEED_16_0GT);
934 	}
935 	return (PCI_SPEED_UNKNOWN);
936 }
937 
938 static inline enum pcie_link_width
939 pcie_get_width_cap(struct pci_dev *dev)
940 {
941 	uint32_t lnkcap;
942 
943 	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
944 	if (lnkcap)
945 		return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4);
946 
947 	return (PCIE_LNK_WIDTH_UNKNOWN);
948 }
949 
950 #endif	/* _LINUX_PCI_H_ */
951