1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/nv.h> 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 #include <linux/pm.h> 63 64 struct pci_device_id { 65 uint32_t vendor; 66 uint32_t device; 67 uint32_t subvendor; 68 uint32_t subdevice; 69 uint32_t class; 70 uint32_t class_mask; 71 uintptr_t driver_data; 72 }; 73 74 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 75 #define MODULE_DEVICE_TABLE(_bus, _table) \ 76 \ 77 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 78 DEVMETHOD_END \ 79 }; \ 80 \ 81 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 82 "lkpi_" #_bus #_table, \ 83 _ ## _bus ## _ ## _table ## _methods, \ 84 0 \ 85 }; \ 86 \ 87 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 88 0, 0); \ 89 \ 90 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 91 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 92 93 #define PCI_ANY_ID -1U 94 95 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 96 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 97 #define PCI_FUNC(devfn) ((devfn) & 0x07) 98 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 99 100 #define PCI_VDEVICE(_vendor, _device) \ 101 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 102 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 103 #define PCI_DEVICE(_vendor, _device) \ 104 .vendor = (_vendor), .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 107 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 108 109 #define PCI_VENDOR_ID PCIR_VENDOR 110 #define PCI_DEVICE_ID PCIR_DEVICE 111 #define PCI_COMMAND PCIR_COMMAND 112 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 115 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 116 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 117 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 118 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 119 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 120 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 121 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 122 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 123 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 124 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 125 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 126 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 127 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 128 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 129 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 130 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 131 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 132 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 133 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 134 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 135 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 136 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 137 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 138 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 139 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 140 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 141 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 142 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 143 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 144 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 145 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 146 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 147 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 148 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 149 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 150 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 151 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 152 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 153 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 154 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 155 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 156 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 157 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 158 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 159 #define PCI_EXP_LNKCTL2_TLS 0x000f 160 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 161 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 162 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 163 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 164 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 165 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 166 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 167 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 168 169 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 170 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 171 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 172 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 173 174 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 175 #define PCI_EXP_DEVSTA_TRPND 0x0020 176 177 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 178 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 179 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 180 181 enum pci_bus_speed { 182 PCI_SPEED_UNKNOWN = -1, 183 PCIE_SPEED_2_5GT, 184 PCIE_SPEED_5_0GT, 185 PCIE_SPEED_8_0GT, 186 PCIE_SPEED_16_0GT, 187 PCIE_SPEED_32_0GT, 188 PCIE_SPEED_64_0GT, 189 }; 190 191 enum pcie_link_width { 192 PCIE_LNK_WIDTH_RESRV = 0x00, 193 PCIE_LNK_X1 = 0x01, 194 PCIE_LNK_X2 = 0x02, 195 PCIE_LNK_X4 = 0x04, 196 PCIE_LNK_X8 = 0x08, 197 PCIE_LNK_X12 = 0x0c, 198 PCIE_LNK_X16 = 0x10, 199 PCIE_LNK_X32 = 0x20, 200 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 201 }; 202 203 #define PCIE_LINK_STATE_L0S 0x00000001 204 #define PCIE_LINK_STATE_L1 0x00000002 205 #define PCIE_LINK_STATE_CLKPM 0x00000004 206 207 typedef int pci_power_t; 208 209 #define PCI_D0 PCI_POWERSTATE_D0 210 #define PCI_D1 PCI_POWERSTATE_D1 211 #define PCI_D2 PCI_POWERSTATE_D2 212 #define PCI_D3hot PCI_POWERSTATE_D3 213 #define PCI_D3cold 4 214 215 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 216 217 extern const char *pci_power_names[6]; 218 219 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 220 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 221 222 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 223 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 224 225 #define PCI_L1SS_CTL1 0x8 226 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 227 228 #define PCI_IRQ_LEGACY 0x01 229 #define PCI_IRQ_MSI 0x02 230 #define PCI_IRQ_MSIX 0x04 231 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 232 233 struct pci_dev; 234 235 struct pci_driver { 236 struct list_head node; 237 char *name; 238 const struct pci_device_id *id_table; 239 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 240 void (*remove)(struct pci_dev *dev); 241 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 242 int (*resume) (struct pci_dev *dev); /* Device woken up */ 243 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 244 driver_t bsddriver; 245 devclass_t bsdclass; 246 struct device_driver driver; 247 const struct pci_error_handlers *err_handler; 248 bool isdrm; 249 int bsd_probe_return; 250 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 251 const nvlist_t *pf_config); 252 void (*bsd_iov_uninit)(device_t dev); 253 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 254 const nvlist_t *vf_config); 255 }; 256 257 struct pci_bus { 258 struct pci_dev *self; 259 int domain; 260 int number; 261 }; 262 263 extern struct list_head pci_drivers; 264 extern struct list_head pci_devices; 265 extern spinlock_t pci_lock; 266 267 #define __devexit_p(x) x 268 269 #define module_pci_driver(_driver) \ 270 \ 271 static inline int \ 272 _pci_init(void) \ 273 { \ 274 \ 275 return (linux_pci_register_driver(&_driver)); \ 276 } \ 277 \ 278 static inline void \ 279 _pci_exit(void) \ 280 { \ 281 \ 282 linux_pci_unregister_driver(&_driver); \ 283 } \ 284 \ 285 module_init(_pci_init); \ 286 module_exit(_pci_exit) 287 288 struct msi_msg { 289 uint32_t data; 290 }; 291 292 struct msi_desc { 293 struct msi_msg msg; 294 struct { 295 bool is_64; 296 } msi_attrib; 297 }; 298 299 /* 300 * If we find drivers accessing this from multiple KPIs we may have to 301 * refcount objects of this structure. 302 */ 303 struct pci_mmio_region { 304 TAILQ_ENTRY(pci_mmio_region) next; 305 struct resource *res; 306 int rid; 307 int type; 308 }; 309 310 struct pci_dev { 311 struct device dev; 312 struct list_head links; 313 struct pci_driver *pdrv; 314 struct pci_bus *bus; 315 struct pci_dev *root; 316 pci_power_t current_state; 317 uint16_t device; 318 uint16_t vendor; 319 uint16_t subsystem_vendor; 320 uint16_t subsystem_device; 321 unsigned int irq; 322 unsigned int devfn; 323 uint32_t class; 324 uint8_t revision; 325 uint8_t msi_cap; 326 bool managed; /* devres "pcim_*(). */ 327 bool want_iomap_res; 328 bool msi_enabled; 329 bool msix_enabled; 330 phys_addr_t rom; 331 size_t romlen; 332 /* 333 * msi_desc should be an array one day? For as long as we only support 334 * 1 MSI vector this is fine. 335 */ 336 struct msi_desc *msi_desc; 337 338 TAILQ_HEAD(, pci_mmio_region) mmio; 339 }; 340 341 /* We need some meta-struct to keep track of these for devres. */ 342 struct pci_devres { 343 bool enable_io; 344 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 345 uint8_t region_mask; 346 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 347 }; 348 struct pcim_iomap_devres { 349 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 350 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 351 }; 352 353 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 354 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 355 unsigned int flags); 356 357 /* Internal helper function(s). */ 358 struct pci_dev *lkpinew_pci_dev(device_t); 359 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev); 360 void lkpi_pci_devres_release(struct device *, void *); 361 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size); 362 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev); 363 void lkpi_pcim_iomap_table_release(struct device *, void *); 364 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 365 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 366 367 static inline bool 368 dev_is_pci(struct device *dev) 369 { 370 371 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 372 } 373 374 static inline int 375 pci_resource_type(struct pci_dev *pdev, int bar) 376 { 377 struct pci_map *pm; 378 379 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 380 if (!pm) 381 return (-1); 382 383 if (PCI_BAR_IO(pm->pm_value)) 384 return (SYS_RES_IOPORT); 385 else 386 return (SYS_RES_MEMORY); 387 } 388 389 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 390 struct resource_list *rl, int type, int rid); 391 392 static inline struct resource_list_entry * 393 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 394 { 395 struct pci_devinfo *dinfo; 396 struct resource_list *rl; 397 struct resource_list_entry *rle; 398 399 dinfo = device_get_ivars(pdev->dev.bsddev); 400 rl = &dinfo->resources; 401 rle = resource_list_find(rl, type, rid); 402 /* Reserve resources for this BAR if needed. */ 403 if (rle == NULL && reserve_bar) 404 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 405 return (rle); 406 } 407 408 static inline struct resource_list_entry * 409 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 410 { 411 int type; 412 413 type = pci_resource_type(pdev, bar); 414 if (type < 0) 415 return (NULL); 416 bar = PCIR_BAR(bar); 417 return (linux_pci_get_rle(pdev, type, bar, reserve)); 418 } 419 420 static inline struct device * 421 linux_pci_find_irq_dev(unsigned int irq) 422 { 423 struct pci_dev *pdev; 424 struct device *found; 425 426 found = NULL; 427 spin_lock(&pci_lock); 428 list_for_each_entry(pdev, &pci_devices, links) { 429 if (irq == pdev->dev.irq || 430 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 431 found = &pdev->dev; 432 break; 433 } 434 } 435 spin_unlock(&pci_lock); 436 return (found); 437 } 438 439 /* 440 * All drivers just seem to want to inspect the type not flags. 441 */ 442 static inline int 443 pci_resource_flags(struct pci_dev *pdev, int bar) 444 { 445 int type; 446 447 type = pci_resource_type(pdev, bar); 448 if (type < 0) 449 return (0); 450 return (1 << type); 451 } 452 453 static inline const char * 454 pci_name(struct pci_dev *d) 455 { 456 457 return device_get_desc(d->dev.bsddev); 458 } 459 460 static inline void * 461 pci_get_drvdata(struct pci_dev *pdev) 462 { 463 464 return dev_get_drvdata(&pdev->dev); 465 } 466 467 static inline void 468 pci_set_drvdata(struct pci_dev *pdev, void *data) 469 { 470 471 dev_set_drvdata(&pdev->dev, data); 472 } 473 474 static inline struct pci_dev * 475 pci_dev_get(struct pci_dev *pdev) 476 { 477 478 if (pdev != NULL) 479 get_device(&pdev->dev); 480 return (pdev); 481 } 482 483 static __inline void 484 pci_dev_put(struct pci_dev *pdev) 485 { 486 487 if (pdev != NULL) 488 put_device(&pdev->dev); 489 } 490 491 static inline int 492 pci_enable_device(struct pci_dev *pdev) 493 { 494 495 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 496 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 497 return (0); 498 } 499 500 static inline void 501 pci_disable_device(struct pci_dev *pdev) 502 { 503 504 pci_disable_busmaster(pdev->dev.bsddev); 505 } 506 507 static inline int 508 pci_set_master(struct pci_dev *pdev) 509 { 510 511 pci_enable_busmaster(pdev->dev.bsddev); 512 return (0); 513 } 514 515 static inline int 516 pci_set_power_state(struct pci_dev *pdev, int state) 517 { 518 519 pci_set_powerstate(pdev->dev.bsddev, state); 520 return (0); 521 } 522 523 static inline int 524 pci_clear_master(struct pci_dev *pdev) 525 { 526 527 pci_disable_busmaster(pdev->dev.bsddev); 528 return (0); 529 } 530 531 static inline bool 532 pci_is_root_bus(struct pci_bus *pbus) 533 { 534 535 return (pbus->self == NULL); 536 } 537 538 static inline struct pci_dev * 539 pci_upstream_bridge(struct pci_dev *pdev) 540 { 541 542 if (pci_is_root_bus(pdev->bus)) 543 return (NULL); 544 545 /* 546 * If we do not have a (proper) "upstream bridge" set, e.g., we point 547 * to ourselves, try to handle this case on the fly like we do 548 * for pcie_find_root_port(). 549 */ 550 if (pdev == pdev->bus->self) { 551 device_t bridge; 552 553 bridge = device_get_parent(pdev->dev.bsddev); 554 if (bridge == NULL) 555 goto done; 556 bridge = device_get_parent(bridge); 557 if (bridge == NULL) 558 goto done; 559 if (device_get_devclass(device_get_parent(bridge)) != 560 devclass_find("pci")) 561 goto done; 562 563 /* 564 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 565 * for it so it can be returned. 566 */ 567 pdev->bus->self = lkpinew_pci_dev(bridge); 568 } 569 done: 570 return (pdev->bus->self); 571 } 572 573 static inline struct pci_devres * 574 lkpi_pci_devres_find(struct pci_dev *pdev) 575 { 576 577 if (!pdev->managed) 578 return (NULL); 579 580 return (lkpi_pci_devres_get_alloc(pdev)); 581 } 582 583 static inline void 584 pci_release_region(struct pci_dev *pdev, int bar) 585 { 586 struct resource_list_entry *rle; 587 struct pci_devres *dr; 588 struct pci_mmio_region *mmio, *p; 589 590 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 591 return; 592 593 /* 594 * As we implicitly track the requests we also need to clear them on 595 * release. Do clear before resource release. 596 */ 597 dr = lkpi_pci_devres_find(pdev); 598 if (dr != NULL) { 599 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 600 " region_table res %p != rel->res %p\n", __func__, pdev, 601 bar, dr->region_table[bar], rle->res)); 602 dr->region_table[bar] = NULL; 603 dr->region_mask &= ~(1 << bar); 604 } 605 606 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 607 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 608 continue; 609 TAILQ_REMOVE(&pdev->mmio, mmio, next); 610 free(mmio, M_DEVBUF); 611 } 612 613 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 614 } 615 616 static inline void 617 pci_release_regions(struct pci_dev *pdev) 618 { 619 int i; 620 621 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 622 pci_release_region(pdev, i); 623 } 624 625 static inline int 626 pci_request_regions(struct pci_dev *pdev, const char *res_name) 627 { 628 int error; 629 int i; 630 631 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 632 error = pci_request_region(pdev, i, res_name); 633 if (error && error != -ENODEV) { 634 pci_release_regions(pdev); 635 return (error); 636 } 637 } 638 return (0); 639 } 640 641 static inline void 642 lkpi_pci_disable_msix(struct pci_dev *pdev) 643 { 644 645 pci_release_msi(pdev->dev.bsddev); 646 647 /* 648 * The MSIX IRQ numbers associated with this PCI device are no 649 * longer valid and might be re-assigned. Make sure 650 * linux_pci_find_irq_dev() does no longer see them by 651 * resetting their references to zero: 652 */ 653 pdev->dev.irq_start = 0; 654 pdev->dev.irq_end = 0; 655 pdev->msix_enabled = false; 656 } 657 /* Only for consistency. No conflict on that one. */ 658 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 659 660 static inline void 661 lkpi_pci_disable_msi(struct pci_dev *pdev) 662 { 663 664 pci_release_msi(pdev->dev.bsddev); 665 666 pdev->dev.irq_start = 0; 667 pdev->dev.irq_end = 0; 668 pdev->irq = pdev->dev.irq; 669 pdev->msi_enabled = false; 670 } 671 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 672 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 673 674 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 675 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 676 677 static inline bus_addr_t 678 pci_bus_address(struct pci_dev *pdev, int bar) 679 { 680 681 return (pci_resource_start(pdev, bar)); 682 } 683 684 #define PCI_CAP_ID_EXP PCIY_EXPRESS 685 #define PCI_CAP_ID_PCIX PCIY_PCIX 686 #define PCI_CAP_ID_AGP PCIY_AGP 687 #define PCI_CAP_ID_PM PCIY_PMG 688 689 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 690 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 691 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 692 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 693 #define PCI_EXP_LNKSTA PCIER_LINK_STA 694 695 static inline int 696 pci_find_capability(struct pci_dev *pdev, int capid) 697 { 698 int reg; 699 700 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 701 return (0); 702 return (reg); 703 } 704 705 static inline int pci_pcie_cap(struct pci_dev *dev) 706 { 707 return pci_find_capability(dev, PCI_CAP_ID_EXP); 708 } 709 710 static inline int 711 pci_find_ext_capability(struct pci_dev *pdev, int capid) 712 { 713 int reg; 714 715 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 716 return (0); 717 return (reg); 718 } 719 720 #define PCIM_PCAP_PME_SHIFT 11 721 static __inline bool 722 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 723 { 724 struct pci_devinfo *dinfo; 725 pcicfgregs *cfg; 726 727 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 728 return (false); 729 730 dinfo = device_get_ivars(pdev->dev.bsddev); 731 cfg = &dinfo->cfg; 732 733 if (cfg->pp.pp_cap == 0) 734 return (false); 735 736 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 737 return (true); 738 739 return (false); 740 } 741 742 static inline int 743 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 744 { 745 746 if (!pci_enable_aspm) 747 return (-EPERM); 748 749 return (-ENXIO); 750 } 751 752 static inline int 753 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 754 { 755 756 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 757 return (0); 758 } 759 760 static inline int 761 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 762 { 763 764 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 765 return (0); 766 } 767 768 static inline int 769 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 770 { 771 772 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 773 return (0); 774 } 775 776 static inline int 777 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 778 { 779 780 pci_write_config(pdev->dev.bsddev, where, val, 1); 781 return (0); 782 } 783 784 static inline int 785 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 786 { 787 788 pci_write_config(pdev->dev.bsddev, where, val, 2); 789 return (0); 790 } 791 792 static inline int 793 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 794 { 795 796 pci_write_config(pdev->dev.bsddev, where, val, 4); 797 return (0); 798 } 799 800 int linux_pci_register_driver(struct pci_driver *pdrv); 801 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 802 void linux_pci_unregister_driver(struct pci_driver *pdrv); 803 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 804 805 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 806 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 807 808 struct msix_entry { 809 int entry; 810 int vector; 811 }; 812 813 /* 814 * Enable msix, positive errors indicate actual number of available 815 * vectors. Negative errors are failures. 816 * 817 * NB: define added to prevent this definition of pci_enable_msix from 818 * clashing with the native FreeBSD version. 819 */ 820 #define pci_enable_msix(...) \ 821 linux_pci_enable_msix(__VA_ARGS__) 822 823 static inline int 824 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 825 { 826 struct resource_list_entry *rle; 827 int error; 828 int avail; 829 int i; 830 831 avail = pci_msix_count(pdev->dev.bsddev); 832 if (avail < nreq) { 833 if (avail == 0) 834 return -EINVAL; 835 return avail; 836 } 837 avail = nreq; 838 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 839 return error; 840 /* 841 * Handle case where "pci_alloc_msix()" may allocate less 842 * interrupts than available and return with no error: 843 */ 844 if (avail < nreq) { 845 pci_release_msi(pdev->dev.bsddev); 846 return avail; 847 } 848 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 849 pdev->dev.irq_start = rle->start; 850 pdev->dev.irq_end = rle->start + avail; 851 for (i = 0; i < nreq; i++) 852 entries[i].vector = pdev->dev.irq_start + i; 853 pdev->msix_enabled = true; 854 return (0); 855 } 856 857 #define pci_enable_msix_range(...) \ 858 linux_pci_enable_msix_range(__VA_ARGS__) 859 860 static inline int 861 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 862 int minvec, int maxvec) 863 { 864 int nvec = maxvec; 865 int rc; 866 867 if (maxvec < minvec) 868 return (-ERANGE); 869 870 do { 871 rc = pci_enable_msix(dev, entries, nvec); 872 if (rc < 0) { 873 return (rc); 874 } else if (rc > 0) { 875 if (rc < minvec) 876 return (-ENOSPC); 877 nvec = rc; 878 } 879 } while (rc); 880 return (nvec); 881 } 882 883 #define pci_enable_msi(pdev) \ 884 linux_pci_enable_msi(pdev) 885 886 static inline int 887 pci_enable_msi(struct pci_dev *pdev) 888 { 889 struct resource_list_entry *rle; 890 int error; 891 int avail; 892 893 avail = pci_msi_count(pdev->dev.bsddev); 894 if (avail < 1) 895 return -EINVAL; 896 897 avail = 1; /* this function only enable one MSI IRQ */ 898 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 899 return error; 900 901 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 902 pdev->dev.irq_start = rle->start; 903 pdev->dev.irq_end = rle->start + avail; 904 pdev->irq = rle->start; 905 pdev->msi_enabled = true; 906 return (0); 907 } 908 909 static inline int 910 pci_channel_offline(struct pci_dev *pdev) 911 { 912 913 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 914 } 915 916 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 917 { 918 return -ENODEV; 919 } 920 921 static inline void pci_disable_sriov(struct pci_dev *dev) 922 { 923 } 924 925 static inline void * 926 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 927 { 928 struct resource *res; 929 930 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 931 if (res == NULL) 932 return (NULL); 933 /* This is a FreeBSD extension so we can use bus_*(). */ 934 if (pdev->want_iomap_res) 935 return (res); 936 return ((void *)rman_get_bushandle(res)); 937 } 938 939 static inline void 940 pci_iounmap(struct pci_dev *pdev, void *res) 941 { 942 struct pci_mmio_region *mmio, *p; 943 944 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 945 if (res != (void *)rman_get_bushandle(mmio->res)) 946 continue; 947 bus_release_resource(pdev->dev.bsddev, 948 mmio->type, mmio->rid, mmio->res); 949 TAILQ_REMOVE(&pdev->mmio, mmio, next); 950 free(mmio, M_DEVBUF); 951 return; 952 } 953 } 954 955 static inline void 956 lkpi_pci_save_state(struct pci_dev *pdev) 957 { 958 959 pci_save_state(pdev->dev.bsddev); 960 } 961 962 static inline void 963 lkpi_pci_restore_state(struct pci_dev *pdev) 964 { 965 966 pci_restore_state(pdev->dev.bsddev); 967 } 968 969 #define pci_save_state(dev) lkpi_pci_save_state(dev) 970 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 971 972 static inline int 973 pci_reset_function(struct pci_dev *pdev) 974 { 975 976 return (-ENOSYS); 977 } 978 979 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 980 const struct pci_device_id _table[] __devinitdata 981 982 /* XXX This should not be necessary. */ 983 #define pcix_set_mmrbc(d, v) 0 984 #define pcix_get_max_mmrbc(d) 0 985 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 986 987 #define PCI_DMA_BIDIRECTIONAL 0 988 #define PCI_DMA_TODEVICE 1 989 #define PCI_DMA_FROMDEVICE 2 990 #define PCI_DMA_NONE 3 991 992 #define pci_pool dma_pool 993 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 994 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 995 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 996 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 997 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 998 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 999 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1000 _size, _vaddr, _dma_handle) 1001 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 1002 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1003 _sg, _nents, (enum dma_data_direction)_dir) 1004 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 1005 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1006 (_ptr), (_size), (enum dma_data_direction)_dir) 1007 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 1008 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1009 _addr, _size, (enum dma_data_direction)_dir) 1010 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 1011 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1012 _sg, _nents, (enum dma_data_direction)_dir) 1013 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 1014 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 1015 _offset, _size, (enum dma_data_direction)_dir) 1016 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 1017 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1018 _dma_address, _size, (enum dma_data_direction)_dir) 1019 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1020 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1021 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1022 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1023 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1024 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1025 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1026 #define pci_unmap_addr dma_unmap_addr 1027 #define pci_unmap_addr_set dma_unmap_addr_set 1028 #define pci_unmap_len dma_unmap_len 1029 #define pci_unmap_len_set dma_unmap_len_set 1030 1031 typedef unsigned int __bitwise pci_channel_state_t; 1032 typedef unsigned int __bitwise pci_ers_result_t; 1033 1034 enum pci_channel_state { 1035 pci_channel_io_normal = 1, 1036 pci_channel_io_frozen = 2, 1037 pci_channel_io_perm_failure = 3, 1038 }; 1039 1040 enum pci_ers_result { 1041 PCI_ERS_RESULT_NONE = 1, 1042 PCI_ERS_RESULT_CAN_RECOVER = 2, 1043 PCI_ERS_RESULT_NEED_RESET = 3, 1044 PCI_ERS_RESULT_DISCONNECT = 4, 1045 PCI_ERS_RESULT_RECOVERED = 5, 1046 }; 1047 1048 /* PCI bus error event callbacks */ 1049 struct pci_error_handlers { 1050 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1051 enum pci_channel_state error); 1052 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1053 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1054 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1055 void (*resume)(struct pci_dev *dev); 1056 }; 1057 1058 /* FreeBSD does not support SRIOV - yet */ 1059 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1060 { 1061 return dev; 1062 } 1063 1064 static inline bool pci_is_pcie(struct pci_dev *dev) 1065 { 1066 return !!pci_pcie_cap(dev); 1067 } 1068 1069 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1070 { 1071 int pos; 1072 u16 reg16; 1073 1074 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1075 if (!pos) 1076 return 0; 1077 1078 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1079 1080 return reg16; 1081 } 1082 1083 static inline int pci_pcie_type(struct pci_dev *dev) 1084 { 1085 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1086 } 1087 1088 static inline int pcie_cap_version(struct pci_dev *dev) 1089 { 1090 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1091 } 1092 1093 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1094 { 1095 int type = pci_pcie_type(dev); 1096 1097 return pcie_cap_version(dev) > 1 || 1098 type == PCI_EXP_TYPE_ROOT_PORT || 1099 type == PCI_EXP_TYPE_ENDPOINT || 1100 type == PCI_EXP_TYPE_LEG_END; 1101 } 1102 1103 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1104 { 1105 return true; 1106 } 1107 1108 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1109 { 1110 int type = pci_pcie_type(dev); 1111 1112 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1113 (type == PCI_EXP_TYPE_DOWNSTREAM && 1114 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1115 } 1116 1117 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1118 { 1119 int type = pci_pcie_type(dev); 1120 1121 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1122 type == PCI_EXP_TYPE_RC_EC; 1123 } 1124 1125 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1126 { 1127 if (!pci_is_pcie(dev)) 1128 return false; 1129 1130 switch (pos) { 1131 case PCI_EXP_FLAGS_TYPE: 1132 return true; 1133 case PCI_EXP_DEVCAP: 1134 case PCI_EXP_DEVCTL: 1135 case PCI_EXP_DEVSTA: 1136 return pcie_cap_has_devctl(dev); 1137 case PCI_EXP_LNKCAP: 1138 case PCI_EXP_LNKCTL: 1139 case PCI_EXP_LNKSTA: 1140 return pcie_cap_has_lnkctl(dev); 1141 case PCI_EXP_SLTCAP: 1142 case PCI_EXP_SLTCTL: 1143 case PCI_EXP_SLTSTA: 1144 return pcie_cap_has_sltctl(dev); 1145 case PCI_EXP_RTCTL: 1146 case PCI_EXP_RTCAP: 1147 case PCI_EXP_RTSTA: 1148 return pcie_cap_has_rtctl(dev); 1149 case PCI_EXP_DEVCAP2: 1150 case PCI_EXP_DEVCTL2: 1151 case PCI_EXP_LNKCAP2: 1152 case PCI_EXP_LNKCTL2: 1153 case PCI_EXP_LNKSTA2: 1154 return pcie_cap_version(dev) > 1; 1155 default: 1156 return false; 1157 } 1158 } 1159 1160 static inline int 1161 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1162 { 1163 if (pos & 3) 1164 return -EINVAL; 1165 1166 if (!pcie_capability_reg_implemented(dev, pos)) 1167 return -EINVAL; 1168 1169 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1170 } 1171 1172 static inline int 1173 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1174 { 1175 if (pos & 3) 1176 return -EINVAL; 1177 1178 if (!pcie_capability_reg_implemented(dev, pos)) 1179 return -EINVAL; 1180 1181 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1182 } 1183 1184 static inline int 1185 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1186 { 1187 if (pos & 1) 1188 return -EINVAL; 1189 1190 if (!pcie_capability_reg_implemented(dev, pos)) 1191 return 0; 1192 1193 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1194 } 1195 1196 static inline int 1197 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1198 { 1199 int error; 1200 uint16_t v; 1201 1202 error = pcie_capability_read_word(dev, pos, &v); 1203 if (error != 0) 1204 return (error); 1205 1206 v |= val; 1207 1208 error = pcie_capability_write_word(dev, pos, v); 1209 return (error); 1210 } 1211 1212 static inline int 1213 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1214 { 1215 int error; 1216 uint16_t v; 1217 1218 error = pcie_capability_read_word(dev, pos, &v); 1219 if (error != 0) 1220 return (error); 1221 1222 v &= ~val; 1223 1224 error = pcie_capability_write_word(dev, pos, v); 1225 return (error); 1226 } 1227 1228 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1229 enum pci_bus_speed *speed, enum pcie_link_width *width) 1230 { 1231 *speed = PCI_SPEED_UNKNOWN; 1232 *width = PCIE_LNK_WIDTH_UNKNOWN; 1233 return (0); 1234 } 1235 1236 static inline int 1237 pci_num_vf(struct pci_dev *dev) 1238 { 1239 return (0); 1240 } 1241 1242 static inline enum pci_bus_speed 1243 pcie_get_speed_cap(struct pci_dev *dev) 1244 { 1245 device_t root; 1246 uint32_t lnkcap, lnkcap2; 1247 int error, pos; 1248 1249 root = device_get_parent(dev->dev.bsddev); 1250 if (root == NULL) 1251 return (PCI_SPEED_UNKNOWN); 1252 root = device_get_parent(root); 1253 if (root == NULL) 1254 return (PCI_SPEED_UNKNOWN); 1255 root = device_get_parent(root); 1256 if (root == NULL) 1257 return (PCI_SPEED_UNKNOWN); 1258 1259 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1260 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1261 return (PCI_SPEED_UNKNOWN); 1262 1263 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1264 return (PCI_SPEED_UNKNOWN); 1265 1266 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1267 1268 if (lnkcap2) { /* PCIe r3.0-compliant */ 1269 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1270 return (PCIE_SPEED_2_5GT); 1271 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1272 return (PCIE_SPEED_5_0GT); 1273 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1274 return (PCIE_SPEED_8_0GT); 1275 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1276 return (PCIE_SPEED_16_0GT); 1277 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1278 return (PCIE_SPEED_32_0GT); 1279 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1280 return (PCIE_SPEED_64_0GT); 1281 } else { /* pre-r3.0 */ 1282 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1283 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1284 return (PCIE_SPEED_2_5GT); 1285 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1286 return (PCIE_SPEED_5_0GT); 1287 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1288 return (PCIE_SPEED_8_0GT); 1289 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1290 return (PCIE_SPEED_16_0GT); 1291 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1292 return (PCIE_SPEED_32_0GT); 1293 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1294 return (PCIE_SPEED_64_0GT); 1295 } 1296 return (PCI_SPEED_UNKNOWN); 1297 } 1298 1299 static inline enum pcie_link_width 1300 pcie_get_width_cap(struct pci_dev *dev) 1301 { 1302 uint32_t lnkcap; 1303 1304 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1305 if (lnkcap) 1306 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1307 1308 return (PCIE_LNK_WIDTH_UNKNOWN); 1309 } 1310 1311 static inline int 1312 pcie_get_mps(struct pci_dev *dev) 1313 { 1314 return (pci_get_max_payload(dev->dev.bsddev)); 1315 } 1316 1317 static inline uint32_t 1318 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1319 { 1320 1321 switch(spd) { 1322 case PCIE_SPEED_64_0GT: 1323 return (64000 * 128 / 130); 1324 case PCIE_SPEED_32_0GT: 1325 return (32000 * 128 / 130); 1326 case PCIE_SPEED_16_0GT: 1327 return (16000 * 128 / 130); 1328 case PCIE_SPEED_8_0GT: 1329 return (8000 * 128 / 130); 1330 case PCIE_SPEED_5_0GT: 1331 return (5000 * 8 / 10); 1332 case PCIE_SPEED_2_5GT: 1333 return (2500 * 8 / 10); 1334 default: 1335 return (0); 1336 } 1337 } 1338 1339 static inline uint32_t 1340 pcie_bandwidth_available(struct pci_dev *pdev, 1341 struct pci_dev **limiting, 1342 enum pci_bus_speed *speed, 1343 enum pcie_link_width *width) 1344 { 1345 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1346 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1347 1348 if (speed) 1349 *speed = nspeed; 1350 if (width) 1351 *width = nwidth; 1352 1353 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1354 } 1355 1356 static inline struct pci_dev * 1357 pcie_find_root_port(struct pci_dev *pdev) 1358 { 1359 device_t root; 1360 1361 if (pdev->root != NULL) 1362 return (pdev->root); 1363 1364 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1365 if (root == NULL) 1366 return (NULL); 1367 1368 pdev->root = lkpinew_pci_dev(root); 1369 return (pdev->root); 1370 } 1371 1372 /* This is needed when people rip out the device "HotPlug". */ 1373 static inline void 1374 pci_lock_rescan_remove(void) 1375 { 1376 } 1377 1378 static inline void 1379 pci_unlock_rescan_remove(void) 1380 { 1381 } 1382 1383 static __inline void 1384 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1385 { 1386 } 1387 1388 /* 1389 * The following functions can be used to attach/detach the LinuxKPI's 1390 * PCI device runtime. The pci_driver and pci_device_id pointer is 1391 * allowed to be NULL. Other pointers must be all valid. 1392 * The pci_dev structure should be zero-initialized before passed 1393 * to the linux_pci_attach_device function. 1394 */ 1395 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1396 const struct pci_device_id *, struct pci_dev *); 1397 extern int linux_pci_detach_device(struct pci_dev *); 1398 1399 static inline int 1400 pci_dev_present(const struct pci_device_id *cur) 1401 { 1402 while (cur != NULL && (cur->vendor || cur->device)) { 1403 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1404 return (1); 1405 } 1406 cur++; 1407 } 1408 return (0); 1409 } 1410 1411 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1412 unsigned int bus, unsigned int devfn); 1413 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1414 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1415 1416 static inline int 1417 pci_domain_nr(struct pci_bus *pbus) 1418 { 1419 1420 return (pbus->domain); 1421 } 1422 1423 static inline int 1424 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1425 int pos, uint32_t *val, int len) 1426 { 1427 1428 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1429 return (0); 1430 } 1431 1432 static inline int 1433 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1434 { 1435 uint32_t tmp; 1436 int ret; 1437 1438 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1439 *val = (u16)tmp; 1440 return (ret); 1441 } 1442 1443 static inline int 1444 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1445 { 1446 uint32_t tmp; 1447 int ret; 1448 1449 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1450 *val = (u8)tmp; 1451 return (ret); 1452 } 1453 1454 static inline int 1455 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1456 uint32_t val, int size) 1457 { 1458 1459 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1460 return (0); 1461 } 1462 1463 static inline int 1464 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1465 uint8_t val) 1466 { 1467 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1468 } 1469 1470 static inline int 1471 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1472 uint16_t val) 1473 { 1474 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1475 } 1476 1477 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1478 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1479 1480 /* -------------------------------------------------------------------------- */ 1481 1482 static inline int 1483 pcim_enable_device(struct pci_dev *pdev) 1484 { 1485 struct pci_devres *dr; 1486 int error; 1487 1488 /* Here we cannot run through the pdev->managed check. */ 1489 dr = lkpi_pci_devres_get_alloc(pdev); 1490 if (dr == NULL) 1491 return (-ENOMEM); 1492 1493 /* If resources were enabled before do not do it again. */ 1494 if (dr->enable_io) 1495 return (0); 1496 1497 error = pci_enable_device(pdev); 1498 if (error == 0) 1499 dr->enable_io = true; 1500 1501 /* This device is not managed. */ 1502 pdev->managed = true; 1503 1504 return (error); 1505 } 1506 1507 static inline void __iomem ** 1508 pcim_iomap_table(struct pci_dev *pdev) 1509 { 1510 struct pcim_iomap_devres *dr; 1511 1512 dr = lkpi_pcim_iomap_devres_find(pdev); 1513 if (dr == NULL) 1514 return (NULL); 1515 1516 /* 1517 * If the driver has manually set a flag to be able to request the 1518 * resource to use bus_read/write_<n>, return the shadow table. 1519 */ 1520 if (pdev->want_iomap_res) 1521 return ((void **)dr->res_table); 1522 1523 /* This is the Linux default. */ 1524 return (dr->mmio_table); 1525 } 1526 1527 static inline int 1528 pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, const char *name) 1529 { 1530 struct pcim_iomap_devres *dr; 1531 void *res; 1532 uint32_t mappings; 1533 int bar; 1534 1535 dr = lkpi_pcim_iomap_devres_find(pdev); 1536 if (dr == NULL) 1537 return (-ENOMEM); 1538 1539 /* Now iomap all the requested (by "mask") ones. */ 1540 for (bar = mappings = 0; mappings != mask; bar++) { 1541 if ((mask & (1 << bar)) == 0) 1542 continue; 1543 1544 /* Request double is not allowed. */ 1545 if (dr->mmio_table[bar] != NULL) { 1546 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1547 __func__, bar, dr->mmio_table[bar]); 1548 goto err; 1549 } 1550 1551 res = _lkpi_pci_iomap(pdev, bar, 0); 1552 if (res == NULL) 1553 goto err; 1554 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1555 dr->res_table[bar] = res; 1556 1557 mappings |= (1 << bar); 1558 } 1559 1560 return (0); 1561 err: 1562 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1563 if ((mappings & (1 << bar)) != 0) { 1564 res = dr->mmio_table[bar]; 1565 if (res == NULL) 1566 continue; 1567 pci_iounmap(pdev, res); 1568 } 1569 } 1570 1571 return (-EINVAL); 1572 } 1573 1574 static inline int 1575 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1576 { 1577 uint32_t requests, req_mask; 1578 int bar, error; 1579 1580 /* Request all the BARs ("regions") we do not iomap. */ 1581 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1582 for (bar = requests = 0; requests != req_mask; bar++) { 1583 if ((req_mask & (1 << bar)) == 0) 1584 continue; 1585 error = pci_request_region(pdev, bar, name); 1586 if (error != 0 && error != -ENODEV) 1587 goto err; 1588 requests |= (1 << bar); 1589 } 1590 1591 error = pcim_iomap_regions(pdev, mask, name); 1592 if (error != 0) 1593 goto err; 1594 1595 return (0); 1596 1597 err: 1598 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1599 if ((requests & (1 << bar)) != 0) 1600 pci_release_region(pdev, bar); 1601 } 1602 1603 return (-EINVAL); 1604 } 1605 1606 /* 1607 * We cannot simply re-define pci_get_device() as we would normally do 1608 * and then hide it in linux_pci.c as too many semi-native drivers still 1609 * inlucde linux/pci.h and run into the conflict with native PCI. Linux drivers 1610 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1611 */ 1612 static inline struct pci_dev * 1613 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1614 { 1615 1616 return (lkpi_pci_get_device(vendor, device, odev)); 1617 } 1618 1619 /* This is a FreeBSD extension so we can use bus_*(). */ 1620 static inline void 1621 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1622 { 1623 pdev->want_iomap_res = true; 1624 } 1625 1626 static inline bool 1627 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1628 { 1629 1630 return (false); 1631 } 1632 1633 static inline void * 1634 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1635 { 1636 1637 return (NULL); 1638 } 1639 1640 static inline void 1641 pci_ignore_hotplug(struct pci_dev *pdev) 1642 { 1643 } 1644 1645 static inline const char * 1646 pci_power_name(pci_power_t state) 1647 { 1648 int pstate = state + 1; 1649 1650 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1651 return (pci_power_names[pstate]); 1652 else 1653 return (pci_power_names[0]); 1654 } 1655 1656 static inline int 1657 pcie_get_readrq(struct pci_dev *dev) 1658 { 1659 u16 ctl; 1660 1661 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1662 return (-EINVAL); 1663 1664 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1665 } 1666 1667 static inline bool 1668 pci_is_enabled(struct pci_dev *pdev) 1669 { 1670 1671 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1672 PCIM_CMD_BUSMASTEREN) != 0); 1673 } 1674 1675 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1676