1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <sys/rman.h> 47 #include <sys/bus.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 #define MODULE_DEVICE_TABLE(bus, table) 74 75 #define PCI_ANY_ID -1U 76 77 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 78 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 79 #define PCI_FUNC(devfn) ((devfn) & 0x07) 80 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 81 82 #define PCI_VDEVICE(_vendor, _device) \ 83 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 84 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 85 #define PCI_DEVICE(_vendor, _device) \ 86 .vendor = (_vendor), .device = (_device), \ 87 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 88 89 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 90 91 #define PCI_VENDOR_ID PCIR_DEVVENDOR 92 #define PCI_COMMAND PCIR_COMMAND 93 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 94 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 95 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 96 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 97 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 98 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 99 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 100 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 101 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 102 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 103 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 104 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 105 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 106 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 107 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 108 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 109 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 110 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 111 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 112 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 113 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 114 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 115 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 116 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 117 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 118 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 119 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 120 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 121 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 122 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 123 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 124 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 125 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 126 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 127 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 128 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 129 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 130 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 131 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 132 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 133 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 134 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 135 #define PCI_EXP_LNKCTL2_TLS 0x000f 136 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 137 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 138 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 139 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 140 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 141 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 142 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 143 144 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 145 #define PCI_EXP_DEVSTA_TRPND 0x0020 146 147 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 148 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 149 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 150 151 enum pci_bus_speed { 152 PCI_SPEED_UNKNOWN = -1, 153 PCIE_SPEED_2_5GT, 154 PCIE_SPEED_5_0GT, 155 PCIE_SPEED_8_0GT, 156 PCIE_SPEED_16_0GT, 157 }; 158 159 enum pcie_link_width { 160 PCIE_LNK_WIDTH_RESRV = 0x00, 161 PCIE_LNK_X1 = 0x01, 162 PCIE_LNK_X2 = 0x02, 163 PCIE_LNK_X4 = 0x04, 164 PCIE_LNK_X8 = 0x08, 165 PCIE_LNK_X12 = 0x0c, 166 PCIE_LNK_X16 = 0x10, 167 PCIE_LNK_X32 = 0x20, 168 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 169 }; 170 171 #define PCIE_LINK_STATE_L0S 0x00000001 172 #define PCIE_LINK_STATE_L1 0x00000002 173 #define PCIE_LINK_STATE_CLKPM 0x00000004 174 175 typedef int pci_power_t; 176 177 #define PCI_D0 PCI_POWERSTATE_D0 178 #define PCI_D1 PCI_POWERSTATE_D1 179 #define PCI_D2 PCI_POWERSTATE_D2 180 #define PCI_D3hot PCI_POWERSTATE_D3 181 #define PCI_D3cold 4 182 183 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 184 185 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 186 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 187 188 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 189 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 190 191 #define PCI_L1SS_CTL1 0x8 192 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 193 194 #define PCI_IRQ_LEGACY 0x01 195 #define PCI_IRQ_MSI 0x02 196 #define PCI_IRQ_MSIX 0x04 197 198 struct pci_dev; 199 200 struct pci_driver { 201 struct list_head node; 202 char *name; 203 const struct pci_device_id *id_table; 204 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 205 void (*remove)(struct pci_dev *dev); 206 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 207 int (*resume) (struct pci_dev *dev); /* Device woken up */ 208 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 209 driver_t bsddriver; 210 devclass_t bsdclass; 211 struct device_driver driver; 212 const struct pci_error_handlers *err_handler; 213 bool isdrm; 214 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 215 const nvlist_t *pf_config); 216 void (*bsd_iov_uninit)(device_t dev); 217 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 218 const nvlist_t *vf_config); 219 }; 220 221 struct pci_bus { 222 struct pci_dev *self; 223 int domain; 224 int number; 225 }; 226 227 extern struct list_head pci_drivers; 228 extern struct list_head pci_devices; 229 extern spinlock_t pci_lock; 230 231 #define __devexit_p(x) x 232 233 #define module_pci_driver(_driver) \ 234 \ 235 static inline int \ 236 _pci_init(void) \ 237 { \ 238 \ 239 return (linux_pci_register_driver(&_driver)); \ 240 } \ 241 \ 242 static inline void \ 243 _pci_exit(void) \ 244 { \ 245 \ 246 linux_pci_unregister_driver(&_driver); \ 247 } \ 248 \ 249 module_init(_pci_init); \ 250 module_exit(_pci_exit) 251 252 /* 253 * If we find drivers accessing this from multiple KPIs we may have to 254 * refcount objects of this structure. 255 */ 256 struct pci_mmio_region { 257 TAILQ_ENTRY(pci_mmio_region) next; 258 struct resource *res; 259 int rid; 260 int type; 261 }; 262 263 struct pci_dev { 264 struct device dev; 265 struct list_head links; 266 struct pci_driver *pdrv; 267 struct pci_bus *bus; 268 struct pci_dev *root; 269 uint16_t device; 270 uint16_t vendor; 271 uint16_t subsystem_vendor; 272 uint16_t subsystem_device; 273 unsigned int irq; 274 unsigned int devfn; 275 uint32_t class; 276 uint8_t revision; 277 bool managed; /* devres "pcim_*(). */ 278 bool want_iomap_res; 279 bool msi_enabled; 280 bool msix_enabled; 281 phys_addr_t rom; 282 size_t romlen; 283 284 TAILQ_HEAD(, pci_mmio_region) mmio; 285 }; 286 287 /* We need some meta-struct to keep track of these for devres. */ 288 struct pci_devres { 289 bool enable_io; 290 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 291 uint8_t region_mask; 292 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 293 }; 294 struct pcim_iomap_devres { 295 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 296 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 297 }; 298 299 /* Internal helper function(s). */ 300 struct pci_dev *lkpinew_pci_dev(device_t); 301 void lkpi_pci_devres_release(struct device *, void *); 302 void lkpi_pcim_iomap_table_release(struct device *, void *); 303 304 static inline int 305 pci_resource_type(struct pci_dev *pdev, int bar) 306 { 307 struct pci_map *pm; 308 309 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 310 if (!pm) 311 return (-1); 312 313 if (PCI_BAR_IO(pm->pm_value)) 314 return (SYS_RES_IOPORT); 315 else 316 return (SYS_RES_MEMORY); 317 } 318 319 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 320 struct resource_list *rl, int type, int rid); 321 322 static inline struct resource_list_entry * 323 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 324 { 325 struct pci_devinfo *dinfo; 326 struct resource_list *rl; 327 struct resource_list_entry *rle; 328 329 dinfo = device_get_ivars(pdev->dev.bsddev); 330 rl = &dinfo->resources; 331 rle = resource_list_find(rl, type, rid); 332 /* Reserve resources for this BAR if needed. */ 333 if (rle == NULL && reserve_bar) 334 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 335 return (rle); 336 } 337 338 static inline struct resource_list_entry * 339 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 340 { 341 int type; 342 343 type = pci_resource_type(pdev, bar); 344 if (type < 0) 345 return (NULL); 346 bar = PCIR_BAR(bar); 347 return (linux_pci_get_rle(pdev, type, bar, reserve)); 348 } 349 350 static inline struct device * 351 linux_pci_find_irq_dev(unsigned int irq) 352 { 353 struct pci_dev *pdev; 354 struct device *found; 355 356 found = NULL; 357 spin_lock(&pci_lock); 358 list_for_each_entry(pdev, &pci_devices, links) { 359 if (irq == pdev->dev.irq || 360 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 361 found = &pdev->dev; 362 break; 363 } 364 } 365 spin_unlock(&pci_lock); 366 return (found); 367 } 368 369 /* 370 * All drivers just seem to want to inspect the type not flags. 371 */ 372 static inline int 373 pci_resource_flags(struct pci_dev *pdev, int bar) 374 { 375 int type; 376 377 type = pci_resource_type(pdev, bar); 378 if (type < 0) 379 return (0); 380 return (1 << type); 381 } 382 383 static inline const char * 384 pci_name(struct pci_dev *d) 385 { 386 387 return device_get_desc(d->dev.bsddev); 388 } 389 390 static inline void * 391 pci_get_drvdata(struct pci_dev *pdev) 392 { 393 394 return dev_get_drvdata(&pdev->dev); 395 } 396 397 static inline void 398 pci_set_drvdata(struct pci_dev *pdev, void *data) 399 { 400 401 dev_set_drvdata(&pdev->dev, data); 402 } 403 404 static inline struct pci_dev * 405 pci_dev_get(struct pci_dev *pdev) 406 { 407 408 if (pdev != NULL) 409 get_device(&pdev->dev); 410 return (pdev); 411 } 412 413 static __inline void 414 pci_dev_put(struct pci_dev *pdev) 415 { 416 417 if (pdev != NULL) 418 put_device(&pdev->dev); 419 } 420 421 static inline int 422 pci_enable_device(struct pci_dev *pdev) 423 { 424 425 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 426 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 427 return (0); 428 } 429 430 static inline void 431 pci_disable_device(struct pci_dev *pdev) 432 { 433 434 pci_disable_busmaster(pdev->dev.bsddev); 435 } 436 437 static inline int 438 pci_set_master(struct pci_dev *pdev) 439 { 440 441 pci_enable_busmaster(pdev->dev.bsddev); 442 return (0); 443 } 444 445 static inline int 446 pci_set_power_state(struct pci_dev *pdev, int state) 447 { 448 449 pci_set_powerstate(pdev->dev.bsddev, state); 450 return (0); 451 } 452 453 static inline int 454 pci_clear_master(struct pci_dev *pdev) 455 { 456 457 pci_disable_busmaster(pdev->dev.bsddev); 458 return (0); 459 } 460 461 static inline struct pci_devres * 462 lkpi_pci_devres_get_alloc(struct pci_dev *pdev) 463 { 464 struct pci_devres *dr; 465 466 dr = lkpi_devres_find(&pdev->dev, lkpi_pci_devres_release, NULL, NULL); 467 if (dr == NULL) { 468 dr = lkpi_devres_alloc(lkpi_pci_devres_release, sizeof(*dr), 469 GFP_KERNEL | __GFP_ZERO); 470 if (dr != NULL) 471 lkpi_devres_add(&pdev->dev, dr); 472 } 473 474 return (dr); 475 } 476 static inline struct pci_devres * 477 lkpi_pci_devres_find(struct pci_dev *pdev) 478 { 479 480 if (!pdev->managed) 481 return (NULL); 482 483 return (lkpi_pci_devres_get_alloc(pdev)); 484 } 485 486 static inline int 487 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 488 { 489 struct resource *res; 490 struct pci_devres *dr; 491 struct pci_mmio_region *mmio; 492 int rid; 493 int type; 494 495 type = pci_resource_type(pdev, bar); 496 if (type < 0) 497 return (-ENODEV); 498 rid = PCIR_BAR(bar); 499 res = bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 500 RF_ACTIVE|RF_SHAREABLE); 501 if (res == NULL) { 502 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 503 "bar %d type %d rid %d\n", 504 __func__, bar, type, PCIR_BAR(bar)); 505 return (-ENODEV); 506 } 507 508 /* 509 * It seems there is an implicit devres tracking on these if the device 510 * is managed; otherwise the resources are not automatiaclly freed on 511 * FreeBSD/LinuxKPI tough they should be/are expected to be by Linux 512 * drivers. 513 */ 514 dr = lkpi_pci_devres_find(pdev); 515 if (dr != NULL) { 516 dr->region_mask |= (1 << bar); 517 dr->region_table[bar] = res; 518 } 519 520 /* Even if the device is not managed we need to track it for iomap. */ 521 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 522 mmio->rid = PCIR_BAR(bar); 523 mmio->type = type; 524 mmio->res = res; 525 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 526 527 return (0); 528 } 529 530 static inline void 531 pci_release_region(struct pci_dev *pdev, int bar) 532 { 533 struct resource_list_entry *rle; 534 struct pci_devres *dr; 535 struct pci_mmio_region *mmio, *p; 536 537 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 538 return; 539 540 /* 541 * As we implicitly track the requests we also need to clear them on 542 * release. Do clear before resource release. 543 */ 544 dr = lkpi_pci_devres_find(pdev); 545 if (dr != NULL) { 546 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 547 " region_table res %p != rel->res %p\n", __func__, pdev, 548 bar, dr->region_table[bar], rle->res)); 549 dr->region_table[bar] = NULL; 550 dr->region_mask &= ~(1 << bar); 551 } 552 553 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 554 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 555 continue; 556 TAILQ_REMOVE(&pdev->mmio, mmio, next); 557 free(mmio, M_DEVBUF); 558 } 559 560 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 561 } 562 563 static inline void 564 pci_release_regions(struct pci_dev *pdev) 565 { 566 int i; 567 568 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 569 pci_release_region(pdev, i); 570 } 571 572 static inline int 573 pci_request_regions(struct pci_dev *pdev, const char *res_name) 574 { 575 int error; 576 int i; 577 578 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 579 error = pci_request_region(pdev, i, res_name); 580 if (error && error != -ENODEV) { 581 pci_release_regions(pdev); 582 return (error); 583 } 584 } 585 return (0); 586 } 587 588 static inline void 589 lkpi_pci_disable_msix(struct pci_dev *pdev) 590 { 591 592 pci_release_msi(pdev->dev.bsddev); 593 594 /* 595 * The MSIX IRQ numbers associated with this PCI device are no 596 * longer valid and might be re-assigned. Make sure 597 * linux_pci_find_irq_dev() does no longer see them by 598 * resetting their references to zero: 599 */ 600 pdev->dev.irq_start = 0; 601 pdev->dev.irq_end = 0; 602 pdev->msix_enabled = false; 603 } 604 /* Only for consistency. No conflict on that one. */ 605 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 606 607 static inline void 608 lkpi_pci_disable_msi(struct pci_dev *pdev) 609 { 610 611 pci_release_msi(pdev->dev.bsddev); 612 613 pdev->dev.irq_start = 0; 614 pdev->dev.irq_end = 0; 615 pdev->irq = pdev->dev.irq; 616 pdev->msi_enabled = false; 617 } 618 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 619 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 620 621 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 622 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 623 624 static inline bus_addr_t 625 pci_bus_address(struct pci_dev *pdev, int bar) 626 { 627 628 return (pci_resource_start(pdev, bar)); 629 } 630 631 #define PCI_CAP_ID_EXP PCIY_EXPRESS 632 #define PCI_CAP_ID_PCIX PCIY_PCIX 633 #define PCI_CAP_ID_AGP PCIY_AGP 634 #define PCI_CAP_ID_PM PCIY_PMG 635 636 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 637 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 638 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 639 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 640 #define PCI_EXP_LNKSTA PCIER_LINK_STA 641 642 static inline int 643 pci_find_capability(struct pci_dev *pdev, int capid) 644 { 645 int reg; 646 647 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 648 return (0); 649 return (reg); 650 } 651 652 static inline int pci_pcie_cap(struct pci_dev *dev) 653 { 654 return pci_find_capability(dev, PCI_CAP_ID_EXP); 655 } 656 657 static inline int 658 pci_find_ext_capability(struct pci_dev *pdev, int capid) 659 { 660 int reg; 661 662 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 663 return (0); 664 return (reg); 665 } 666 667 #define PCIM_PCAP_PME_SHIFT 11 668 static __inline bool 669 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 670 { 671 struct pci_devinfo *dinfo; 672 pcicfgregs *cfg; 673 674 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 675 return (false); 676 677 dinfo = device_get_ivars(pdev->dev.bsddev); 678 cfg = &dinfo->cfg; 679 680 if (cfg->pp.pp_cap == 0) 681 return (false); 682 683 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 684 return (true); 685 686 return (false); 687 } 688 689 static inline int 690 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 691 { 692 693 if (!pci_enable_aspm) 694 return (-EPERM); 695 696 return (-ENXIO); 697 } 698 699 static inline int 700 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 701 { 702 703 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 704 return (0); 705 } 706 707 static inline int 708 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 709 { 710 711 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 712 return (0); 713 } 714 715 static inline int 716 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 717 { 718 719 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 720 return (0); 721 } 722 723 static inline int 724 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 725 { 726 727 pci_write_config(pdev->dev.bsddev, where, val, 1); 728 return (0); 729 } 730 731 static inline int 732 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 733 { 734 735 pci_write_config(pdev->dev.bsddev, where, val, 2); 736 return (0); 737 } 738 739 static inline int 740 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 741 { 742 743 pci_write_config(pdev->dev.bsddev, where, val, 4); 744 return (0); 745 } 746 747 int linux_pci_register_driver(struct pci_driver *pdrv); 748 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 749 void linux_pci_unregister_driver(struct pci_driver *pdrv); 750 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 751 752 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 753 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 754 755 struct msix_entry { 756 int entry; 757 int vector; 758 }; 759 760 /* 761 * Enable msix, positive errors indicate actual number of available 762 * vectors. Negative errors are failures. 763 * 764 * NB: define added to prevent this definition of pci_enable_msix from 765 * clashing with the native FreeBSD version. 766 */ 767 #define pci_enable_msix(...) \ 768 linux_pci_enable_msix(__VA_ARGS__) 769 770 static inline int 771 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 772 { 773 struct resource_list_entry *rle; 774 int error; 775 int avail; 776 int i; 777 778 avail = pci_msix_count(pdev->dev.bsddev); 779 if (avail < nreq) { 780 if (avail == 0) 781 return -EINVAL; 782 return avail; 783 } 784 avail = nreq; 785 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 786 return error; 787 /* 788 * Handle case where "pci_alloc_msix()" may allocate less 789 * interrupts than available and return with no error: 790 */ 791 if (avail < nreq) { 792 pci_release_msi(pdev->dev.bsddev); 793 return avail; 794 } 795 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 796 pdev->dev.irq_start = rle->start; 797 pdev->dev.irq_end = rle->start + avail; 798 for (i = 0; i < nreq; i++) 799 entries[i].vector = pdev->dev.irq_start + i; 800 pdev->msix_enabled = true; 801 return (0); 802 } 803 804 #define pci_enable_msix_range(...) \ 805 linux_pci_enable_msix_range(__VA_ARGS__) 806 807 static inline int 808 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 809 int minvec, int maxvec) 810 { 811 int nvec = maxvec; 812 int rc; 813 814 if (maxvec < minvec) 815 return (-ERANGE); 816 817 do { 818 rc = pci_enable_msix(dev, entries, nvec); 819 if (rc < 0) { 820 return (rc); 821 } else if (rc > 0) { 822 if (rc < minvec) 823 return (-ENOSPC); 824 nvec = rc; 825 } 826 } while (rc); 827 return (nvec); 828 } 829 830 #define pci_enable_msi(pdev) \ 831 linux_pci_enable_msi(pdev) 832 833 static inline int 834 pci_enable_msi(struct pci_dev *pdev) 835 { 836 struct resource_list_entry *rle; 837 int error; 838 int avail; 839 840 avail = pci_msi_count(pdev->dev.bsddev); 841 if (avail < 1) 842 return -EINVAL; 843 844 avail = 1; /* this function only enable one MSI IRQ */ 845 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 846 return error; 847 848 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 849 pdev->dev.irq_start = rle->start; 850 pdev->dev.irq_end = rle->start + avail; 851 pdev->irq = rle->start; 852 pdev->msi_enabled = true; 853 return (0); 854 } 855 856 static inline int 857 pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 858 unsigned int flags) 859 { 860 int error; 861 862 if (flags & PCI_IRQ_MSIX) { 863 struct msix_entry *entries; 864 int i; 865 866 entries = kcalloc(maxv, sizeof(*entries), GFP_KERNEL); 867 if (entries == NULL) { 868 error = -ENOMEM; 869 goto out; 870 } 871 for (i = 0; i < maxv; ++i) 872 entries[i].entry = i; 873 error = pci_enable_msix(pdev, entries, maxv); 874 out: 875 kfree(entries); 876 if (error == 0 && pdev->msix_enabled) 877 return (pdev->dev.irq_end - pdev->dev.irq_start); 878 } 879 if (flags & PCI_IRQ_MSI) { 880 error = pci_enable_msi(pdev); 881 if (error == 0 && pdev->msi_enabled) 882 return (pdev->dev.irq_end - pdev->dev.irq_start); 883 } 884 if (flags & PCI_IRQ_LEGACY) { 885 if (pdev->irq) 886 return (1); 887 } 888 889 return (-EINVAL); 890 } 891 892 static inline int 893 pci_channel_offline(struct pci_dev *pdev) 894 { 895 896 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 897 } 898 899 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 900 { 901 return -ENODEV; 902 } 903 static inline void pci_disable_sriov(struct pci_dev *dev) 904 { 905 } 906 907 static inline struct resource * 908 _lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size __unused) 909 { 910 struct pci_mmio_region *mmio, *p; 911 int type; 912 913 type = pci_resource_type(pdev, bar); 914 if (type < 0) { 915 device_printf(pdev->dev.bsddev, "%s: bar %d type %d\n", 916 __func__, bar, type); 917 return (NULL); 918 } 919 920 /* 921 * Check for duplicate mappings. 922 * This can happen if a driver calls pci_request_region() first. 923 */ 924 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 925 if (mmio->type == type && mmio->rid == PCIR_BAR(bar)) { 926 return (mmio->res); 927 } 928 } 929 930 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 931 mmio->rid = PCIR_BAR(bar); 932 mmio->type = type; 933 mmio->res = bus_alloc_resource_any(pdev->dev.bsddev, mmio->type, 934 &mmio->rid, RF_ACTIVE|RF_SHAREABLE); 935 if (mmio->res == NULL) { 936 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 937 "bar %d type %d rid %d\n", 938 __func__, bar, type, PCIR_BAR(bar)); 939 free(mmio, M_DEVBUF); 940 return (NULL); 941 } 942 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 943 944 return (mmio->res); 945 } 946 947 static inline void * 948 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 949 { 950 struct resource *res; 951 952 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 953 if (res == NULL) 954 return (NULL); 955 /* This is a FreeBSD extension so we can use bus_*(). */ 956 if (pdev->want_iomap_res) 957 return (res); 958 return ((void *)rman_get_bushandle(res)); 959 } 960 961 static inline void 962 pci_iounmap(struct pci_dev *pdev, void *res) 963 { 964 struct pci_mmio_region *mmio, *p; 965 966 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 967 if (res != (void *)rman_get_bushandle(mmio->res)) 968 continue; 969 bus_release_resource(pdev->dev.bsddev, 970 mmio->type, mmio->rid, mmio->res); 971 TAILQ_REMOVE(&pdev->mmio, mmio, next); 972 free(mmio, M_DEVBUF); 973 return; 974 } 975 } 976 977 static inline void 978 lkpi_pci_save_state(struct pci_dev *pdev) 979 { 980 981 pci_save_state(pdev->dev.bsddev); 982 } 983 984 static inline void 985 lkpi_pci_restore_state(struct pci_dev *pdev) 986 { 987 988 pci_restore_state(pdev->dev.bsddev); 989 } 990 991 #define pci_save_state(dev) lkpi_pci_save_state(dev) 992 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 993 994 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 995 const struct pci_device_id _table[] __devinitdata 996 997 /* XXX This should not be necessary. */ 998 #define pcix_set_mmrbc(d, v) 0 999 #define pcix_get_max_mmrbc(d) 0 1000 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 1001 1002 #define PCI_DMA_BIDIRECTIONAL 0 1003 #define PCI_DMA_TODEVICE 1 1004 #define PCI_DMA_FROMDEVICE 2 1005 #define PCI_DMA_NONE 3 1006 1007 #define pci_pool dma_pool 1008 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 1009 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 1010 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 1011 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 1012 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 1013 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 1014 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1015 _size, _vaddr, _dma_handle) 1016 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 1017 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1018 _sg, _nents, (enum dma_data_direction)_dir) 1019 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 1020 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1021 (_ptr), (_size), (enum dma_data_direction)_dir) 1022 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 1023 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1024 _addr, _size, (enum dma_data_direction)_dir) 1025 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 1026 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1027 _sg, _nents, (enum dma_data_direction)_dir) 1028 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 1029 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 1030 _offset, _size, (enum dma_data_direction)_dir) 1031 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 1032 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1033 _dma_address, _size, (enum dma_data_direction)_dir) 1034 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1035 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1036 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1037 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1038 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1039 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1040 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1041 #define pci_unmap_addr dma_unmap_addr 1042 #define pci_unmap_addr_set dma_unmap_addr_set 1043 #define pci_unmap_len dma_unmap_len 1044 #define pci_unmap_len_set dma_unmap_len_set 1045 1046 typedef unsigned int __bitwise pci_channel_state_t; 1047 typedef unsigned int __bitwise pci_ers_result_t; 1048 1049 enum pci_channel_state { 1050 pci_channel_io_normal = 1, 1051 pci_channel_io_frozen = 2, 1052 pci_channel_io_perm_failure = 3, 1053 }; 1054 1055 enum pci_ers_result { 1056 PCI_ERS_RESULT_NONE = 1, 1057 PCI_ERS_RESULT_CAN_RECOVER = 2, 1058 PCI_ERS_RESULT_NEED_RESET = 3, 1059 PCI_ERS_RESULT_DISCONNECT = 4, 1060 PCI_ERS_RESULT_RECOVERED = 5, 1061 }; 1062 1063 /* PCI bus error event callbacks */ 1064 struct pci_error_handlers { 1065 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1066 enum pci_channel_state error); 1067 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1068 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1069 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1070 void (*resume)(struct pci_dev *dev); 1071 }; 1072 1073 /* FreeBSD does not support SRIOV - yet */ 1074 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1075 { 1076 return dev; 1077 } 1078 1079 static inline bool pci_is_pcie(struct pci_dev *dev) 1080 { 1081 return !!pci_pcie_cap(dev); 1082 } 1083 1084 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1085 { 1086 int pos; 1087 u16 reg16; 1088 1089 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1090 if (!pos) 1091 return 0; 1092 1093 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1094 1095 return reg16; 1096 } 1097 1098 static inline int pci_pcie_type(struct pci_dev *dev) 1099 { 1100 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1101 } 1102 1103 static inline int pcie_cap_version(struct pci_dev *dev) 1104 { 1105 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1106 } 1107 1108 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1109 { 1110 int type = pci_pcie_type(dev); 1111 1112 return pcie_cap_version(dev) > 1 || 1113 type == PCI_EXP_TYPE_ROOT_PORT || 1114 type == PCI_EXP_TYPE_ENDPOINT || 1115 type == PCI_EXP_TYPE_LEG_END; 1116 } 1117 1118 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1119 { 1120 return true; 1121 } 1122 1123 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1124 { 1125 int type = pci_pcie_type(dev); 1126 1127 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1128 (type == PCI_EXP_TYPE_DOWNSTREAM && 1129 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1130 } 1131 1132 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1133 { 1134 int type = pci_pcie_type(dev); 1135 1136 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1137 type == PCI_EXP_TYPE_RC_EC; 1138 } 1139 1140 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1141 { 1142 if (!pci_is_pcie(dev)) 1143 return false; 1144 1145 switch (pos) { 1146 case PCI_EXP_FLAGS_TYPE: 1147 return true; 1148 case PCI_EXP_DEVCAP: 1149 case PCI_EXP_DEVCTL: 1150 case PCI_EXP_DEVSTA: 1151 return pcie_cap_has_devctl(dev); 1152 case PCI_EXP_LNKCAP: 1153 case PCI_EXP_LNKCTL: 1154 case PCI_EXP_LNKSTA: 1155 return pcie_cap_has_lnkctl(dev); 1156 case PCI_EXP_SLTCAP: 1157 case PCI_EXP_SLTCTL: 1158 case PCI_EXP_SLTSTA: 1159 return pcie_cap_has_sltctl(dev); 1160 case PCI_EXP_RTCTL: 1161 case PCI_EXP_RTCAP: 1162 case PCI_EXP_RTSTA: 1163 return pcie_cap_has_rtctl(dev); 1164 case PCI_EXP_DEVCAP2: 1165 case PCI_EXP_DEVCTL2: 1166 case PCI_EXP_LNKCAP2: 1167 case PCI_EXP_LNKCTL2: 1168 case PCI_EXP_LNKSTA2: 1169 return pcie_cap_version(dev) > 1; 1170 default: 1171 return false; 1172 } 1173 } 1174 1175 static inline int 1176 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1177 { 1178 if (pos & 3) 1179 return -EINVAL; 1180 1181 if (!pcie_capability_reg_implemented(dev, pos)) 1182 return -EINVAL; 1183 1184 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1185 } 1186 1187 static inline int 1188 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1189 { 1190 if (pos & 3) 1191 return -EINVAL; 1192 1193 if (!pcie_capability_reg_implemented(dev, pos)) 1194 return -EINVAL; 1195 1196 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1197 } 1198 1199 static inline int 1200 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1201 { 1202 if (pos & 1) 1203 return -EINVAL; 1204 1205 if (!pcie_capability_reg_implemented(dev, pos)) 1206 return 0; 1207 1208 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1209 } 1210 1211 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1212 enum pci_bus_speed *speed, enum pcie_link_width *width) 1213 { 1214 *speed = PCI_SPEED_UNKNOWN; 1215 *width = PCIE_LNK_WIDTH_UNKNOWN; 1216 return (0); 1217 } 1218 1219 static inline int 1220 pci_num_vf(struct pci_dev *dev) 1221 { 1222 return (0); 1223 } 1224 1225 static inline enum pci_bus_speed 1226 pcie_get_speed_cap(struct pci_dev *dev) 1227 { 1228 device_t root; 1229 uint32_t lnkcap, lnkcap2; 1230 int error, pos; 1231 1232 root = device_get_parent(dev->dev.bsddev); 1233 if (root == NULL) 1234 return (PCI_SPEED_UNKNOWN); 1235 root = device_get_parent(root); 1236 if (root == NULL) 1237 return (PCI_SPEED_UNKNOWN); 1238 root = device_get_parent(root); 1239 if (root == NULL) 1240 return (PCI_SPEED_UNKNOWN); 1241 1242 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1243 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1244 return (PCI_SPEED_UNKNOWN); 1245 1246 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1247 return (PCI_SPEED_UNKNOWN); 1248 1249 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1250 1251 if (lnkcap2) { /* PCIe r3.0-compliant */ 1252 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1253 return (PCIE_SPEED_2_5GT); 1254 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1255 return (PCIE_SPEED_5_0GT); 1256 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1257 return (PCIE_SPEED_8_0GT); 1258 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1259 return (PCIE_SPEED_16_0GT); 1260 } else { /* pre-r3.0 */ 1261 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1262 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1263 return (PCIE_SPEED_2_5GT); 1264 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1265 return (PCIE_SPEED_5_0GT); 1266 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1267 return (PCIE_SPEED_8_0GT); 1268 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1269 return (PCIE_SPEED_16_0GT); 1270 } 1271 return (PCI_SPEED_UNKNOWN); 1272 } 1273 1274 static inline enum pcie_link_width 1275 pcie_get_width_cap(struct pci_dev *dev) 1276 { 1277 uint32_t lnkcap; 1278 1279 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1280 if (lnkcap) 1281 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1282 1283 return (PCIE_LNK_WIDTH_UNKNOWN); 1284 } 1285 1286 static inline int 1287 pcie_get_mps(struct pci_dev *dev) 1288 { 1289 return (pci_get_max_payload(dev->dev.bsddev)); 1290 } 1291 1292 static inline uint32_t 1293 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1294 { 1295 1296 switch(spd) { 1297 case PCIE_SPEED_16_0GT: 1298 return (16000 * 128 / 130); 1299 case PCIE_SPEED_8_0GT: 1300 return (8000 * 128 / 130); 1301 case PCIE_SPEED_5_0GT: 1302 return (5000 * 8 / 10); 1303 case PCIE_SPEED_2_5GT: 1304 return (2500 * 8 / 10); 1305 default: 1306 return (0); 1307 } 1308 } 1309 1310 static inline uint32_t 1311 pcie_bandwidth_available(struct pci_dev *pdev, 1312 struct pci_dev **limiting, 1313 enum pci_bus_speed *speed, 1314 enum pcie_link_width *width) 1315 { 1316 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1317 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1318 1319 if (speed) 1320 *speed = nspeed; 1321 if (width) 1322 *width = nwidth; 1323 1324 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1325 } 1326 1327 static inline struct pci_dev * 1328 pcie_find_root_port(struct pci_dev *pdev) 1329 { 1330 device_t root; 1331 1332 if (pdev->root != NULL) 1333 return (pdev->root); 1334 1335 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1336 if (root == NULL) 1337 return (NULL); 1338 1339 pdev->root = lkpinew_pci_dev(root); 1340 return (pdev->root); 1341 } 1342 1343 /* This is needed when people rip out the device "HotPlug". */ 1344 static inline void 1345 pci_lock_rescan_remove(void) 1346 { 1347 } 1348 1349 static inline void 1350 pci_unlock_rescan_remove(void) 1351 { 1352 } 1353 1354 static __inline void 1355 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1356 { 1357 } 1358 1359 /* 1360 * The following functions can be used to attach/detach the LinuxKPI's 1361 * PCI device runtime. The pci_driver and pci_device_id pointer is 1362 * allowed to be NULL. Other pointers must be all valid. 1363 * The pci_dev structure should be zero-initialized before passed 1364 * to the linux_pci_attach_device function. 1365 */ 1366 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1367 const struct pci_device_id *, struct pci_dev *); 1368 extern int linux_pci_detach_device(struct pci_dev *); 1369 1370 static inline int 1371 pci_dev_present(const struct pci_device_id *cur) 1372 { 1373 while (cur != NULL && (cur->vendor || cur->device)) { 1374 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1375 return (1); 1376 } 1377 cur++; 1378 } 1379 return (0); 1380 } 1381 1382 static inline bool 1383 pci_is_root_bus(struct pci_bus *pbus) 1384 { 1385 1386 return (pbus->self == NULL); 1387 } 1388 1389 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1390 unsigned int bus, unsigned int devfn); 1391 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1392 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1393 1394 static inline int 1395 pci_domain_nr(struct pci_bus *pbus) 1396 { 1397 1398 return (pbus->domain); 1399 } 1400 1401 static inline int 1402 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1403 int pos, uint32_t *val, int len) 1404 { 1405 1406 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1407 return (0); 1408 } 1409 1410 static inline int 1411 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1412 { 1413 uint32_t tmp; 1414 int ret; 1415 1416 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1417 *val = (u16)tmp; 1418 return (ret); 1419 } 1420 1421 static inline int 1422 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1423 { 1424 uint32_t tmp; 1425 int ret; 1426 1427 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1428 *val = (u8)tmp; 1429 return (ret); 1430 } 1431 1432 static inline int 1433 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1434 uint32_t val, int size) 1435 { 1436 1437 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1438 return (0); 1439 } 1440 1441 static inline int 1442 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1443 uint8_t val) 1444 { 1445 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1446 } 1447 1448 static inline int 1449 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1450 uint16_t val) 1451 { 1452 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1453 } 1454 1455 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1456 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1457 1458 /* -------------------------------------------------------------------------- */ 1459 1460 static inline int 1461 pcim_enable_device(struct pci_dev *pdev) 1462 { 1463 struct pci_devres *dr; 1464 int error; 1465 1466 /* Here we cannot run through the pdev->managed check. */ 1467 dr = lkpi_pci_devres_get_alloc(pdev); 1468 if (dr == NULL) 1469 return (-ENOMEM); 1470 1471 /* If resources were enabled before do not do it again. */ 1472 if (dr->enable_io) 1473 return (0); 1474 1475 error = pci_enable_device(pdev); 1476 if (error == 0) 1477 dr->enable_io = true; 1478 1479 /* This device is not managed. */ 1480 pdev->managed = true; 1481 1482 return (error); 1483 } 1484 1485 static inline struct pcim_iomap_devres * 1486 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev) 1487 { 1488 struct pcim_iomap_devres *dr; 1489 1490 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release, 1491 NULL, NULL); 1492 if (dr == NULL) { 1493 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release, 1494 sizeof(*dr), GFP_KERNEL | __GFP_ZERO); 1495 if (dr != NULL) 1496 lkpi_devres_add(&pdev->dev, dr); 1497 } 1498 1499 if (dr == NULL) 1500 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__); 1501 1502 return (dr); 1503 } 1504 1505 static inline void __iomem ** 1506 pcim_iomap_table(struct pci_dev *pdev) 1507 { 1508 struct pcim_iomap_devres *dr; 1509 1510 dr = lkpi_pcim_iomap_devres_find(pdev); 1511 if (dr == NULL) 1512 return (NULL); 1513 1514 /* 1515 * If the driver has manually set a flag to be able to request the 1516 * resource to use bus_read/write_<n>, return the shadow table. 1517 */ 1518 if (pdev->want_iomap_res) 1519 return ((void **)dr->res_table); 1520 1521 /* This is the Linux default. */ 1522 return (dr->mmio_table); 1523 } 1524 1525 static inline int 1526 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1527 { 1528 struct pcim_iomap_devres *dr; 1529 void *res; 1530 uint32_t mappings, requests, req_mask; 1531 int bar, error; 1532 1533 dr = lkpi_pcim_iomap_devres_find(pdev); 1534 if (dr == NULL) 1535 return (-ENOMEM); 1536 1537 /* Request all the BARs ("regions") we do not iomap. */ 1538 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1539 for (bar = requests = 0; requests != req_mask; bar++) { 1540 if ((req_mask & (1 << bar)) == 0) 1541 continue; 1542 error = pci_request_region(pdev, bar, name); 1543 if (error != 0 && error != -ENODEV) 1544 goto err; 1545 requests |= (1 << bar); 1546 } 1547 1548 /* Now iomap all the requested (by "mask") ones. */ 1549 for (bar = mappings = 0; mappings != mask; bar++) { 1550 if ((mask & (1 << bar)) == 0) 1551 continue; 1552 1553 /* Request double is not allowed. */ 1554 if (dr->mmio_table[bar] != NULL) { 1555 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1556 __func__, bar, dr->mmio_table[bar]); 1557 goto err; 1558 } 1559 1560 res = _lkpi_pci_iomap(pdev, bar, 0); 1561 if (res == NULL) 1562 goto err; 1563 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1564 dr->res_table[bar] = res; 1565 1566 mappings |= (1 << bar); 1567 } 1568 1569 return (0); 1570 1571 err: 1572 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1573 if ((mappings & (1 << bar)) != 0) { 1574 res = dr->mmio_table[bar]; 1575 if (res == NULL) 1576 continue; 1577 pci_iounmap(pdev, res); 1578 } else if ((requests & (1 << bar)) != 0) { 1579 pci_release_region(pdev, bar); 1580 } 1581 } 1582 1583 return (-EINVAL); 1584 } 1585 1586 /* This is a FreeBSD extension so we can use bus_*(). */ 1587 static inline void 1588 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1589 { 1590 pdev->want_iomap_res = true; 1591 } 1592 1593 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1594