1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/pciio.h> 41 #include <sys/rman.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pci_private.h> 45 46 #include <machine/resource.h> 47 48 #include <linux/list.h> 49 #include <linux/dmapool.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/compiler.h> 52 #include <linux/errno.h> 53 #include <asm/atomic.h> 54 #include <linux/device.h> 55 56 struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class; 62 uint32_t class_mask; 63 uintptr_t driver_data; 64 }; 65 66 #define MODULE_DEVICE_TABLE(bus, table) 67 68 #define PCI_BASE_CLASS_DISPLAY 0x03 69 #define PCI_CLASS_DISPLAY_VGA 0x0300 70 #define PCI_CLASS_DISPLAY_OTHER 0x0380 71 #define PCI_BASE_CLASS_BRIDGE 0x06 72 #define PCI_CLASS_BRIDGE_ISA 0x0601 73 74 #define PCI_ANY_ID -1U 75 #define PCI_VENDOR_ID_APPLE 0x106b 76 #define PCI_VENDOR_ID_ASUSTEK 0x1043 77 #define PCI_VENDOR_ID_ATI 0x1002 78 #define PCI_VENDOR_ID_DELL 0x1028 79 #define PCI_VENDOR_ID_HP 0x103c 80 #define PCI_VENDOR_ID_IBM 0x1014 81 #define PCI_VENDOR_ID_INTEL 0x8086 82 #define PCI_VENDOR_ID_MELLANOX 0x15b3 83 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 84 #define PCI_VENDOR_ID_SERVERWORKS 0x1166 85 #define PCI_VENDOR_ID_SONY 0x104d 86 #define PCI_VENDOR_ID_TOPSPIN 0x1867 87 #define PCI_VENDOR_ID_VIA 0x1106 88 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 89 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 90 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 91 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 92 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 93 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 94 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 95 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 96 #define PCI_SUBDEVICE_ID_QEMU 0x1100 97 98 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 99 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 100 #define PCI_FUNC(devfn) ((devfn) & 0x07) 101 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 102 103 #define PCI_VDEVICE(_vendor, _device) \ 104 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 #define PCI_DEVICE(_vendor, _device) \ 107 .vendor = (_vendor), .device = (_device), \ 108 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 109 110 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 111 112 #define PCI_VENDOR_ID PCIR_DEVVENDOR 113 #define PCI_COMMAND PCIR_COMMAND 114 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 115 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 116 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 117 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 118 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 119 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 120 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 121 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 122 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 123 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 124 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 125 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 126 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 127 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 128 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 129 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 130 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 131 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 132 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 133 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 134 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 135 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 136 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 137 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 138 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 139 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 140 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 141 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 142 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 143 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 144 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 145 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 146 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 147 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 148 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 149 150 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 151 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 152 #define PCI_EXP_DEVSTA_TRPND 0x0020 153 154 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 155 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 156 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 157 158 enum pci_bus_speed { 159 PCI_SPEED_UNKNOWN = -1, 160 PCIE_SPEED_2_5GT, 161 PCIE_SPEED_5_0GT, 162 PCIE_SPEED_8_0GT, 163 PCIE_SPEED_16_0GT, 164 }; 165 166 enum pcie_link_width { 167 PCIE_LNK_WIDTH_RESRV = 0x00, 168 PCIE_LNK_X1 = 0x01, 169 PCIE_LNK_X2 = 0x02, 170 PCIE_LNK_X4 = 0x04, 171 PCIE_LNK_X8 = 0x08, 172 PCIE_LNK_X12 = 0x0c, 173 PCIE_LNK_X16 = 0x10, 174 PCIE_LNK_X32 = 0x20, 175 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 176 }; 177 178 typedef int pci_power_t; 179 180 #define PCI_D0 PCI_POWERSTATE_D0 181 #define PCI_D1 PCI_POWERSTATE_D1 182 #define PCI_D2 PCI_POWERSTATE_D2 183 #define PCI_D3hot PCI_POWERSTATE_D3 184 #define PCI_D3cold 4 185 186 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 187 188 struct pci_dev; 189 190 struct pci_driver { 191 struct list_head links; 192 char *name; 193 const struct pci_device_id *id_table; 194 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 195 void (*remove)(struct pci_dev *dev); 196 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 197 int (*resume) (struct pci_dev *dev); /* Device woken up */ 198 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 199 driver_t bsddriver; 200 devclass_t bsdclass; 201 struct device_driver driver; 202 const struct pci_error_handlers *err_handler; 203 bool isdrm; 204 }; 205 206 struct pci_bus { 207 struct pci_dev *self; 208 int domain; 209 int number; 210 }; 211 212 extern struct list_head pci_drivers; 213 extern struct list_head pci_devices; 214 extern spinlock_t pci_lock; 215 216 #define __devexit_p(x) x 217 218 struct pci_dev { 219 struct device dev; 220 struct list_head links; 221 struct pci_driver *pdrv; 222 struct pci_bus *bus; 223 uint16_t device; 224 uint16_t vendor; 225 uint16_t subsystem_vendor; 226 uint16_t subsystem_device; 227 unsigned int irq; 228 unsigned int devfn; 229 uint32_t class; 230 uint8_t revision; 231 }; 232 233 static inline struct resource_list_entry * 234 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 235 { 236 struct pci_devinfo *dinfo; 237 struct resource_list *rl; 238 239 dinfo = device_get_ivars(pdev->dev.bsddev); 240 rl = &dinfo->resources; 241 return resource_list_find(rl, type, rid); 242 } 243 244 static inline struct resource_list_entry * 245 linux_pci_get_bar(struct pci_dev *pdev, int bar) 246 { 247 struct resource_list_entry *rle; 248 249 bar = PCIR_BAR(bar); 250 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 251 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 252 return (rle); 253 } 254 255 static inline struct device * 256 linux_pci_find_irq_dev(unsigned int irq) 257 { 258 struct pci_dev *pdev; 259 struct device *found; 260 261 found = NULL; 262 spin_lock(&pci_lock); 263 list_for_each_entry(pdev, &pci_devices, links) { 264 if (irq == pdev->dev.irq || 265 (irq >= pdev->dev.msix && irq < pdev->dev.msix_max)) { 266 found = &pdev->dev; 267 break; 268 } 269 } 270 spin_unlock(&pci_lock); 271 return (found); 272 } 273 274 static inline int 275 pci_resource_type(struct pci_dev *pdev, int bar) 276 { 277 struct pci_map *pm; 278 279 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 280 if (!pm) 281 return (-1); 282 283 if (PCI_BAR_IO(pm->pm_value)) 284 return (SYS_RES_IOPORT); 285 else 286 return (SYS_RES_MEMORY); 287 } 288 289 /* 290 * All drivers just seem to want to inspect the type not flags. 291 */ 292 static inline int 293 pci_resource_flags(struct pci_dev *pdev, int bar) 294 { 295 int type; 296 297 type = pci_resource_type(pdev, bar); 298 if (type < 0) 299 return (0); 300 return (1 << type); 301 } 302 303 static inline const char * 304 pci_name(struct pci_dev *d) 305 { 306 307 return device_get_desc(d->dev.bsddev); 308 } 309 310 static inline void * 311 pci_get_drvdata(struct pci_dev *pdev) 312 { 313 314 return dev_get_drvdata(&pdev->dev); 315 } 316 317 static inline void 318 pci_set_drvdata(struct pci_dev *pdev, void *data) 319 { 320 321 dev_set_drvdata(&pdev->dev, data); 322 } 323 324 static inline int 325 pci_enable_device(struct pci_dev *pdev) 326 { 327 328 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 329 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 330 return (0); 331 } 332 333 static inline void 334 pci_disable_device(struct pci_dev *pdev) 335 { 336 337 pci_disable_busmaster(pdev->dev.bsddev); 338 } 339 340 static inline int 341 pci_set_master(struct pci_dev *pdev) 342 { 343 344 pci_enable_busmaster(pdev->dev.bsddev); 345 return (0); 346 } 347 348 static inline int 349 pci_set_power_state(struct pci_dev *pdev, int state) 350 { 351 352 pci_set_powerstate(pdev->dev.bsddev, state); 353 return (0); 354 } 355 356 static inline int 357 pci_clear_master(struct pci_dev *pdev) 358 { 359 360 pci_disable_busmaster(pdev->dev.bsddev); 361 return (0); 362 } 363 364 static inline int 365 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 366 { 367 int rid; 368 int type; 369 370 type = pci_resource_type(pdev, bar); 371 if (type < 0) 372 return (-ENODEV); 373 rid = PCIR_BAR(bar); 374 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 375 RF_ACTIVE) == NULL) 376 return (-EINVAL); 377 return (0); 378 } 379 380 static inline void 381 pci_release_region(struct pci_dev *pdev, int bar) 382 { 383 struct resource_list_entry *rle; 384 385 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 386 return; 387 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 388 } 389 390 static inline void 391 pci_release_regions(struct pci_dev *pdev) 392 { 393 int i; 394 395 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 396 pci_release_region(pdev, i); 397 } 398 399 static inline int 400 pci_request_regions(struct pci_dev *pdev, const char *res_name) 401 { 402 int error; 403 int i; 404 405 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 406 error = pci_request_region(pdev, i, res_name); 407 if (error && error != -ENODEV) { 408 pci_release_regions(pdev); 409 return (error); 410 } 411 } 412 return (0); 413 } 414 415 static inline void 416 pci_disable_msix(struct pci_dev *pdev) 417 { 418 419 pci_release_msi(pdev->dev.bsddev); 420 421 /* 422 * The MSIX IRQ numbers associated with this PCI device are no 423 * longer valid and might be re-assigned. Make sure 424 * linux_pci_find_irq_dev() does no longer see them by 425 * resetting their references to zero: 426 */ 427 pdev->dev.msix = 0; 428 pdev->dev.msix_max = 0; 429 } 430 431 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 432 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 433 434 static inline bus_addr_t 435 pci_bus_address(struct pci_dev *pdev, int bar) 436 { 437 438 return (pci_resource_start(pdev, bar)); 439 } 440 441 #define PCI_CAP_ID_EXP PCIY_EXPRESS 442 #define PCI_CAP_ID_PCIX PCIY_PCIX 443 #define PCI_CAP_ID_AGP PCIY_AGP 444 #define PCI_CAP_ID_PM PCIY_PMG 445 446 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 447 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 448 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 449 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 450 #define PCI_EXP_LNKSTA PCIER_LINK_STA 451 452 static inline int 453 pci_find_capability(struct pci_dev *pdev, int capid) 454 { 455 int reg; 456 457 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 458 return (0); 459 return (reg); 460 } 461 462 static inline int pci_pcie_cap(struct pci_dev *dev) 463 { 464 return pci_find_capability(dev, PCI_CAP_ID_EXP); 465 } 466 467 468 static inline int 469 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 470 { 471 472 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 473 return (0); 474 } 475 476 static inline int 477 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 478 { 479 480 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 481 return (0); 482 } 483 484 static inline int 485 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 486 { 487 488 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 489 return (0); 490 } 491 492 static inline int 493 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 494 { 495 496 pci_write_config(pdev->dev.bsddev, where, val, 1); 497 return (0); 498 } 499 500 static inline int 501 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 502 { 503 504 pci_write_config(pdev->dev.bsddev, where, val, 2); 505 return (0); 506 } 507 508 static inline int 509 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 510 { 511 512 pci_write_config(pdev->dev.bsddev, where, val, 4); 513 return (0); 514 } 515 516 int linux_pci_register_driver(struct pci_driver *pdrv); 517 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 518 void linux_pci_unregister_driver(struct pci_driver *pdrv); 519 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 520 521 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 522 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 523 524 struct msix_entry { 525 int entry; 526 int vector; 527 }; 528 529 /* 530 * Enable msix, positive errors indicate actual number of available 531 * vectors. Negative errors are failures. 532 * 533 * NB: define added to prevent this definition of pci_enable_msix from 534 * clashing with the native FreeBSD version. 535 */ 536 #define pci_enable_msix(...) \ 537 linux_pci_enable_msix(__VA_ARGS__) 538 539 static inline int 540 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 541 { 542 struct resource_list_entry *rle; 543 int error; 544 int avail; 545 int i; 546 547 avail = pci_msix_count(pdev->dev.bsddev); 548 if (avail < nreq) { 549 if (avail == 0) 550 return -EINVAL; 551 return avail; 552 } 553 avail = nreq; 554 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 555 return error; 556 /* 557 * Handle case where "pci_alloc_msix()" may allocate less 558 * interrupts than available and return with no error: 559 */ 560 if (avail < nreq) { 561 pci_release_msi(pdev->dev.bsddev); 562 return avail; 563 } 564 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 565 pdev->dev.msix = rle->start; 566 pdev->dev.msix_max = rle->start + avail; 567 for (i = 0; i < nreq; i++) 568 entries[i].vector = pdev->dev.msix + i; 569 return (0); 570 } 571 572 #define pci_enable_msix_range(...) \ 573 linux_pci_enable_msix_range(__VA_ARGS__) 574 575 static inline int 576 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 577 int minvec, int maxvec) 578 { 579 int nvec = maxvec; 580 int rc; 581 582 if (maxvec < minvec) 583 return (-ERANGE); 584 585 do { 586 rc = pci_enable_msix(dev, entries, nvec); 587 if (rc < 0) { 588 return (rc); 589 } else if (rc > 0) { 590 if (rc < minvec) 591 return (-ENOSPC); 592 nvec = rc; 593 } 594 } while (rc); 595 return (nvec); 596 } 597 598 static inline int 599 pci_channel_offline(struct pci_dev *pdev) 600 { 601 602 return (pci_get_vendor(pdev->dev.bsddev) == PCIV_INVALID); 603 } 604 605 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 606 { 607 return -ENODEV; 608 } 609 static inline void pci_disable_sriov(struct pci_dev *dev) 610 { 611 } 612 613 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 614 const struct pci_device_id _table[] __devinitdata 615 616 617 /* XXX This should not be necessary. */ 618 #define pcix_set_mmrbc(d, v) 0 619 #define pcix_get_max_mmrbc(d) 0 620 #define pcie_set_readrq(d, v) pci_set_max_read_req(&(d)->dev, (v)) 621 622 #define PCI_DMA_BIDIRECTIONAL 0 623 #define PCI_DMA_TODEVICE 1 624 #define PCI_DMA_FROMDEVICE 2 625 #define PCI_DMA_NONE 3 626 627 #define pci_pool dma_pool 628 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 629 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 630 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 631 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 632 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 633 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 634 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 635 _size, _vaddr, _dma_handle) 636 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 637 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 638 _sg, _nents, (enum dma_data_direction)_dir) 639 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 640 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 641 (_ptr), (_size), (enum dma_data_direction)_dir) 642 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 643 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 644 _addr, _size, (enum dma_data_direction)_dir) 645 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 646 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 647 _sg, _nents, (enum dma_data_direction)_dir) 648 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 649 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 650 _offset, _size, (enum dma_data_direction)_dir) 651 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 652 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 653 _dma_address, _size, (enum dma_data_direction)_dir) 654 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 655 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 656 dma_mapping_error(&(_pdev)->dev, _dma_addr) 657 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 658 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 659 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 660 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 661 #define pci_unmap_addr dma_unmap_addr 662 #define pci_unmap_addr_set dma_unmap_addr_set 663 #define pci_unmap_len dma_unmap_len 664 #define pci_unmap_len_set dma_unmap_len_set 665 666 typedef unsigned int __bitwise pci_channel_state_t; 667 typedef unsigned int __bitwise pci_ers_result_t; 668 669 enum pci_channel_state { 670 pci_channel_io_normal = 1, 671 pci_channel_io_frozen = 2, 672 pci_channel_io_perm_failure = 3, 673 }; 674 675 enum pci_ers_result { 676 PCI_ERS_RESULT_NONE = 1, 677 PCI_ERS_RESULT_CAN_RECOVER = 2, 678 PCI_ERS_RESULT_NEED_RESET = 3, 679 PCI_ERS_RESULT_DISCONNECT = 4, 680 PCI_ERS_RESULT_RECOVERED = 5, 681 }; 682 683 684 /* PCI bus error event callbacks */ 685 struct pci_error_handlers { 686 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 687 enum pci_channel_state error); 688 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 689 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 690 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 691 void (*resume)(struct pci_dev *dev); 692 }; 693 694 /* FreeBSD does not support SRIOV - yet */ 695 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 696 { 697 return dev; 698 } 699 700 static inline bool pci_is_pcie(struct pci_dev *dev) 701 { 702 return !!pci_pcie_cap(dev); 703 } 704 705 static inline u16 pcie_flags_reg(struct pci_dev *dev) 706 { 707 int pos; 708 u16 reg16; 709 710 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 711 if (!pos) 712 return 0; 713 714 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 715 716 return reg16; 717 } 718 719 720 static inline int pci_pcie_type(struct pci_dev *dev) 721 { 722 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 723 } 724 725 static inline int pcie_cap_version(struct pci_dev *dev) 726 { 727 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 728 } 729 730 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 731 { 732 int type = pci_pcie_type(dev); 733 734 return pcie_cap_version(dev) > 1 || 735 type == PCI_EXP_TYPE_ROOT_PORT || 736 type == PCI_EXP_TYPE_ENDPOINT || 737 type == PCI_EXP_TYPE_LEG_END; 738 } 739 740 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 741 { 742 return true; 743 } 744 745 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 746 { 747 int type = pci_pcie_type(dev); 748 749 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 750 (type == PCI_EXP_TYPE_DOWNSTREAM && 751 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 752 } 753 754 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 755 { 756 int type = pci_pcie_type(dev); 757 758 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 759 type == PCI_EXP_TYPE_RC_EC; 760 } 761 762 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 763 { 764 if (!pci_is_pcie(dev)) 765 return false; 766 767 switch (pos) { 768 case PCI_EXP_FLAGS_TYPE: 769 return true; 770 case PCI_EXP_DEVCAP: 771 case PCI_EXP_DEVCTL: 772 case PCI_EXP_DEVSTA: 773 return pcie_cap_has_devctl(dev); 774 case PCI_EXP_LNKCAP: 775 case PCI_EXP_LNKCTL: 776 case PCI_EXP_LNKSTA: 777 return pcie_cap_has_lnkctl(dev); 778 case PCI_EXP_SLTCAP: 779 case PCI_EXP_SLTCTL: 780 case PCI_EXP_SLTSTA: 781 return pcie_cap_has_sltctl(dev); 782 case PCI_EXP_RTCTL: 783 case PCI_EXP_RTCAP: 784 case PCI_EXP_RTSTA: 785 return pcie_cap_has_rtctl(dev); 786 case PCI_EXP_DEVCAP2: 787 case PCI_EXP_DEVCTL2: 788 case PCI_EXP_LNKCAP2: 789 case PCI_EXP_LNKCTL2: 790 case PCI_EXP_LNKSTA2: 791 return pcie_cap_version(dev) > 1; 792 default: 793 return false; 794 } 795 } 796 797 static inline int 798 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 799 { 800 if (pos & 3) 801 return -EINVAL; 802 803 if (!pcie_capability_reg_implemented(dev, pos)) 804 return -EINVAL; 805 806 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 807 } 808 809 static inline int 810 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 811 { 812 if (pos & 3) 813 return -EINVAL; 814 815 if (!pcie_capability_reg_implemented(dev, pos)) 816 return -EINVAL; 817 818 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 819 } 820 821 static inline int 822 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 823 { 824 if (pos & 1) 825 return -EINVAL; 826 827 if (!pcie_capability_reg_implemented(dev, pos)) 828 return 0; 829 830 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 831 } 832 833 static inline int pcie_get_minimum_link(struct pci_dev *dev, 834 enum pci_bus_speed *speed, enum pcie_link_width *width) 835 { 836 *speed = PCI_SPEED_UNKNOWN; 837 *width = PCIE_LNK_WIDTH_UNKNOWN; 838 return (0); 839 } 840 841 static inline int 842 pci_num_vf(struct pci_dev *dev) 843 { 844 return (0); 845 } 846 847 static inline enum pci_bus_speed 848 pcie_get_speed_cap(struct pci_dev *dev) 849 { 850 device_t root; 851 uint32_t lnkcap, lnkcap2; 852 int error, pos; 853 854 root = device_get_parent(dev->dev.bsddev); 855 if (root == NULL) 856 return (PCI_SPEED_UNKNOWN); 857 root = device_get_parent(root); 858 if (root == NULL) 859 return (PCI_SPEED_UNKNOWN); 860 root = device_get_parent(root); 861 if (root == NULL) 862 return (PCI_SPEED_UNKNOWN); 863 864 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 865 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 866 return (PCI_SPEED_UNKNOWN); 867 868 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 869 return (PCI_SPEED_UNKNOWN); 870 871 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 872 873 if (lnkcap2) { /* PCIe r3.0-compliant */ 874 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 875 return (PCIE_SPEED_2_5GT); 876 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 877 return (PCIE_SPEED_5_0GT); 878 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 879 return (PCIE_SPEED_8_0GT); 880 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 881 return (PCIE_SPEED_16_0GT); 882 } else { /* pre-r3.0 */ 883 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 884 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 885 return (PCIE_SPEED_2_5GT); 886 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 887 return (PCIE_SPEED_5_0GT); 888 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 889 return (PCIE_SPEED_8_0GT); 890 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 891 return (PCIE_SPEED_16_0GT); 892 } 893 return (PCI_SPEED_UNKNOWN); 894 } 895 896 static inline enum pcie_link_width 897 pcie_get_width_cap(struct pci_dev *dev) 898 { 899 uint32_t lnkcap; 900 901 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 902 if (lnkcap) 903 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 904 905 return (PCIE_LNK_WIDTH_UNKNOWN); 906 } 907 908 #endif /* _LINUX_PCI_H_ */ 909