1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/module.h> 43 #include <sys/nv.h> 44 #include <sys/pciio.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pci_private.h> 48 49 #include <machine/resource.h> 50 51 #include <linux/list.h> 52 #include <linux/dmapool.h> 53 #include <linux/dma-mapping.h> 54 #include <linux/compiler.h> 55 #include <linux/errno.h> 56 #include <asm/atomic.h> 57 #include <asm/memtype.h> 58 #include <linux/device.h> 59 #include <linux/pci_ids.h> 60 #include <linux/pm.h> 61 62 struct pci_device_id { 63 uint32_t vendor; 64 uint32_t device; 65 uint32_t subvendor; 66 uint32_t subdevice; 67 uint32_t class; 68 uint32_t class_mask; 69 uintptr_t driver_data; 70 }; 71 72 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 73 #define MODULE_DEVICE_TABLE(_bus, _table) \ 74 \ 75 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 76 DEVMETHOD_END \ 77 }; \ 78 \ 79 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 80 "lkpi_" #_bus #_table, \ 81 _ ## _bus ## _ ## _table ## _methods, \ 82 0 \ 83 }; \ 84 \ 85 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 86 0, 0); \ 87 \ 88 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 89 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 90 91 #define PCI_ANY_ID -1U 92 93 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 94 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 95 #define PCI_FUNC(devfn) ((devfn) & 0x07) 96 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 97 98 #define PCI_VDEVICE(_vendor, _device) \ 99 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 100 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 101 #define PCI_DEVICE(_vendor, _device) \ 102 .vendor = (_vendor), .device = (_device), \ 103 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 104 105 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 106 107 #define PCI_STD_NUM_BARS 6 108 #define PCI_VENDOR_ID PCIR_VENDOR 109 #define PCI_DEVICE_ID PCIR_DEVICE 110 #define PCI_COMMAND PCIR_COMMAND 111 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 112 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 115 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 116 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 117 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 118 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 119 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 120 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 121 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 122 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 123 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 124 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 125 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 126 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 127 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 128 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 129 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 130 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 131 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 132 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 133 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 134 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 135 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 136 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 137 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 138 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 139 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 140 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 141 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 142 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 143 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 144 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 145 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 146 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 147 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 148 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 149 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 150 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 151 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 152 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 153 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 154 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 155 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 156 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 157 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 158 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 159 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 160 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 161 #define PCI_EXP_LNKCTL2_TLS 0x000f 162 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 163 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 164 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 165 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 166 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 167 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 168 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 169 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 170 171 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 172 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 173 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 174 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 175 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 176 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 177 178 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 179 #define PCI_EXP_DEVSTA_TRPND 0x0020 180 181 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 182 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 183 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 184 185 enum pci_bus_speed { 186 PCI_SPEED_UNKNOWN = -1, 187 PCIE_SPEED_2_5GT, 188 PCIE_SPEED_5_0GT, 189 PCIE_SPEED_8_0GT, 190 PCIE_SPEED_16_0GT, 191 PCIE_SPEED_32_0GT, 192 PCIE_SPEED_64_0GT, 193 }; 194 195 enum pcie_link_width { 196 PCIE_LNK_WIDTH_RESRV = 0x00, 197 PCIE_LNK_X1 = 0x01, 198 PCIE_LNK_X2 = 0x02, 199 PCIE_LNK_X4 = 0x04, 200 PCIE_LNK_X8 = 0x08, 201 PCIE_LNK_X12 = 0x0c, 202 PCIE_LNK_X16 = 0x10, 203 PCIE_LNK_X32 = 0x20, 204 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 205 }; 206 207 #define PCIE_LINK_STATE_L0S 0x00000001 208 #define PCIE_LINK_STATE_L1 0x00000002 209 #define PCIE_LINK_STATE_CLKPM 0x00000004 210 211 typedef int pci_power_t; 212 213 #define PCI_D0 PCI_POWERSTATE_D0 214 #define PCI_D1 PCI_POWERSTATE_D1 215 #define PCI_D2 PCI_POWERSTATE_D2 216 #define PCI_D3hot PCI_POWERSTATE_D3 217 #define PCI_D3cold 4 218 219 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 220 221 extern const char *pci_power_names[6]; 222 223 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 224 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 225 226 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 227 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 228 229 #define PCI_L1SS_CTL1 0x8 230 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 231 232 #define PCI_IRQ_LEGACY 0x01 233 #define PCI_IRQ_MSI 0x02 234 #define PCI_IRQ_MSIX 0x04 235 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 236 237 struct pci_dev; 238 239 struct pci_driver { 240 struct list_head node; 241 char *name; 242 const struct pci_device_id *id_table; 243 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 244 void (*remove)(struct pci_dev *dev); 245 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 246 int (*resume) (struct pci_dev *dev); /* Device woken up */ 247 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 248 driver_t bsddriver; 249 devclass_t bsdclass; 250 struct device_driver driver; 251 const struct pci_error_handlers *err_handler; 252 bool isdrm; 253 int bsd_probe_return; 254 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 255 const nvlist_t *pf_config); 256 void (*bsd_iov_uninit)(device_t dev); 257 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 258 const nvlist_t *vf_config); 259 }; 260 261 struct pci_bus { 262 struct pci_dev *self; 263 /* struct pci_bus *parent */ 264 int domain; 265 int number; 266 }; 267 268 extern struct list_head pci_drivers; 269 extern struct list_head pci_devices; 270 extern spinlock_t pci_lock; 271 272 #define __devexit_p(x) x 273 274 #define module_pci_driver(_driver) \ 275 \ 276 static inline int \ 277 _pci_init(void) \ 278 { \ 279 \ 280 return (linux_pci_register_driver(&_driver)); \ 281 } \ 282 \ 283 static inline void \ 284 _pci_exit(void) \ 285 { \ 286 \ 287 linux_pci_unregister_driver(&_driver); \ 288 } \ 289 \ 290 module_init(_pci_init); \ 291 module_exit(_pci_exit) 292 293 struct msi_msg { 294 uint32_t data; 295 }; 296 297 struct pci_msi_desc { 298 struct { 299 bool is_64; 300 } msi_attrib; 301 }; 302 303 struct msi_desc { 304 struct msi_msg msg; 305 struct pci_msi_desc pci; 306 }; 307 308 struct msix_entry { 309 int entry; 310 int vector; 311 }; 312 313 /* 314 * If we find drivers accessing this from multiple KPIs we may have to 315 * refcount objects of this structure. 316 */ 317 struct resource; 318 struct pci_mmio_region { 319 TAILQ_ENTRY(pci_mmio_region) next; 320 struct resource *res; 321 int rid; 322 int type; 323 }; 324 325 struct pci_dev { 326 struct device dev; 327 struct list_head links; 328 struct pci_driver *pdrv; 329 struct pci_bus *bus; 330 struct pci_dev *root; 331 pci_power_t current_state; 332 uint16_t device; 333 uint16_t vendor; 334 uint16_t subsystem_vendor; 335 uint16_t subsystem_device; 336 unsigned int irq; 337 unsigned int devfn; 338 uint32_t class; 339 uint8_t revision; 340 uint8_t msi_cap; 341 uint8_t msix_cap; 342 bool managed; /* devres "pcim_*(). */ 343 bool want_iomap_res; 344 bool msi_enabled; 345 bool msix_enabled; 346 phys_addr_t rom; 347 size_t romlen; 348 struct msi_desc **msi_desc; 349 char *path_name; 350 spinlock_t pcie_cap_lock; 351 352 TAILQ_HEAD(, pci_mmio_region) mmio; 353 }; 354 355 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 356 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 357 unsigned int flags); 358 bool pci_device_is_present(struct pci_dev *pdev); 359 360 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 361 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 362 void *linuxkpi_pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size); 363 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 364 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 365 const char *name); 366 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 367 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 368 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 369 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 370 int nreq); 371 372 /* Internal helper function(s). */ 373 struct pci_dev *lkpinew_pci_dev(device_t); 374 void lkpi_pci_devres_release(struct device *, void *); 375 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 376 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 377 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 378 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 379 380 static inline bool 381 dev_is_pci(struct device *dev) 382 { 383 384 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 385 } 386 387 static inline int 388 pci_resource_type(struct pci_dev *pdev, int bar) 389 { 390 struct pci_map *pm; 391 392 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 393 if (!pm) 394 return (-1); 395 396 if (PCI_BAR_IO(pm->pm_value)) 397 return (SYS_RES_IOPORT); 398 else 399 return (SYS_RES_MEMORY); 400 } 401 402 /* 403 * All drivers just seem to want to inspect the type not flags. 404 */ 405 static inline int 406 pci_resource_flags(struct pci_dev *pdev, int bar) 407 { 408 int type; 409 410 type = pci_resource_type(pdev, bar); 411 if (type < 0) 412 return (0); 413 return (1 << type); 414 } 415 416 static inline const char * 417 pci_name(struct pci_dev *d) 418 { 419 return d->path_name; 420 } 421 422 static inline void * 423 pci_get_drvdata(struct pci_dev *pdev) 424 { 425 426 return dev_get_drvdata(&pdev->dev); 427 } 428 429 static inline void 430 pci_set_drvdata(struct pci_dev *pdev, void *data) 431 { 432 433 dev_set_drvdata(&pdev->dev, data); 434 } 435 436 static inline struct pci_dev * 437 pci_dev_get(struct pci_dev *pdev) 438 { 439 440 if (pdev != NULL) 441 get_device(&pdev->dev); 442 return (pdev); 443 } 444 445 static __inline void 446 pci_dev_put(struct pci_dev *pdev) 447 { 448 449 if (pdev != NULL) 450 put_device(&pdev->dev); 451 } 452 453 static inline int 454 pci_enable_device(struct pci_dev *pdev) 455 { 456 457 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 458 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 459 return (0); 460 } 461 462 static inline void 463 pci_disable_device(struct pci_dev *pdev) 464 { 465 466 pci_disable_busmaster(pdev->dev.bsddev); 467 } 468 469 static inline int 470 pci_set_master(struct pci_dev *pdev) 471 { 472 473 pci_enable_busmaster(pdev->dev.bsddev); 474 return (0); 475 } 476 477 static inline int 478 pci_set_power_state(struct pci_dev *pdev, int state) 479 { 480 481 pci_set_powerstate(pdev->dev.bsddev, state); 482 return (0); 483 } 484 485 static inline int 486 pci_clear_master(struct pci_dev *pdev) 487 { 488 489 pci_disable_busmaster(pdev->dev.bsddev); 490 return (0); 491 } 492 493 static inline bool 494 pci_is_root_bus(struct pci_bus *pbus) 495 { 496 497 return (pbus->self == NULL); 498 } 499 500 static inline struct pci_dev * 501 pci_upstream_bridge(struct pci_dev *pdev) 502 { 503 504 if (pci_is_root_bus(pdev->bus)) 505 return (NULL); 506 507 /* 508 * If we do not have a (proper) "upstream bridge" set, e.g., we point 509 * to ourselves, try to handle this case on the fly like we do 510 * for pcie_find_root_port(). 511 */ 512 if (pdev == pdev->bus->self) { 513 device_t bridge; 514 515 bridge = device_get_parent(pdev->dev.bsddev); 516 if (bridge == NULL) 517 goto done; 518 bridge = device_get_parent(bridge); 519 if (bridge == NULL) 520 goto done; 521 if (device_get_devclass(device_get_parent(bridge)) != 522 devclass_find("pci")) 523 goto done; 524 525 /* 526 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 527 * for it so it can be returned. 528 */ 529 pdev->bus->self = lkpinew_pci_dev(bridge); 530 } 531 done: 532 return (pdev->bus->self); 533 } 534 535 #define pci_release_region(pdev, bar) linuxkpi_pci_release_region(pdev, bar) 536 #define pci_release_regions(pdev) linuxkpi_pci_release_regions(pdev) 537 #define pci_request_regions(pdev, res_name) \ 538 linuxkpi_pci_request_regions(pdev, res_name) 539 540 static inline void 541 lkpi_pci_disable_msix(struct pci_dev *pdev) 542 { 543 544 pci_release_msi(pdev->dev.bsddev); 545 546 /* 547 * The MSIX IRQ numbers associated with this PCI device are no 548 * longer valid and might be re-assigned. Make sure 549 * lkpi_pci_find_irq_dev() does no longer see them by 550 * resetting their references to zero: 551 */ 552 pdev->dev.irq_start = 0; 553 pdev->dev.irq_end = 0; 554 pdev->msix_enabled = false; 555 } 556 /* Only for consistency. No conflict on that one. */ 557 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 558 559 static inline void 560 lkpi_pci_disable_msi(struct pci_dev *pdev) 561 { 562 563 pci_release_msi(pdev->dev.bsddev); 564 565 pdev->dev.irq_start = 0; 566 pdev->dev.irq_end = 0; 567 pdev->irq = pdev->dev.irq; 568 pdev->msi_enabled = false; 569 } 570 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 571 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 572 573 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 574 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 575 576 static inline bus_addr_t 577 pci_bus_address(struct pci_dev *pdev, int bar) 578 { 579 580 return (pci_resource_start(pdev, bar)); 581 } 582 583 #define PCI_CAP_ID_EXP PCIY_EXPRESS 584 #define PCI_CAP_ID_PCIX PCIY_PCIX 585 #define PCI_CAP_ID_AGP PCIY_AGP 586 #define PCI_CAP_ID_PM PCIY_PMG 587 588 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 589 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 590 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 591 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 592 #define PCI_EXP_LNKSTA PCIER_LINK_STA 593 594 static inline int 595 pci_find_capability(struct pci_dev *pdev, int capid) 596 { 597 int reg; 598 599 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 600 return (0); 601 return (reg); 602 } 603 604 static inline int pci_pcie_cap(struct pci_dev *dev) 605 { 606 return pci_find_capability(dev, PCI_CAP_ID_EXP); 607 } 608 609 static inline int 610 pci_find_ext_capability(struct pci_dev *pdev, int capid) 611 { 612 int reg; 613 614 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 615 return (0); 616 return (reg); 617 } 618 619 #define PCIM_PCAP_PME_SHIFT 11 620 static __inline bool 621 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 622 { 623 struct pci_devinfo *dinfo; 624 pcicfgregs *cfg; 625 626 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 627 return (false); 628 629 dinfo = device_get_ivars(pdev->dev.bsddev); 630 cfg = &dinfo->cfg; 631 632 if (cfg->pp.pp_cap == 0) 633 return (false); 634 635 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 636 return (true); 637 638 return (false); 639 } 640 641 static inline int 642 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 643 { 644 645 if (!pci_enable_aspm) 646 return (-EPERM); 647 648 return (-ENXIO); 649 } 650 651 static inline int 652 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 653 { 654 655 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 656 return (0); 657 } 658 659 static inline int 660 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 661 { 662 663 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 664 return (0); 665 } 666 667 static inline int 668 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 669 { 670 671 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 672 return (0); 673 } 674 675 static inline int 676 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 677 { 678 679 pci_write_config(pdev->dev.bsddev, where, val, 1); 680 return (0); 681 } 682 683 static inline int 684 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 685 { 686 687 pci_write_config(pdev->dev.bsddev, where, val, 2); 688 return (0); 689 } 690 691 static inline int 692 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 693 { 694 695 pci_write_config(pdev->dev.bsddev, where, val, 4); 696 return (0); 697 } 698 699 int linux_pci_register_driver(struct pci_driver *pdrv); 700 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 701 void linux_pci_unregister_driver(struct pci_driver *pdrv); 702 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 703 704 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 705 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 706 707 /* 708 * Enable msix, positive errors indicate actual number of available 709 * vectors. Negative errors are failures. 710 * 711 * NB: define added to prevent this definition of pci_enable_msix from 712 * clashing with the native FreeBSD version. 713 */ 714 #define pci_enable_msix(...) linuxkpi_pci_enable_msix(__VA_ARGS__) 715 716 #define pci_enable_msix_range(...) \ 717 linux_pci_enable_msix_range(__VA_ARGS__) 718 719 static inline int 720 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 721 int minvec, int maxvec) 722 { 723 int nvec = maxvec; 724 int rc; 725 726 if (maxvec < minvec) 727 return (-ERANGE); 728 729 do { 730 rc = pci_enable_msix(dev, entries, nvec); 731 if (rc < 0) { 732 return (rc); 733 } else if (rc > 0) { 734 if (rc < minvec) 735 return (-ENOSPC); 736 nvec = rc; 737 } 738 } while (rc); 739 return (nvec); 740 } 741 742 #define pci_enable_msi(pdev) \ 743 linux_pci_enable_msi(pdev) 744 745 static inline int 746 pci_enable_msi(struct pci_dev *pdev) 747 { 748 749 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 750 } 751 752 static inline int 753 pci_channel_offline(struct pci_dev *pdev) 754 { 755 756 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 757 } 758 759 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 760 { 761 return -ENODEV; 762 } 763 764 static inline void pci_disable_sriov(struct pci_dev *dev) 765 { 766 } 767 768 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 769 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 770 #define pci_iounmap(pdev, res) linuxkpi_pci_iounmap(pdev, res) 771 772 static inline void 773 lkpi_pci_save_state(struct pci_dev *pdev) 774 { 775 776 pci_save_state(pdev->dev.bsddev); 777 } 778 779 static inline void 780 lkpi_pci_restore_state(struct pci_dev *pdev) 781 { 782 783 pci_restore_state(pdev->dev.bsddev); 784 } 785 786 #define pci_save_state(dev) lkpi_pci_save_state(dev) 787 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 788 789 static inline int 790 pci_reset_function(struct pci_dev *pdev) 791 { 792 793 return (-ENOSYS); 794 } 795 796 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 797 const struct pci_device_id _table[] __devinitdata 798 799 /* XXX This should not be necessary. */ 800 #define pcix_set_mmrbc(d, v) 0 801 #define pcix_get_max_mmrbc(d) 0 802 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 803 804 #define PCI_DMA_BIDIRECTIONAL 0 805 #define PCI_DMA_TODEVICE 1 806 #define PCI_DMA_FROMDEVICE 2 807 #define PCI_DMA_NONE 3 808 809 #define pci_pool dma_pool 810 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 811 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 812 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 813 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 814 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 815 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 816 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 817 _size, _vaddr, _dma_handle) 818 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 819 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 820 _sg, _nents, (enum dma_data_direction)_dir) 821 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 822 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 823 (_ptr), (_size), (enum dma_data_direction)_dir) 824 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 825 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 826 _addr, _size, (enum dma_data_direction)_dir) 827 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 828 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 829 _sg, _nents, (enum dma_data_direction)_dir) 830 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 831 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 832 _offset, _size, (enum dma_data_direction)_dir) 833 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 834 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 835 _dma_address, _size, (enum dma_data_direction)_dir) 836 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 837 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 838 dma_mapping_error(&(_pdev)->dev, _dma_addr) 839 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 840 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 841 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 842 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 843 #define pci_unmap_addr dma_unmap_addr 844 #define pci_unmap_addr_set dma_unmap_addr_set 845 #define pci_unmap_len dma_unmap_len 846 #define pci_unmap_len_set dma_unmap_len_set 847 848 typedef unsigned int __bitwise pci_channel_state_t; 849 typedef unsigned int __bitwise pci_ers_result_t; 850 851 enum pci_channel_state { 852 pci_channel_io_normal = 1, 853 pci_channel_io_frozen = 2, 854 pci_channel_io_perm_failure = 3, 855 }; 856 857 enum pci_ers_result { 858 PCI_ERS_RESULT_NONE = 1, 859 PCI_ERS_RESULT_CAN_RECOVER = 2, 860 PCI_ERS_RESULT_NEED_RESET = 3, 861 PCI_ERS_RESULT_DISCONNECT = 4, 862 PCI_ERS_RESULT_RECOVERED = 5, 863 }; 864 865 /* PCI bus error event callbacks */ 866 struct pci_error_handlers { 867 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 868 enum pci_channel_state error); 869 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 870 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 871 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 872 void (*resume)(struct pci_dev *dev); 873 }; 874 875 /* FreeBSD does not support SRIOV - yet */ 876 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 877 { 878 return dev; 879 } 880 881 static inline bool pci_is_pcie(struct pci_dev *dev) 882 { 883 return !!pci_pcie_cap(dev); 884 } 885 886 static inline u16 pcie_flags_reg(struct pci_dev *dev) 887 { 888 int pos; 889 u16 reg16; 890 891 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 892 if (!pos) 893 return 0; 894 895 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 896 897 return reg16; 898 } 899 900 static inline int pci_pcie_type(struct pci_dev *dev) 901 { 902 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 903 } 904 905 static inline int pcie_cap_version(struct pci_dev *dev) 906 { 907 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 908 } 909 910 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 911 { 912 int type = pci_pcie_type(dev); 913 914 return pcie_cap_version(dev) > 1 || 915 type == PCI_EXP_TYPE_ROOT_PORT || 916 type == PCI_EXP_TYPE_ENDPOINT || 917 type == PCI_EXP_TYPE_LEG_END; 918 } 919 920 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 921 { 922 return true; 923 } 924 925 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 926 { 927 int type = pci_pcie_type(dev); 928 929 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 930 (type == PCI_EXP_TYPE_DOWNSTREAM && 931 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 932 } 933 934 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 935 { 936 int type = pci_pcie_type(dev); 937 938 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 939 type == PCI_EXP_TYPE_RC_EC; 940 } 941 942 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 943 { 944 if (!pci_is_pcie(dev)) 945 return false; 946 947 switch (pos) { 948 case PCI_EXP_FLAGS_TYPE: 949 return true; 950 case PCI_EXP_DEVCAP: 951 case PCI_EXP_DEVCTL: 952 case PCI_EXP_DEVSTA: 953 return pcie_cap_has_devctl(dev); 954 case PCI_EXP_LNKCAP: 955 case PCI_EXP_LNKCTL: 956 case PCI_EXP_LNKSTA: 957 return pcie_cap_has_lnkctl(dev); 958 case PCI_EXP_SLTCAP: 959 case PCI_EXP_SLTCTL: 960 case PCI_EXP_SLTSTA: 961 return pcie_cap_has_sltctl(dev); 962 case PCI_EXP_RTCTL: 963 case PCI_EXP_RTCAP: 964 case PCI_EXP_RTSTA: 965 return pcie_cap_has_rtctl(dev); 966 case PCI_EXP_DEVCAP2: 967 case PCI_EXP_DEVCTL2: 968 case PCI_EXP_LNKCAP2: 969 case PCI_EXP_LNKCTL2: 970 case PCI_EXP_LNKSTA2: 971 return pcie_cap_version(dev) > 1; 972 default: 973 return false; 974 } 975 } 976 977 static inline int 978 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 979 { 980 *dst = 0; 981 if (pos & 3) 982 return -EINVAL; 983 984 if (!pcie_capability_reg_implemented(dev, pos)) 985 return -EINVAL; 986 987 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 988 } 989 990 static inline int 991 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 992 { 993 *dst = 0; 994 if (pos & 3) 995 return -EINVAL; 996 997 if (!pcie_capability_reg_implemented(dev, pos)) 998 return -EINVAL; 999 1000 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1001 } 1002 1003 static inline int 1004 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1005 { 1006 if (pos & 1) 1007 return -EINVAL; 1008 1009 if (!pcie_capability_reg_implemented(dev, pos)) 1010 return 0; 1011 1012 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1013 } 1014 1015 static inline int 1016 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1017 uint16_t clear, uint16_t set) 1018 { 1019 int error; 1020 uint16_t v; 1021 1022 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1023 spin_lock(&dev->pcie_cap_lock); 1024 1025 error = pcie_capability_read_word(dev, pos, &v); 1026 if (error == 0) { 1027 v &= ~clear; 1028 v |= set; 1029 error = pcie_capability_write_word(dev, pos, v); 1030 } 1031 1032 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1033 spin_unlock(&dev->pcie_cap_lock); 1034 1035 return (error); 1036 } 1037 1038 static inline int 1039 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1040 { 1041 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1042 } 1043 1044 static inline int 1045 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1046 { 1047 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1048 } 1049 1050 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1051 enum pci_bus_speed *speed, enum pcie_link_width *width) 1052 { 1053 *speed = PCI_SPEED_UNKNOWN; 1054 *width = PCIE_LNK_WIDTH_UNKNOWN; 1055 return (0); 1056 } 1057 1058 static inline int 1059 pci_num_vf(struct pci_dev *dev) 1060 { 1061 return (0); 1062 } 1063 1064 static inline enum pci_bus_speed 1065 pcie_get_speed_cap(struct pci_dev *dev) 1066 { 1067 device_t root; 1068 uint32_t lnkcap, lnkcap2; 1069 int error, pos; 1070 1071 root = device_get_parent(dev->dev.bsddev); 1072 if (root == NULL) 1073 return (PCI_SPEED_UNKNOWN); 1074 root = device_get_parent(root); 1075 if (root == NULL) 1076 return (PCI_SPEED_UNKNOWN); 1077 root = device_get_parent(root); 1078 if (root == NULL) 1079 return (PCI_SPEED_UNKNOWN); 1080 1081 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1082 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1083 return (PCI_SPEED_UNKNOWN); 1084 1085 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1086 return (PCI_SPEED_UNKNOWN); 1087 1088 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1089 1090 if (lnkcap2) { /* PCIe r3.0-compliant */ 1091 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1092 return (PCIE_SPEED_2_5GT); 1093 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1094 return (PCIE_SPEED_5_0GT); 1095 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1096 return (PCIE_SPEED_8_0GT); 1097 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1098 return (PCIE_SPEED_16_0GT); 1099 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1100 return (PCIE_SPEED_32_0GT); 1101 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1102 return (PCIE_SPEED_64_0GT); 1103 } else { /* pre-r3.0 */ 1104 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1105 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1106 return (PCIE_SPEED_2_5GT); 1107 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1108 return (PCIE_SPEED_5_0GT); 1109 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1110 return (PCIE_SPEED_8_0GT); 1111 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1112 return (PCIE_SPEED_16_0GT); 1113 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1114 return (PCIE_SPEED_32_0GT); 1115 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1116 return (PCIE_SPEED_64_0GT); 1117 } 1118 return (PCI_SPEED_UNKNOWN); 1119 } 1120 1121 static inline enum pcie_link_width 1122 pcie_get_width_cap(struct pci_dev *dev) 1123 { 1124 uint32_t lnkcap; 1125 1126 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1127 if (lnkcap) 1128 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1129 1130 return (PCIE_LNK_WIDTH_UNKNOWN); 1131 } 1132 1133 static inline int 1134 pcie_get_mps(struct pci_dev *dev) 1135 { 1136 return (pci_get_max_payload(dev->dev.bsddev)); 1137 } 1138 1139 static inline uint32_t 1140 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1141 { 1142 1143 switch(spd) { 1144 case PCIE_SPEED_64_0GT: 1145 return (64000 * 128 / 130); 1146 case PCIE_SPEED_32_0GT: 1147 return (32000 * 128 / 130); 1148 case PCIE_SPEED_16_0GT: 1149 return (16000 * 128 / 130); 1150 case PCIE_SPEED_8_0GT: 1151 return (8000 * 128 / 130); 1152 case PCIE_SPEED_5_0GT: 1153 return (5000 * 8 / 10); 1154 case PCIE_SPEED_2_5GT: 1155 return (2500 * 8 / 10); 1156 default: 1157 return (0); 1158 } 1159 } 1160 1161 static inline uint32_t 1162 pcie_bandwidth_available(struct pci_dev *pdev, 1163 struct pci_dev **limiting, 1164 enum pci_bus_speed *speed, 1165 enum pcie_link_width *width) 1166 { 1167 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1168 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1169 1170 if (speed) 1171 *speed = nspeed; 1172 if (width) 1173 *width = nwidth; 1174 1175 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1176 } 1177 1178 static inline bool 1179 pcie_aspm_enabled(struct pci_dev *pdev) 1180 { 1181 return (false); 1182 } 1183 1184 static inline struct pci_dev * 1185 pcie_find_root_port(struct pci_dev *pdev) 1186 { 1187 device_t root; 1188 1189 if (pdev->root != NULL) 1190 return (pdev->root); 1191 1192 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1193 if (root == NULL) 1194 return (NULL); 1195 1196 pdev->root = lkpinew_pci_dev(root); 1197 return (pdev->root); 1198 } 1199 1200 /* This is needed when people rip out the device "HotPlug". */ 1201 static inline void 1202 pci_lock_rescan_remove(void) 1203 { 1204 } 1205 1206 static inline void 1207 pci_unlock_rescan_remove(void) 1208 { 1209 } 1210 1211 static __inline void 1212 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1213 { 1214 } 1215 1216 static inline int 1217 pci_rescan_bus(struct pci_bus *pbus) 1218 { 1219 device_t *devlist, parent; 1220 int devcount, error; 1221 1222 if (!device_is_attached(pbus->self->dev.bsddev)) 1223 return (0); 1224 /* pci_rescan_method() will work on the pcib (parent). */ 1225 error = BUS_RESCAN(pbus->self->dev.bsddev); 1226 if (error != 0) 1227 return (0); 1228 1229 parent = device_get_parent(pbus->self->dev.bsddev); 1230 error = device_get_children(parent, &devlist, &devcount); 1231 if (error != 0) 1232 return (0); 1233 if (devcount != 0) 1234 free(devlist, M_TEMP); 1235 1236 return (devcount); 1237 } 1238 1239 /* 1240 * The following functions can be used to attach/detach the LinuxKPI's 1241 * PCI device runtime. The pci_driver and pci_device_id pointer is 1242 * allowed to be NULL. Other pointers must be all valid. 1243 * The pci_dev structure should be zero-initialized before passed 1244 * to the linux_pci_attach_device function. 1245 */ 1246 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1247 const struct pci_device_id *, struct pci_dev *); 1248 extern int linux_pci_detach_device(struct pci_dev *); 1249 1250 static inline int 1251 pci_dev_present(const struct pci_device_id *cur) 1252 { 1253 while (cur != NULL && (cur->vendor || cur->device)) { 1254 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1255 return (1); 1256 } 1257 cur++; 1258 } 1259 return (0); 1260 } 1261 1262 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1263 unsigned int bus, unsigned int devfn); 1264 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1265 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1266 1267 static inline int 1268 pci_domain_nr(struct pci_bus *pbus) 1269 { 1270 1271 return (pbus->domain); 1272 } 1273 1274 static inline int 1275 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1276 int pos, uint32_t *val, int len) 1277 { 1278 1279 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1280 return (0); 1281 } 1282 1283 static inline int 1284 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1285 { 1286 uint32_t tmp; 1287 int ret; 1288 1289 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1290 *val = (u16)tmp; 1291 return (ret); 1292 } 1293 1294 static inline int 1295 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1296 { 1297 uint32_t tmp; 1298 int ret; 1299 1300 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1301 *val = (u8)tmp; 1302 return (ret); 1303 } 1304 1305 static inline int 1306 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1307 uint32_t val, int size) 1308 { 1309 1310 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1311 return (0); 1312 } 1313 1314 static inline int 1315 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1316 uint8_t val) 1317 { 1318 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1319 } 1320 1321 static inline int 1322 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1323 uint16_t val) 1324 { 1325 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1326 } 1327 1328 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1329 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1330 1331 /* -------------------------------------------------------------------------- */ 1332 1333 #define pcim_enable_device(pdev) linuxkpi_pcim_enable_device(pdev) 1334 #define pcim_iomap_table(pdev) linuxkpi_pcim_iomap_table(pdev) 1335 #define pcim_iomap_regions(pdev, mask, name) \ 1336 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1337 1338 static inline int 1339 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1340 { 1341 uint32_t requests, req_mask; 1342 int bar, error; 1343 1344 /* Request all the BARs ("regions") we do not iomap. */ 1345 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1346 for (bar = requests = 0; requests != req_mask; bar++) { 1347 if ((req_mask & (1 << bar)) == 0) 1348 continue; 1349 error = pci_request_region(pdev, bar, name); 1350 if (error != 0 && error != -ENODEV) 1351 goto err; 1352 requests |= (1 << bar); 1353 } 1354 1355 error = pcim_iomap_regions(pdev, mask, name); 1356 if (error != 0) 1357 goto err; 1358 1359 return (0); 1360 1361 err: 1362 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1363 if ((requests & (1 << bar)) != 0) 1364 pci_release_region(pdev, bar); 1365 } 1366 1367 return (-EINVAL); 1368 } 1369 1370 /* 1371 * We cannot simply re-define pci_get_device() as we would normally do 1372 * and then hide it in linux_pci.c as too many semi-native drivers still 1373 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1374 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1375 */ 1376 static inline struct pci_dev * 1377 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1378 { 1379 1380 return (lkpi_pci_get_device(vendor, device, odev)); 1381 } 1382 1383 /* This is a FreeBSD extension so we can use bus_*(). */ 1384 static inline void 1385 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1386 { 1387 pdev->want_iomap_res = true; 1388 } 1389 1390 static inline bool 1391 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1392 { 1393 1394 return (false); 1395 } 1396 1397 static inline void * 1398 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1399 { 1400 1401 return (NULL); 1402 } 1403 1404 static inline void 1405 pci_ignore_hotplug(struct pci_dev *pdev) 1406 { 1407 } 1408 1409 static inline const char * 1410 pci_power_name(pci_power_t state) 1411 { 1412 int pstate = state + 1; 1413 1414 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1415 return (pci_power_names[pstate]); 1416 else 1417 return (pci_power_names[0]); 1418 } 1419 1420 static inline int 1421 pcie_get_readrq(struct pci_dev *dev) 1422 { 1423 u16 ctl; 1424 1425 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1426 return (-EINVAL); 1427 1428 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1429 } 1430 1431 static inline bool 1432 pci_is_enabled(struct pci_dev *pdev) 1433 { 1434 1435 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1436 PCIM_CMD_BUSMASTEREN) != 0); 1437 } 1438 1439 static inline int 1440 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1441 { 1442 1443 return (0); 1444 } 1445 1446 static inline int 1447 pci_assign_resource(struct pci_dev *pdev, int bar) 1448 { 1449 1450 return (0); 1451 } 1452 1453 static inline int 1454 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1455 { 1456 1457 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1458 if (vector != 0) 1459 return (-EINVAL); 1460 return (pdev->irq); 1461 } 1462 1463 if (pdev->msix_enabled || pdev->msi_enabled) { 1464 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1465 return (-EINVAL); 1466 return (pdev->dev.irq_start + vector); 1467 } 1468 1469 return (-ENXIO); 1470 } 1471 1472 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1473